Coding Style cleanup; generate new CHANGELOG file.

Signed-off-by: Wolfgang Denk <wd@denx.de>

5 files changed, 18 insertions, 19 deletions

diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
index 1d2f28d946..d588818fc2 100755
--- a/include/configs/SMN42.h
+++ b/include/configs/SMN42.h
@@ -42,7 +42,7 @@
 #define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
 #define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
 #define CONFIG_LPC2292
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+#undef	CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 
 #undef CONFIG_USE_IRQ			/* don't need them anymore */
 
@@ -66,10 +66,10 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 
 /* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 /* this would be 0xAE if E0, E1 and E2 were pulled high */
 #define CFG_I2C_SLAVE		0xA0
@@ -92,11 +92,11 @@
 #define	I2C_SCL(x)	{ if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
 #define	I2C_DELAY	{ udelay(100); }
 #define	I2C_ACTIVE	{ unsigned int i2ctmp; \
- 					  i2ctmp = GET32(IO0DIR); \
+					  i2ctmp = GET32(IO0DIR); \
 					  i2ctmp |= SDA; \
 					  PUT32(IO0DIR, i2ctmp); }
 #define	I2C_TRISTATE	{ unsigned int i2ctmp; \
- 					      i2ctmp = GET32(IO0DIR); \
+					      i2ctmp = GET32(IO0DIR); \
 					      i2ctmp &= ~SDA; \
 						  PUT32(IO0DIR, i2ctmp); }
 #endif /* CONFIG_SOFT_I2C */
@@ -132,12 +132,12 @@
 #define CFG_MEMTEST_START	0x81800000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x83000000	/* 24 MB in SRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x81000000	/* default load address	
-                                                 * for uClinux img is here*/
+#define	CFG_LOAD_ADDR		0x81000000	/* default load address	*/
+						/* for uClinux img is here*/
 
-#define CFG_SYS_CLK_FREQ        58982400        /* Hz */
+#define CFG_SYS_CLK_FREQ	58982400	/* Hz */
 #define	CFG_HZ			2048		/* decrementer freq in Hz */
 
 						/* valid baudrates */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index b42cfb6e1f..712668ab8a 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -207,7 +207,7 @@
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 6c2a360378..f6f530cedb 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -173,7 +173,7 @@
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 30e0b10f79..7b6c6953e1 100755
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -42,7 +42,7 @@
 #define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
 #define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
 #define CONFIG_LPC2292
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+#undef	CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 
 #undef CONFIG_USE_IRQ			/* don't need them anymore */
 
@@ -66,7 +66,7 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 
 /*
  * Supported commands
@@ -99,13 +99,12 @@
 #define CFG_MEMTEST_START	0x40000000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x40000000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for 
-                                                 * armadillo: kernel img is here
-						 */
+#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for	*/
+						/* armadillo: kernel img is here*/
 
-#define CFG_SYS_CLK_FREQ        58982400        /* Hz */
+#define CFG_SYS_CLK_FREQ	58982400	/* Hz */
 #define	CFG_HZ			2048		/* decrementer freq in Hz */
 
 						/* valid baudrates */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index fd138a5d17..9888d11108 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -226,7 +226,7 @@
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */