diff options
| author | Tom Rini <trini@konsulko.com> | 2022-11-16 13:10:25 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-05 16:05:38 -0500 |
| commit | 0ed384fd2f511fb415b16fb0eb221e9437cd17ee (patch) | |
| tree | 2f6a4e320b5a49c8128e6d61a1f3d75e25e067f1 /include/configs/P1010RDB.h | |
| parent | 4e5909450ec2acafb3d2e5b9714251ae67e0f0e0 (diff) | |
| download | u-boot-0ed384fd2f511fb415b16fb0eb221e9437cd17ee.tar.gz | |
global: Move remaining CONFIG_SYS_NOR_* to CFG_SYS_NOR_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/P1010RDB.h')
| -rw-r--r-- | include/configs/P1010RDB.h | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3288969ce8..154bf584f2 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -144,22 +144,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +#define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ +#define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -244,21 +244,21 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR |