Merge branch 'next'

6 files changed, 22 insertions, 860 deletions

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 965b587927..4ecc158c46 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -583,6 +583,8 @@ config ATMEL_HLCD
 
 source "drivers/video/ti/Kconfig"
 
+source "drivers/video/exynos/Kconfig"
+
 config LOGICORE_DP_TX
 	bool "Enable Logicore DP TX driver"
 	depends on DISPLAY
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 259658074b..7019b26396 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -36,9 +36,7 @@ obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
 obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_OSD) += video_osd-uclass.o
-obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o
-obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
 obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
new file mode 100644
index 0000000000..37e661b1ed
--- /dev/null
+++ b/drivers/video/exynos/Kconfig
@@ -0,0 +1,20 @@
+
+menuconfig VIDEO_EXYNOS
+	bool "Enable Exynos video support"
+	depends on DM_VIDEO
+	help
+	  Enable support for various video output options on Exynos SoCs.
+
+if VIDEO_EXYNOS
+
+config EXYNOS_DP
+	bool "Exynos Display Port support"
+
+config EXYNOS_FB
+	bool "Exynos FIMD support"
+
+config EXYNOS_MIPI_DSIM
+	bool "Exynos MIPI DSI support"
+	depends on EXYNOS_FB
+
+endif
diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c
deleted file mode 100644
index a3d467aa23..0000000000
--- a/drivers/video/exynos/exynos_pwm_bl.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PWM BACKLIGHT driver for Board based on EXYNOS.
- *
- * Author: Donghwa Lee  <dh09.lee@samsung.com>
- *
- * Derived from linux/drivers/video/backlight/pwm_backlight.c
- */
-
-#include <common.h>
-#include <pwm.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/pwm_backlight.h>
-
-static struct pwm_backlight_data *pwm;
-
-static int exynos_pwm_backlight_update_status(void)
-{
-	int brightness = pwm->brightness;
-	int max = pwm->max_brightness;
-
-	if (brightness == 0) {
-		pwm_config(pwm->pwm_id, 0, pwm->period);
-		pwm_disable(pwm->pwm_id);
-	} else {
-		pwm_config(pwm->pwm_id,
-			brightness * pwm->period / max, pwm->period);
-		pwm_enable(pwm->pwm_id);
-	}
-	return 0;
-}
-
-int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
-{
-	pwm = pd;
-
-	exynos_pwm_backlight_update_status();
-
-	return 0;
-}
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
deleted file mode 100644
index 21ade8d93c..0000000000
--- a/drivers/video/pxa_lcd.c
+++ /dev/null
@@ -1,549 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PXA LCD Controller
- *
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- */
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-#include <lcd.h>
-#include <linux/types.h>
-#include <stdarg.h>
-#include <stdio_dev.h>
-
-/* #define DEBUG */
-
-#ifdef CONFIG_LCD
-
-/*----------------------------------------------------------------------*/
-/*
- * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
- * your display.
- */
-
-#ifdef CONFIG_PXA_VGA
-/* LCD outputs connected to a video DAC  */
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF01
-
-/* 640x480x16 @ 61 Hz */
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 640,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 40,
-	.vl_blw		= 56,
-	.vl_elw		= 56,
-	.vl_vpw		= 20,
-	.vl_bfw		= 8,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_PXA_VIDEO */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_SHARP_LM8V31
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x0030087C
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 3,
-	.vl_elw		= 3,
-	.vl_vpw		= 1,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_SHARP_LM8V31 */
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_VOIPAC_LCD
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 32,
-	.vl_blw		= 144,
-	.vl_elw		= 32,
-	.vl_vpw		= 2,
-	.vl_bfw		= 13,
-	.vl_efw		= 30,
-};
-#endif /* CONFIG_VOIPAC_LCD */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_HITACHI_SX14
-/* Hitachi SX14Q004-ZZA color STN LCD */
-#define LCD_BPP		LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-#define REG_LCCR0	0x00301079
-#define REG_LCCR3	0x0340FF20
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 240,
-	.vl_width	= 167,
-	.vl_height	= 109,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 1,
-	.vl_splt	= 0,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 1,
-	.vl_elw		= 1,
-	.vl_vpw		= 7,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_HITACHI_SX14 */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_LMS283GF05
-
-# define LCD_BPP	LCD_COLOR8
-/*# define LCD_INVERT_COLORS*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x03b00009
-
-vidinfo_t panel_info = {
-	.vl_col		= 240,
-	.vl_row		= 320,
-	.vl_rot		= 3,
-	.vl_width	= 240,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 4,
-	.vl_blw		= 4,
-	.vl_elw		= 8,
-	.vl_vpw		= 4,
-	.vl_bfw		= 4,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_LMS283GF05 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LQ038J7DH53
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700004
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 480,
-	.vl_width	= 320,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x20,
-	.vl_elw		= 0x01,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x04,
-	.vl_efw		= 0x01,
-};
-#endif /* CONFIG_LQ038J7DH53 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LITTLETON_LCD
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF04
-
-vidinfo_t panel_info = {
-	.vl_col		= 480,
-	.vl_row		= 640,
-	.vl_width	= 480,
-	.vl_height	= 640,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 9,
-	.vl_blw		= 8,
-	.vl_elw		= 24,
-	.vl_vpw		= 2,
-	.vl_bfw		= 2,
-	.vl_efw		= 4,
-};
-#endif /* CONFIG_LITTLETON_LCD */
-
-/*----------------------------------------------------------------------*/
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
-static void pxafb_setup_gpio (vidinfo_t *vid);
-static void pxafb_enable_controller (vidinfo_t *vid);
-static int pxafb_init (vidinfo_t *vid);
-
-/************************************************************************/
-/* ---------------  PXA chipset specific functions  ------------------- */
-/************************************************************************/
-
-ushort *configuration_get_cmap(void)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	return (ushort *)fbi->palette;
-}
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	pxafb_init_mem(lcdbase, &panel_info);
-	pxafb_init(&panel_info);
-	pxafb_setup_gpio(&panel_info);
-	pxafb_enable_controller(&panel_info);
-}
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	unsigned short *palette = (unsigned short *)fbi->palette;
-	u_int val;
-
-	if (regno < fbi->palette_size) {
-		val = ((red << 8) & 0xf800);
-		val |= ((green << 4) & 0x07e0);
-		val |= (blue & 0x001f);
-
-#ifdef LCD_INVERT_COLORS
-		palette[regno] = ~val;
-#else
-		palette[regno] = val;
-#endif
-	}
-
-	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
-		regno, &palette[regno],
-		red, green, blue,
-		palette[regno]);
-}
-#endif /* LCD_COLOR8 */
-
-/*----------------------------------------------------------------------*/
-__weak void lcd_enable(void)
-{
-}
-
-/************************************************************************/
-/* ** PXA255 specific routines						*/
-/************************************************************************/
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
- * descriptors and palette areas.
- */
-ulong calc_fbsize (void)
-{
-	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
-
-	size = line_length * panel_info.vl_row;
-	size += PAGE_SIZE;
-
-	return size;
-}
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct pxafb_info *fbi = &vid->pxa;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-
-	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-#ifdef	CONFIG_CPU_MONAHANS
-static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
-#else
-static void pxafb_setup_gpio (vidinfo_t *vid)
-{
-	u_long lccr0;
-
-	/*
-	 * setup is based on type of panel supported
-	 */
-
-	lccr0 = vid->pxa.reg_lccr0;
-
-	/* 4 bit interface */
-	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
-	{
-		debug("Setting GPIO for 4 bit data\n");
-		/* bits 58-61 */
-		writel(readl(GPDR1) | (0xf << 26), GPDR1);
-		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR1_U);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 8 bit interface */
-	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
-		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
-	{
-		debug("Setting GPIO for 8 bit data\n");
-		/* bits 58-65 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | (0x3), GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 16 bit interface */
-	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
-	{
-		debug("Setting GPIO for 16 bit data\n");
-		/* bits 58-77 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | 0x00003fff, GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
-	}
-	else
-	{
-		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
-	}
-}
-#endif
-
-static void pxafb_enable_controller (vidinfo_t *vid)
-{
-	debug("Enabling LCD controller\n");
-
-	/* Sequence from 11.7.10 */
-	writel(vid->pxa.reg_lccr3, LCCR3);
-	writel(vid->pxa.reg_lccr2, LCCR2);
-	writel(vid->pxa.reg_lccr1, LCCR1);
-	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
-	writel(vid->pxa.fdadr0, FDADR0);
-	writel(vid->pxa.fdadr1, FDADR1);
-	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
-
-#ifdef	CONFIG_CPU_MONAHANS
-	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
-#else
-	writel(readl(CKEN) | CKEN16_LCD, CKEN);
-#endif
-
-	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
-	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
-	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
-	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
-	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
-	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
-}
-
-static int pxafb_init (vidinfo_t *vid)
-{
-	struct pxafb_info *fbi = &vid->pxa;
-
-	debug("Configuring PXA LCD\n");
-
-	fbi->reg_lccr0 = REG_LCCR0;
-	fbi->reg_lccr3 = REG_LCCR3;
-
-	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
-		vid->vl_col, vid->vl_hpw,
-		vid->vl_blw, vid->vl_elw);
-	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
-		vid->vl_row, vid->vl_vpw,
-		vid->vl_bfw, vid->vl_efw);
-
-	fbi->reg_lccr1 =
-		LCCR1_DisWdth(vid->vl_col) +
-		LCCR1_HorSnchWdth(vid->vl_hpw) +
-		LCCR1_BegLnDel(vid->vl_blw) +
-		LCCR1_EndLnDel(vid->vl_elw);
-
-	fbi->reg_lccr2 =
-		LCCR2_DisHght(vid->vl_row) +
-		LCCR2_VrtSnchWdth(vid->vl_vpw) +
-		LCCR2_BegFrmDel(vid->vl_bfw) +
-		LCCR2_EndFrmDel(vid->vl_efw);
-
-	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
-	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
-			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
-
-
-	/* setup dma descriptors */
-	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
-	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
-
-	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
-
-	fbi->dmadesc_palette->fsadr = fbi->palette;
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
-
-	if( NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
-	}
-	else
-	{
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
-	}
-
-	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
-	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
-	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
-
-	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
-	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
-	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
-
-	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
-	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
-	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
-
-	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
-	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
-	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
-
-	return 0;
-}
-
-/************************************************************************/
-/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
deleted file mode 100644
index 497258f3de..0000000000
--- a/drivers/video/s6e8ax0.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- */
-
-#include <common.h>
-#include <asm/arch/mipi_dsim.h>
-#include <linux/delay.h>
-
-#include "exynos/exynos_mipi_dsi_lowlevel.h"
-#include "exynos/exynos_mipi_dsi_common.h"
-
-static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	int reverse = dsim_dev->dsim_lcd_dev->reverse_panel;
-	static const unsigned char data_to_send[] = {
-		0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
-		0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
-		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
-		0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3,
-		0xff, 0xff, 0xc8
-	};
-
-	static const unsigned char data_to_send_reverse[] = {
-		0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c,
-		0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20,
-		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
-		0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1,
-		0xf6, 0xf6, 0xc1
-	};
-
-	if (reverse) {
-		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send_reverse,
-			ARRAY_SIZE(data_to_send_reverse));
-	} else {
-		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-	}
-}
-
-static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf2, 0x80, 0x03, 0x0d
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	/* 7500K 2.2 Set : 30cd */
-	static const unsigned char data_to_send[] = {
-		0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad,
-		0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1,
-		0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf7, 0x03
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
-			ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf6, 0x00, 0x02, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
-		0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe3, 0x40
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xb1, 0x04, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0x29, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0x11, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf0, 0x5a, 0x5a
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf1, 0x5a, 0x5a
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
-{
-	/*
-	 * in case of setting gamma and panel condition at first,
-	 * it shuold be setting like below.
-	 * set_gamma() -> set_panel_condition()
-	 */
-
-	s6e8ax0_apply_level1_key(dsim_dev);
-	s6e8ax0_apply_mtp_key(dsim_dev);
-
-	s6e8ax0_sleep_out(dsim_dev);
-	mdelay(5);
-	s6e8ax0_panel_cond(dsim_dev);
-	s6e8ax0_display_cond(dsim_dev);
-	s6e8ax0_gamma_cond(dsim_dev);
-	s6e8ax0_gamma_update(dsim_dev);
-
-	s6e8ax0_etc_source_control(dsim_dev);
-	s6e8ax0_elvss_set(dsim_dev);
-	s6e8ax0_etc_pentile_control(dsim_dev);
-	s6e8ax0_etc_mipi_control1(dsim_dev);
-	s6e8ax0_etc_mipi_control2(dsim_dev);
-	s6e8ax0_etc_power_control(dsim_dev);
-	s6e8ax0_etc_mipi_control3(dsim_dev);
-	s6e8ax0_etc_mipi_control4(dsim_dev);
-}
-
-static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev)
-{
-	s6e8ax0_panel_init(dsim_dev);
-
-	return 0;
-}
-
-static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev)
-{
-	s6e8ax0_display_on(dsim_dev);
-}
-
-static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
-	.name = "s6e8ax0",
-	.id = -1,
-
-	.mipi_panel_init = s6e8ax0_panel_set,
-	.mipi_display_on = s6e8ax0_display_enable,
-};
-
-void s6e8ax0_init(void)
-{
-	exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
-}