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authorShengzhou Liu <Shengzhou.Liu@nxp.com>2016-05-25 16:15:00 +0800
committerYork Sun <york.sun@nxp.com>2016-06-03 14:12:49 -0700
commitd36740462a35aaaaa7e01e43c6ff666467070427 (patch)
treed5d62683155dc54bb452dc1f1340f0ebfbac09c9 /drivers/ddr
parentb06f6f2f0347b6010943fa2ca2f26d1786fdba78 (diff)
downloadu-boot-d36740462a35aaaaa7e01e43c6ff666467070427.tar.gz
driver/ddr/fsl: Check condition for erratum A-009803
Add condition of checking the enabled of address parity for erratum A-009803, if parity is not enabled, the workaround of erratum A-009803 should not be applied. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c42
1 files changed, 23 insertions, 19 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 5039f5de0a..d37e2474c9 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -206,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
/* part 1 of 2 */
- if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
- ddr_out32(&ddr->ddr_sdram_rcw_2,
- regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+ ddr_out32(&ddr->ddr_sdram_rcw_2,
+ regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ }
+ ddr_out32(&ddr->err_disable, regs->err_disable |
+ DDR_ERR_DISABLE_APED);
}
-
- ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
#else
ddr_out32(&ddr->err_disable, regs->err_disable);
#endif
@@ -395,22 +397,24 @@ step2:
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
- /* if it's RDIMM */
- if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
- continue;
- set_wait_for_bits_clear(&ddr->sdram_md_cntl,
- MD_CNTL_MD_EN |
- MD_CNTL_CS_SEL(i) |
- 0x070000ed,
- MD_CNTL_MD_EN);
- udelay(1);
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ /* if it's RDIMM */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+ continue;
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
+ }
}
- }
- ddr_out32(&ddr->err_disable,
- regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ }
#endif
}
#endif