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authorTero Kristo <t-kristo@ti.com>2019-09-27 19:14:26 +0300
committerTom Rini <trini@konsulko.com>2019-10-11 13:32:39 -0400
commit260777fc2333183728d24fb0ffaa22a888c09655 (patch)
treefe44a25865608126801c6b9d5ff3e8073c08e4a9 /drivers/clk/Kconfig
parente69ffdb763dec192102f2705cac14f38c56d9b62 (diff)
downloadu-boot-260777fc2333183728d24fb0ffaa22a888c09655.tar.gz
clk: cdce9xx: add support for cdce9xx clock synthesizer
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk/Kconfig')
-rw-r--r--drivers/clk/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 0035f0a9c6..16d4237f89 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -134,6 +134,13 @@ config CLK_STM32MP1
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
+config CLK_CDCE9XX
+ bool "Enable CDCD9XX clock driver"
+ depends on CLK
+ help
+ Enable the clock synthesizer driver for CDCE913/925/937/949
+ series of chips.
+
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"