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author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-04-23 10:17:41 +0000 |
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committer | Stefano Babic <sbabic@denx.de> | 2013-04-28 11:07:41 +0200 |
commit | 0f67e09e9ef354ae2d282091adb3dc531f2aef7d (patch) | |
tree | be4890247e2b63d086b8778fc35bfd4805e9a633 /doc | |
parent | ccca7dfd0273af41e5b4bdec7f8731b177a20fde (diff) | |
download | u-boot-0f67e09e9ef354ae2d282091adb3dc531f2aef7d.tar.gz |
Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/README.fsl_iim | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim new file mode 100644 index 0000000000..e087f5e0e4 --- /dev/null +++ b/doc/README.fsl_iim @@ -0,0 +1,48 @@ +Driver implementing the fuse API for Freescale's IC Identification Module (IIM) + +This IP can be found on the following SoCs: + - MPC512x, + - i.MX25, + - i.MX27, + - i.MX31, + - i.MX35, + - i.MX51, + - i.MX53. + +The section numbers in this file refer to the i.MX25 Reference Manual. + +A fuse word contains 8 fuse bit slots, as explained in 30.4.2.2.1. + +A bank contains 256 fuse word slots, as shown by the memory map in 30.3.1. + +Some fuse bit or word slots may not have the corresponding fuses actually +implemented in the fusebox. + +See the README files of the SoCs using this driver in order to know the +conventions used by U-Boot to store some specific data in the fuses, e.g. MAC +addresses. + +Fuse operations: + + Read + Read operations are implemented as read accesses to the shadow registers, + using "Word y of Bank x" from the register summary in 30.3.2. This is + explained in detail in 30.4.5.1. + + Sense + Sense operations are implemented as explained in 30.4.5.2. + + Program + Program operations are implemented as explained in 30.4.5.3. Following + this operation, the shadow registers are reloaded by the hardware (not + immediately, but this does not make any difference for a user reading + these registers). + + Override + Override operations are implemented as write accesses to the shadow + registers, as explained in 30.4.5.4. + +Configuration: + + CONFIG_FSL_IIM + Define this to enable the fsl_iim driver. |