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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-07-18 00:34:05 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-24 10:07:24 -0400 |
| commit | 9dc054bb442f900c5d40c964110c5ba3247c2983 (patch) | |
| tree | 20b72bef1ce27eca0a74285f088aca1bac44b4c4 /doc/README.x86 | |
| parent | 428c3f55286192d3ec932698b50985dd9f212545 (diff) | |
| download | u-boot-9dc054bb442f900c5d40c964110c5ba3247c2983.tar.gz | |
doc: board: Add Intel Crown Bay board doc
This extracts Intel Crown Bay board specific information from
README.x86, converts plain text documentation to reST format and
adds it to Sphinx TOC tree. No essential content change.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'doc/README.x86')
| -rw-r--r-- | doc/README.x86 | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/doc/README.x86 b/doc/README.x86 index 8e0a3f36ed..8077ff37ee 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -203,43 +203,6 @@ Flash map for samus / broadwell: --- -Intel Crown Bay specific instructions for bare mode: - -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called -Firmware Support Package [5] to perform all the necessary initialization steps -as documented in the BIOS Writer Guide, including initialization of the CPU, -memory controller, chipset and certain bus interfaces. - -Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, -install it on your host and locate the FSP binary blob. Note this platform -also requires a Chipset Micro Code (CMC) state machine binary to be present in -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found -in this FSP package too. - -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd -* ./Microcode/C0_22211.BIN - -Rename the first one to fsp.bin and second one to cmc.bin and put them in the -board directory. - -Note the FSP release version 001 has a bug which could cause random endless -loop during the FspInit call. This bug was published by Intel although Intel -did not describe any details. We need manually apply the patch to the FSP -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP -binary, change the following five bytes values from orginally E8 42 FF FF FF -to B8 00 80 0B 00. - -As for the video ROM, you need manually extract it from the Intel provided -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM -ID 8086:4108, extract and save it as vga.bin in the board directory. - -Now you can build U-Boot and obtain u-boot.rom - -$ make crownbay_defconfig -$ make all - ---- - Intel Cougar Canyon 2 specific instructions for bare mode: This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors |