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| author | Nitin Jain <nitin.jain@xilinx.com> | 2018-04-20 12:30:40 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-05-11 09:23:43 +0200 |
| commit | 0678941ae54b3f1bbd8024c8d74fb282f0c1b590 (patch) | |
| tree | a7d7b3f17b36ceb28352db914600e06e1e499fc9 /board/xilinx | |
| parent | 767afebbcda59f3ccb04f6c94de8cab2fb7905b6 (diff) | |
| download | u-boot-0678941ae54b3f1bbd8024c8d74fb282f0c1b590.tar.gz | |
arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.
The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.
Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xilinx')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 4c6f29995a..911cd52e0c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -405,7 +405,15 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + mem_map_fill(); + + return 0; } int dram_init(void) @@ -416,6 +424,18 @@ int dram_init(void) return 0; } #else +int dram_init_banksize(void) +{ +#if defined(CONFIG_NR_DRAM_BANKS) + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_effective_memsize(); +#endif + + mem_map_fill(); + + return 0; +} + int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |