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authorAlexey Brodkin <alexey.brodkin@synopsys.com>2018-11-27 09:47:00 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2018-12-03 14:26:45 +0300
commitfb9a46a2ab4bbd6cc8e285d08da56bf3e79710a2 (patch)
tree2e8f419988eb60531d23d450551775982fa63ca2 /board/synopsys
parent4e86c7e3cd21fdab46416284665dbb589f110b94 (diff)
downloadu-boot-fb9a46a2ab4bbd6cc8e285d08da56bf3e79710a2.tar.gz
arc: emsdp: Refactor register and bit accesses
Instead of "base + offset" define all registers right away and access them later via direct defines. Generate bit masks with "BIT" macro. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'board/synopsys')
-rw-r--r--board/synopsys/emsdp/emsdp.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c
index 5ab4435374..3d05f7a8a5 100644
--- a/board/synopsys/emsdp/emsdp.c
+++ b/board/synopsys/emsdp/emsdp.c
@@ -78,31 +78,31 @@ int board_mmc_getcd(struct mmc *mmc)
}
#define CREG_BASE 0xF0001000
-#define CREG_BOOT_OFFSET 0
-#define CREG_BOOT_WP_OFFSET 8
+#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
+#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
-#define CGU_BASE 0xF0000000
-#define CGU_IP_SW_RESET 0x0FF0
+/* Bits in CREG_BOOT register */
+#define CREG_BOOT_WP_BIT BIT(8)
void reset_cpu(ulong addr)
{
- writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET));
+ writel(1, CREG_IP_SW_RESET);
while (1)
; /* loop forever till reset */
}
static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+ u32 creg_boot = readl(CREG_BOOT);
if (!strcmp(argv[1], "unlock"))
- creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET);
+ creg_boot &= ~CREG_BOOT_WP_BIT;
else if (!strcmp(argv[1], "lock"))
- creg_boot |= BIT(CREG_BOOT_WP_OFFSET);
+ creg_boot |= CREG_BOOT_WP_BIT;
else
return CMD_RET_USAGE;
- writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+ writel(creg_boot, CREG_BOOT);
return CMD_RET_SUCCESS;
}