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| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2015-02-10 15:26:10 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2015-02-13 13:14:56 +0900 |
| commit | 79bf043e371cfb7bed276e3ce795f066a364f5ff (patch) | |
| tree | 582bac9733d10de124e492d773648f1ef0e7861c /board/renesas | |
| parent | 3eda55a32d3787303934a1575684a8f61c362892 (diff) | |
| download | u-boot-79bf043e371cfb7bed276e3ce795f066a364f5ff.tar.gz | |
ARM: rmobile: silk: Remove initialization of ACTLR.SMP
Initialization of ACTLR.SMP is in lowlevel_init.
This remove duplicate function.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas')
| -rw-r--r-- | board/renesas/silk/silk.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 8818211d32..dfd9a9d3e4 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -38,18 +38,6 @@ void s_init(void) /* QoS */ qos_init(); - -#ifndef CONFIG_DCACHE_OFF - /* - * The caches are disabled when ACTLR.SMP is set to 0 - * regardless of the value of the SCTLR.C (cache enable bit) - * on Cortex-A7 MPCore - */ - asm volatile( - "mrc 15, 0, r0, c1, c0, 1\n" /* read ACTLR */ - "orr r0, r0, #(1 << 6)\n" /* set ACTLR.SMP bit */ - "mcr p15, 0, r0, c1, c0, 1\n"); /* write ACTLR */ -#endif } #define TMU0_MSTP125 (1 << 25) |