ARM: renesas: Add R8A779F0 S4 Spider board code

Add board code for R8A779F0 S4 Spider board.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
        Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
	Sort headers, use clrbits_le32(), use BIT macros where appropriate
	Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]

3 files changed, 96 insertions, 0 deletions

diff --git a/board/renesas/spider/Kconfig b/board/renesas/spider/Kconfig
new file mode 100644
index 0000000000..8df2e85fc9
--- /dev/null
+++ b/board/renesas/spider/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPIDER
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "spider"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "spider"
+
+endif
diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile
new file mode 100644
index 0000000000..545cb58a98
--- /dev/null
+++ b/board/renesas/spider/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/spider/Makefile
+#
+# Copyright (C) 2020 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= spider.o ../rcar-common/common.o
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
new file mode 100644
index 0000000000..caf88dcc32
--- /dev/null
+++ b/board/renesas/spider/spider.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/spider/spider.c
+ *     This file is Spider board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <common.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+	const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+	/* Update memory mapped and register based freqency */
+	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+	writel(freq, CNTFID0);
+
+	/* Enable counter */
+	setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+static void init_gic_v3(void)
+{
+	 /* GIC v3 power on */
+	writel(BIT(1), GICR_LPI_PWRR);
+
+	/* Wait till the WAKER_CA_BIT changes to 0 */
+	clrbits_le32(GICR_LPI_WAKER, BIT(1));
+	while (readl(GICR_LPI_WAKER) & BIT(2))
+		;
+
+	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
+void s_init(void)
+{
+	if (current_el() == 3)
+		init_generic_timer();
+}
+
+int board_early_init_f(void)
+{
+	/* Unlock CPG access */
+	writel(0x5A5AFFFF, CPGWPR);
+	writel(0xA5A50000, CPGWPCR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (current_el() == 3)
+		init_gic_v3();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	writel(RST_SPRES, RST_SRESCR0);
+}