diff options
| author | Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> | 2020-10-31 17:32:49 +0100 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-11-15 15:29:40 +0530 |
| commit | 71c27dbaaeea11b54f36c8f865f0a0cbeddaa19e (patch) | |
| tree | 6b2d674be117fdaa91db4db7ebdbd2a8cd89f7f5 /board/nokia/rx51 | |
| parent | 56847f3a5e0c03d41cb092065d56e59da4e1c20f (diff) | |
| download | u-boot-71c27dbaaeea11b54f36c8f865f0a0cbeddaa19e.tar.gz | |
Nokia RX-51: Make onenand working
set_gpmc_cs0() sets wrong timings and size for Nokia N900 onenand flash.
Fix that by setting the correct timings and size from the board code
Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Tested-by: Pali Rohár <pali@kernel.org>
Diffstat (limited to 'board/nokia/rx51')
| -rw-r--r-- | board/nokia/rx51/rx51.c | 15 | ||||
| -rw-r--r-- | board/nokia/rx51/rx51.h | 7 |
2 files changed, 22 insertions, 0 deletions
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 528c592441..3d62b5d9ad 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -200,8 +200,23 @@ static void reuse_atags(void) */ int board_init(void) { +#if defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1_RX51, + ONENAND_GPMC_CONFIG2_RX51, + ONENAND_GPMC_CONFIG3_RX51, + ONENAND_GPMC_CONFIG4_RX51, + ONENAND_GPMC_CONFIG5_RX51, + ONENAND_GPMC_CONFIG6_RX51, + 0 + }; +#endif /* in SRAM or SDRAM, finish GPMC */ gpmc_init(); +#if defined(CONFIG_CMD_ONENAND) + enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], + CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); +#endif /* Enable the clks & power */ per_clocks_enable(); /* boot param addr */ diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index fa1b42bf21..4eff823a1b 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -367,4 +367,11 @@ struct emu_hal_params_rx51 { MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ +#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202 +#define ONENAND_GPMC_CONFIG2_RX51 0x00111100 +#define ONENAND_GPMC_CONFIG3_RX51 0x00020200 +#define ONENAND_GPMC_CONFIG4_RX51 0x11001102 +#define ONENAND_GPMC_CONFIG5_RX51 0x03101616 +#define ONENAND_GPMC_CONFIG6_RX51 0x90060000 + #endif |