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authorLudovic Desroches <ludovic.desroches@microchip.com>2018-04-23 10:59:50 +0300
committerTom Rini <trini@konsulko.com>2018-05-08 09:07:35 -0400
commit9ab66d0d207451a834a7995a45c018a6395fc160 (patch)
treebd8101998c51e4d7e9d97c541b204aa65b3a640e /board/atmel
parentcbccb33584c952853baf3522a3cf51660046c77d (diff)
downloadu-boot-9ab66d0d207451a834a7995a45c018a6395fc160.tar.gz
board: atmel: sama5d2_ptc_ek: update pin configuration for NAND
The drive strength has to be set to medium for the NAND data lines. With a low drive, we can get some data corruption. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Diffstat (limited to 'board/atmel')
-rw-r--r--board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
index ff6efbf383..5e8e650cd9 100644
--- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
+++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
@@ -48,14 +48,14 @@ static void board_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */
- atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME); /* D0 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME); /* D1 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME); /* D2 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME); /* D3 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME); /* D4 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME); /* D5 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME); /* D6 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME); /* D7 */
atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */