diff options
author | Neil Armstrong <narmstrong@baylibre.com> | 2021-02-25 09:44:38 +0100 |
---|---|---|
committer | Neil Armstrong <narmstrong@baylibre.com> | 2021-04-06 11:10:29 +0200 |
commit | 2fbd37001c77f0b78d43c578d8e350a6afa27e24 (patch) | |
tree | b877d17c45d76172f1394f7f7fee5055dd12c4e4 /arch | |
parent | 775998d4518c2da2cda02e11edd73a6a7397fcc9 (diff) | |
download | u-boot-2fbd37001c77f0b78d43c578d8e350a6afa27e24.tar.gz |
arm: meson: remove static ethernet link setup
The static ethernet link type config code is no more needed because now handled by
the meson8b glue driver, delete it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch-meson/axg.h | 22 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-meson/eth.h | 12 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-meson/g12a.h | 35 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-meson/gx.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-meson/board-axg.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-meson/board-g12a.c | 31 | ||||
-rw-r--r-- | arch/arm/mach-meson/board-gx.c | 35 |
7 files changed, 0 insertions, 189 deletions
diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h index 91c87696e0..12042de935 100644 --- a/arch/arm/include/asm/arch-meson/axg.h +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -31,26 +31,4 @@ #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 #define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF -/* Peripherals registers */ -#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) - -#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) -#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) - -#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) -#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define AXG_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) - -#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index f765cd7c4c..c0070615c2 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -7,18 +7,6 @@ #ifndef __MESON_ETH_H__ #define __MESON_ETH_H__ -#include <phy.h> - -enum { - /* Use Internal RMII PHY */ - MESON_USE_INTERNAL_RMII_PHY = 1, -}; - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags); - /* Generate an unique MAC address based on the HW serial */ int meson_generate_serial_ethaddr(void); diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h index db29cc3a00..ef4f301f7d 100644 --- a/arch/arm/include/asm/arch-meson/g12a.h +++ b/arch/arm/include/asm/arch-meson/g12a.h @@ -32,39 +32,4 @@ #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 #define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF -/* Peripherals registers */ -#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) - -#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) -#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) - -#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) -#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define G12A_ETH_REG_0_CLK_EN BIT(12) - -#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) -#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) -#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) -#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) -#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) -#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) -#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) -#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) -#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) -#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) -#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) -#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) - -/* HIU registers */ -#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) - -#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __G12A_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 743d2e8bb9..26ec5d0bc3 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -41,24 +41,4 @@ #define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) -#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) -#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) -#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) -#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) - -#define GX_ETH_REG_0_PHY_INTF BIT(0) -#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) -#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define GX_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) - -#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __GX_H__ */ diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 3b14bc9989..71ac65c636 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -91,40 +91,6 @@ static struct mm_region axg_mem_map[] = { struct mm_region *mem_map = axg_mem_map; -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | - AXG_ETH_REG_0_TX_PHASE(1) | - AXG_ETH_REG_0_TX_RATIO(4) | - AXG_ETH_REG_0_PHY_CLK_EN | - AXG_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | - AXG_ETH_REG_0_INVERT_RMII_CLK | - AXG_ETH_REG_0_CLK_EN); - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_gx_dwc2_data; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index cc7e01d014..2e59eee8f7 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -97,37 +97,6 @@ static struct mm_region g12a_mem_map[] = { struct mm_region *mem_map = g12a_mem_map; -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII | - G12A_ETH_REG_0_TX_PHASE(1) | - G12A_ETH_REG_0_TX_RATIO(4) | - G12A_ETH_REG_0_PHY_CLK_EN | - G12A_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII | - G12A_ETH_REG_0_INVERT_RMII_CLK | - G12A_ETH_REG_0_CLK_EN); - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_g12a_dwc2_data; diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index cae7af5afb..01fafd81c4 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -109,41 +109,6 @@ static struct mm_region gx_mem_map[] = { struct mm_region *mem_map = gx_mem_map; -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | - GX_ETH_REG_0_TX_PHASE(1) | - GX_ETH_REG_0_TX_RATIO(4) | - GX_ETH_REG_0_PHY_CLK_EN | - GX_ETH_REG_0_CLK_EN); - - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | - GX_ETH_REG_0_CLK_EN); - - if (!IS_ENABLED(CONFIG_MESON_GXBB)) - writel(0x10110181, GX_ETH_REG_2); - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_gx_dwc2_data; |