diff options
| author | Mathew McBride <matt@traverse.com.au> | 2023-04-12 07:38:21 +0000 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2023-05-05 09:46:03 +0800 |
| commit | 2d6fce16c6dff419bfdd0e8c4cf257723bcb4d79 (patch) | |
| tree | 7a2d4a66ba4129a4fd230e38cb0097930e1c76df /arch | |
| parent | 843f60b4e8b6bd31e4a2ece3eb028f5e04cae9c9 (diff) | |
| download | u-boot-2d6fce16c6dff419bfdd0e8c4cf257723bcb4d79.tar.gz | |
arm: dts: fsl-ls1088a: import CPU definition from Linux kernel
This is required for Linux to boot using the same FDT as
U-Boot (such as passing the control FDT to bootefi).
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-ls1088a.dtsi | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 85316ddb66..dc6241e20d 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -13,6 +13,93 @@ #address-cells = <2>; #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* We have 2 clusters having 4 Cortex-A53 cores each */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; |