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authorSean Anderson <sean.anderson@seco.com>2022-09-23 12:05:51 -0400
committerPeng Fan <peng.fan@nxp.com>2022-10-17 15:17:56 +0800
commit0c3eec2aea8fba147c9eee48577f1dcab57c1174 (patch)
tree9ca78b5355eee0e1924ed0e18e2b22ea51a30856 /arch
parente2ff1d0fa777b11ad6b26432cb7613ab433b15d6 (diff)
downloadu-boot-0c3eec2aea8fba147c9eee48577f1dcab57c1174.tar.gz
arm64: ls104x: Enable eDMA snooping
This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c2
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 926f8f21b6..515dbe02fd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -682,7 +682,7 @@ void fsl_lsch2_early_init_f(void)
SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
- SCFG_SNPCNFGCR_SATAWRSNP);
+ SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
#elif defined(CONFIG_ARCH_LS1012A)
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1fb1191a65..2b73647ab4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -383,6 +383,7 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
+#define SCFG_SNPCNFGCR_EDMASNP 0x00020000
#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000