diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2017-05-01 14:31:56 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-05-02 09:21:09 +0200 |
| commit | 9946631a0f2d8e8493ea17e9fe1f0e190aa3372d (patch) | |
| tree | 886fbc45128cae2a2ea7d6bfd1e4c63524d6a5d9 /arch/arm/mach-sunxi | |
| parent | af83a604b33dde3bbc75fe7b467e649970d674e8 (diff) | |
| download | u-boot-9946631a0f2d8e8493ea17e9fe1f0e190aa3372d.tar.gz | |
sunxi: add clock configuration of R40 sata
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).
Add clock configuration of R40 SATA.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun6i.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 631bc6e250..ec5b026ef5 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -51,6 +51,13 @@ void clock_init_safe(void) writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); if (IS_ENABLED(CONFIG_MACH_SUN6I)) writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); + +#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) + setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); +#endif } #endif |