From 9946631a0f2d8e8493ea17e9fe1f0e190aa3372d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 1 May 2017 14:31:56 +0800 Subject: sunxi: add clock configuration of R40 sata R40 has a similar SATA controller with the ones on A10/A20, but with a reset line added (like other peripherals on sun6i+), and two extra VDD pins added (1.2v and 2.5v). Add clock configuration of R40 SATA. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/mach-sunxi/clock_sun6i.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-sunxi') diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 631bc6e250..ec5b026ef5 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -51,6 +51,13 @@ void clock_init_safe(void) writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); if (IS_ENABLED(CONFIG_MACH_SUN6I)) writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); + +#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) + setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); +#endif } #endif -- cgit v1.2.1