diff options
| author | Tom Rini <trini@konsulko.com> | 2022-12-04 10:13:42 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-23 10:15:11 -0500 |
| commit | 9dbe356ef4ad07221ca488e48eb1ef604859ca72 (patch) | |
| tree | 2d77bff86c063c7f93b1a2b78a64d0c58dc72df3 /arch/arm/mach-mvebu/include | |
| parent | f9932d38a326e18113cc2daf8449c332e46c97a6 (diff) | |
| download | u-boot-9dbe356ef4ad07221ca488e48eb1ef604859ca72.tar.gz | |
global: Migrate CONFIG_SAR_REG to CFG
Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-mvebu/include')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1210d26c74..6edd2e2d79 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -134,7 +134,7 @@ #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) +#define CFG_SAR_REG (MVEBU_REGISTER(0xe8200)) #define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define SAR_CPU_FREQ_OFFS 17 @@ -146,11 +146,11 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18600)) #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -169,11 +169,11 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ -#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CFG_SAR_REG (MBUS_DFX_BASE + 0xf8200) #define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define SAR_CPU_FREQ_OFFS 18 @@ -191,7 +191,7 @@ #define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define SAR_CPU_FREQ_OFFS 21 |