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authorYe Li <ye.li@nxp.com>2019-01-07 09:29:21 +0000
committerStefano Babic <sbabic@denx.de>2019-01-28 20:55:46 +0100
commitd8bbf362f3dc87326597217b8bab083516cf534f (patch)
tree7e3d30d31af9b491374bbf9bcab02222d73bd491 /arch/arm/include
parent56ac8104e3aed2afd9f164186beefc49ef4fdcc6 (diff)
downloadu-boot-d8bbf362f3dc87326597217b8bab083516cf534f.tar.gz
imx: Check the PL310 version for applying errata
Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/pl310.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index 3624362bf1..b83978b1cc 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -19,6 +19,11 @@
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK 0x3f
+#define L2X0_CACHE_ID_RTL_R3P2 0x8
+
struct pl310_regs {
u32 pl310_cache_id;
u32 pl310_cache_type;