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authorKishon Vijay Abraham I <kishon@ti.com>2015-02-23 18:39:44 +0530
committerMarek Vasut <marex@denx.de>2015-04-14 05:48:08 +0200
commitd3cfcb3e2cf44ab7493c9ca0b7a6368bdf3df2d0 (patch)
tree8763fdd7809382517a90dd13141ddd07806e5a6f /arch/arm/include/asm
parent5877de916510cc2030eafe3761a835726956c7d3 (diff)
downloadu-boot-d3cfcb3e2cf44ab7493c9ca0b7a6368bdf3df2d0.tar.gz
ARM: DRA7: Enable clocks for USB OTGSS and USB PHY
Enabled clocks for dwc3 controller and USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/omap_common.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 123c84ff95..c8c3e71b55 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -143,7 +143,7 @@ struct prcm_regs {
u32 cm_div_m2_dpll_unipro;
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
- u32 cm_coreaon_usb_phy_core_clkctrl;
+ u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
/* cm2.core */
@@ -230,7 +230,7 @@ struct prcm_regs {
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
- u32 cm_l3init_usb_otg_ss_clkctrl;
+ u32 cm_l3init_usb_otg_ss1_clkctrl;
u32 prm_irqstatus_mpu_2;