diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-02-12 01:33:45 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:11 -0400 |
| commit | d4d986ee27fe6a78e50d4789d5b08b87a5e64892 (patch) | |
| tree | 0bc6adb8e8d303a5512194a6f5cb4a426e678079 /arch/arm/include/asm/omap_common.h | |
| parent | 9100edecf8379c357037c34044757202f85480b2 (diff) | |
| download | u-boot-d4d986ee27fe6a78e50d4789d5b08b87a5e64892.tar.gz | |
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/omap_common.h')
| -rw-r--r-- | arch/arm/include/asm/omap_common.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec938..0af0c3376c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; |