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authorIcenowy Zheng <icenowy@aosc.io>2022-01-29 10:23:03 -0500
committerAndre Przywara <andre.przywara@arm.com>2022-02-04 00:09:57 +0000
commit5d35f0f254cde3d8830a88193e143cd204785643 (patch)
treea58f141a325d65d1d38ab04110f41f28b50f661e /arch/arm/include/asm/arch-sunxi/clock_sun6i.h
parent88998f7775311bb20f41c7ba9341be5162423a1c (diff)
downloadu-boot-5d35f0f254cde3d8830a88193e143cd204785643.tar.gz
ARM: sunxi: Add clock and uart to sunxi headers
This patch aims to add header files for the suniv. The header files included add support for uart, and clocks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun6i.h')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index ee387127f3..7fcf340db6 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -226,7 +226,12 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
+#ifdef CONFIG_MACH_SUNIV
+/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
+#define PLL6_CFG_DEFAULT 0x90041801
+#else
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
+#endif
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@@ -488,6 +493,14 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
+/* apb1 reset */
+#ifdef CONFIG_MACH_SUNIV
+#define APB1_GATE_UART_SHIFT (20)
+#define APB1_GATE_TWI_SHIFT (16)
+#define APB1_RESET_UART_SHIFT (20)
+#define APB1_RESET_TWI_SHIFT (16)
+#endif
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)