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authorTom Rini <trini@konsulko.com>2023-04-04 11:47:25 -0400
committerTom Rini <trini@konsulko.com>2023-05-03 09:05:24 -0400
commit7a3ee61f55518106e61179eb44579087a871cf26 (patch)
tree67234c4c11077d65fa98104ffa986b50d2b96d83 /arch/arm/dts
parent4d03f476a709962dc9789273cedaecf1f9bfae57 (diff)
downloadu-boot-7a3ee61f55518106e61179eb44579087a871cf26.tar.gz
arm: Remove omap5_uevm board
This platform is unsupported by TI and was never widely distributed. As this is untested for a long while and missing some DM conversions, remove it and related device tree files. Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/omap5-board-common.dtsi762
-rw-r--r--arch/arm/dts/omap5-l4-abe.dtsi449
-rw-r--r--arch/arm/dts/omap5-l4.dtsi2437
-rw-r--r--arch/arm/dts/omap5-uevm.dts200
-rw-r--r--arch/arm/dts/omap5.dtsi583
-rw-r--r--arch/arm/dts/omap54xx-clocks.dtsi1208
7 files changed, 0 insertions, 5642 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 29fb1c1d4b..8c10346a96 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1142,9 +1142,6 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
omap4-sdp.dtb \
omap4-sdp-es23plus.dtb
-dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
- omap5-uevm.dtb
-
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
at91-sama7g5ek.dtb
diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi
deleted file mode 100644
index 45435bb88c..0000000000
--- a/arch/arm/dts/omap5-board-common.dtsi
+++ /dev/null
@@ -1,762 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include "omap5.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- aliases {
- display0 = &hdmi0;
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- vmain: fixedregulator-vmain {
- compatible = "regulator-fixed";
- regulator-name = "vmain";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vsys_cobra: fixedregulator-vsys_cobra {
- compatible = "regulator-fixed";
- regulator-name = "vsys_cobra";
- vin-supply = <&vmain>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdds_1v8_main: fixedregulator-vdds_1v8_main {
- compatible = "regulator-fixed";
- regulator-name = "vdds_1v8_main";
- vin-supply = <&smps7_reg>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vmmcsd_fixed: fixedregulator-mmcsd {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- mmc3_pwrseq: sdhci0_pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&clk32kgaudio>;
- clock-names = "ext_clock";
- };
-
- vmmcsdio_fixed: fixedregulator-mmcsdio {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsdio_fixed";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
- enable-active-high;
- startup-delay-us = <70000>;
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_pins>;
- };
-
- /* HS USB Host PHY on PORT 2 */
- hsusb2_phy: hsusb2_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
- clocks = <&auxclk1_ck>;
- clock-names = "main_clk";
- clock-frequency = <19200000>;
- #phy-cells = <0>;
- };
-
- /* HS USB Host PHY on PORT 3 */
- hsusb3_phy: hsusb3_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
- #phy-cells = <0>;
- };
-
- tpd12s015: encoder {
- compatible = "ti,tpd12s015";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
- /* gpios defined in the board specific dts */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tpd12s015_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tpd12s015_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- label = "hdmi";
-
- type = "b";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tpd12s015_out>;
- };
- };
- };
-
- sound: sound {
- compatible = "ti,abe-twl6040";
- ti,model = "omap5-uevm";
-
- ti,jack-detection;
- ti,mclk-freq = <19200000>;
-
- ti,mcpdm = <&mcpdm>;
-
- ti,twl6040 = <&twl6040>;
-
- /* Audio routing */
- ti,audio-routing =
- "Headset Stereophone", "HSOL",
- "Headset Stereophone", "HSOR",
- "Line Out", "AUXL",
- "Line Out", "AUXR",
- "HSMIC", "Headset Mic",
- "Headset Mic", "Headset Mic Bias",
- "AFML", "Line In",
- "AFMR", "Line In";
- };
-};
-
-&gpio8 {
- /* TI trees use GPIO instead of msecure, see also muxing */
- msecure-hog {
- gpio-hog;
- gpios = <10 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "gpio8_234/msecure";
- };
-};
-
-&omap5_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <
- &usbhost_pins
- &led_gpio_pins
- >;
-
- twl6040_pins: pinmux_twl6040_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
- >;
- };
-
- mcpdm_pins: pinmux_mcpdm_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
- OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
- OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
- OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
- OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
- >;
- };
-
- mcbsp1_pins: pinmux_mcbsp1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
- OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
- OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
- OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
- OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
- OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
- OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
- OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
- >;
- };
-
- mcspi2_pins: pinmux_mcspi2_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
- OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
- OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
- OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
- >;
- };
-
- mcspi3_pins: pinmux_mcspi3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
- OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
- OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
- OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
- >;
- };
-
- mmc3_pins: pinmux_mmc3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
- OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
- OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
- OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
- OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
- OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
- >;
- };
-
- wlan_pins: pinmux_wlan_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
- >;
- };
-
- /* TI trees use GPIO mode; msecure mode does not work reliably? */
- palmas_msecure_pins: palmas_msecure_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
- >;
- };
-
- usbhost_pins: pinmux_usbhost_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
- OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
-
- OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
- OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
-
- OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
- OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
- >;
- };
-
- led_gpio_pins: pinmux_led_gpio_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
- OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
- OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
- OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
- OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
- >;
- };
-
- uart5_pins: pinmux_uart5_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
- OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
- OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
- OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
- >;
- };
-
- dss_hdmi_pins: pinmux_dss_hdmi_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
- OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
- OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
- >;
- };
-};
-
-&omap5_pmx_wkup {
- pinctrl-names = "default";
- pinctrl-0 = <
- &usbhost_wkup_pins
- >;
-
- palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
- pinctrl-single,pins = <
- /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
- OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
- >;
- };
-
- usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
- >;
- };
-
- wlcore_irq_pin: pinmux_wlcore_irq_pin {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
- >;
- };
-};
-
-&mmc1 {
- vmmc-supply = <&ldo9_reg>;
- bus-width = <4>;
-};
-
-&mmc2 {
- vmmc-supply = <&vmmcsd_fixed>;
- bus-width = <8>;
- ti,non-removable;
-};
-
-&mmc3 {
- vmmc-supply = <&vmmcsdio_fixed>;
- mmc-pwrseq = <&mmc3_pwrseq>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins>;
- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
- &omap5_pmx_core 0x16a>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1271";
- reg = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&wlcore_irq_pin>;
- interrupt-parent = <&gpio1>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
- ref-clock-frequency = <26000000>;
- };
-};
-
-&mmc4 {
- status = "disabled";
-};
-
-&mmc5 {
- status = "disabled";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-
- clock-frequency = <400000>;
-
- palmas: palmas@48 {
- compatible = "ti,palmas";
- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
- reg = <0x48>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,system-power-controller;
- ti,mux-pad1 = <0xa1>;
- ti,mux-pad2 = <0x1b>;
- pinctrl-names = "default";
- pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
-
- palmas_gpio: gpio {
- compatible = "ti,palmas-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- extcon_usb3: palmas_usb {
- compatible = "ti,palmas-usb-vid";
- ti,enable-vbus-detection;
- ti,enable-id-detection;
- ti,wakeup;
- id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
- };
-
- clk32kgaudio: palmas_clk32k@1 {
- compatible = "ti,palmas-clk32kgaudio";
- #clock-cells = <0>;
- };
-
- rtc {
- compatible = "ti,palmas-rtc";
- interrupt-parent = <&palmas>;
- interrupts = <8 IRQ_TYPE_NONE>;
- ti,backup-battery-chargeable;
- ti,backup-battery-charge-high-current;
- };
-
- gpadc: gpadc {
- compatible = "ti,palmas-gpadc";
- interrupts = <18 0
- 16 0
- 17 0>;
- #io-channel-cells = <1>;
- ti,channel0-current-microamp = <5>;
- ti,channel3-current-microamp = <10>;
- };
-
- palmas_pmic {
- compatible = "ti,palmas-pmic";
- interrupt-parent = <&palmas>;
- interrupts = <14 IRQ_TYPE_NONE>;
- interrupt-names = "short-irq";
-
- ti,ldo6-vibrator;
-
- smps123-in-supply = <&vsys_cobra>;
- smps45-in-supply = <&vsys_cobra>;
- smps6-in-supply = <&vsys_cobra>;
- smps7-in-supply = <&vsys_cobra>;
- smps8-in-supply = <&vsys_cobra>;
- smps9-in-supply = <&vsys_cobra>;
- smps10_out2-in-supply = <&vsys_cobra>;
- smps10_out1-in-supply = <&vsys_cobra>;
- ldo1-in-supply = <&vsys_cobra>;
- ldo2-in-supply = <&vsys_cobra>;
- ldo3-in-supply = <&vdds_1v8_main>;
- ldo4-in-supply = <&vdds_1v8_main>;
- ldo5-in-supply = <&vsys_cobra>;
- ldo6-in-supply = <&vdds_1v8_main>;
- ldo7-in-supply = <&vsys_cobra>;
- ldo8-in-supply = <&vsys_cobra>;
- ldo9-in-supply = <&vmmcsd_fixed>;
- ldoln-in-supply = <&vsys_cobra>;
- ldousb-in-supply = <&vsys_cobra>;
-
- regulators {
- smps123_reg: smps123 {
- /* VDD_OPP_MPU */
- regulator-name = "smps123";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps45_reg: smps45 {
- /* VDD_OPP_MM */
- regulator-name = "smps45";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1310000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps6_reg: smps6 {
- /* VDD_DDR3 - over VDD_SMPS6 */
- regulator-name = "smps6";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps7_reg: smps7 {
- /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
- regulator-name = "smps7";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps8_reg: smps8 {
- /* VDD_OPP_CORE */
- regulator-name = "smps8";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1310000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps9_reg: smps9 {
- /* VDDA_2v1_AUD over VDD_2v1 */
- regulator-name = "smps9";
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2100000>;
- ti,smps-range = <0x80>;
- };
-
- smps10_out2_reg: smps10_out2 {
- /* VBUS_5V_OTG */
- regulator-name = "smps10_out2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps10_out1_reg: smps10_out1 {
- /* VBUS_5V_OTG */
- regulator-name = "smps10_out1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- ldo1_reg: ldo1 {
- /* VDDAPHY_CAM: vdda_csiport */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo2_reg: ldo2 {
- /* VCC_2V8_DISP: Does not go anywhere */
- regulator-name = "ldo2";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- /* Unused */
- status = "disabled";
- };
-
- ldo3_reg: ldo3 {
- /* VDDAPHY_MDM: vdda_lli */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- /* Only if Modem is used */
- status = "disabled";
- };
-
- ldo4_reg: ldo4 {
- /* VDDAPHY_DISP: vdda_dsiport/hdmi */
- regulator-name = "ldo4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PHY: usb/sata/hdmi.. */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo6_reg: ldo6 {
- /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
- regulator-name = "ldo6";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo7_reg: ldo7 {
- /* VDD_VPP: vpp1 */
- regulator-name = "ldo7";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- /* Only for efuse reprograming! */
- status = "disabled";
- };
-
- ldo8_reg: ldo8 {
- /* VDD_3v0: Does not go anywhere */
- regulator-name = "ldo8";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- /* Unused */
- status = "disabled";
- };
-
- ldo9_reg: ldo9 {
- /* VCC_DV_SDIO: vdds_sdcard */
- regulator-name = "ldo9";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- };
-
- ldoln_reg: ldoln {
- /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
- regulator-name = "ldoln";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldousb_reg: ldousb {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldousb";
- regulator-min-microvolt = <3250000>;
- regulator-max-microvolt = <3250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- regen3_reg: regen3 {
- /* REGEN3 controls LDO9 supply to card */
- regulator-name = "regen3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-
- palmas_power_button: palmas_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&palmas>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- };
- };
-
- twl6040: twl@4b {
- compatible = "ti,twl6040";
- #clock-cells = <0>;
- reg = <0x4b>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&twl6040_pins>;
-
- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
-
- /* audpwron gpio defined in the board specific dts */
-
- vio-supply = <&smps7_reg>;
- v2v1-supply = <&smps9_reg>;
- enable-active-high;
-
- clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
- clock-names = "clk32k", "mclk";
- };
-};
-
-&mcpdm_module {
- /* Module on the SoC needs external clock from the PMIC */
- pinctrl-names = "default";
- pinctrl-0 = <&mcpdm_pins>;
- status = "okay";
-};
-
-&mcpdm {
- clocks = <&twl6040>;
- clock-names = "pdmclk";
-};
-
-&mcbsp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp1_pins>;
- status = "okay";
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-};
-
-&usbhshost {
- port2-mode = "ehci-hsic";
- port3-mode = "ehci-hsic";
-};
-
-&usbhsehci {
- phys = <0 &hsusb2_phy &hsusb3_phy>;
-};
-
-&usb3 {
- extcon = <&extcon_usb3>;
- vbus-supply = <&smps10_out1_reg>;
-};
-
-&dwc3 {
- extcon = <&extcon_usb3>;
- dr_mode = "otg";
-};
-
-&mcspi1 {
-
-};
-
-&mcspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi2_pins>;
-};
-
-&mcspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi3_pins>;
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <&omap5_pmx_core 0x19c>;
-};
-
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart5_pins>;
-};
-
-&cpu0 {
- cpu0-supply = <&smps123_reg>;
-};
-
-&dss {
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-
- /* vdda-supply populated in board specific dts file */
-
- pinctrl-names = "default";
- pinctrl-0 = <&dss_hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&tpd12s015_in>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-l4-abe.dtsi b/arch/arm/dts/omap5-l4-abe.dtsi
deleted file mode 100644
index f73eea0b43..0000000000
--- a/arch/arm/dts/omap5-l4-abe.dtsi
+++ /dev/null
@@ -1,449 +0,0 @@
-&l4_abe { /* 0x40100000 */
- compatible = "ti,omap5-l4-abe", "simple-bus";
- reg = <0x40100000 0x400>,
- <0x40100400 0x400>;
- reg-names = "la", "ap";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
- <0x49000000 0x49000000 0x100000>;
- segment@0 { /* 0x40100000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges =
- /* CPU to L4 ABE mapping */
- <0x00000000 0x00000000 0x000400>, /* ap 0 */
- <0x00000400 0x00000400 0x000400>, /* ap 1 */
- <0x00022000 0x00022000 0x001000>, /* ap 2 */
- <0x00023000 0x00023000 0x001000>, /* ap 3 */
- <0x00024000 0x00024000 0x001000>, /* ap 4 */
- <0x00025000 0x00025000 0x001000>, /* ap 5 */
- <0x00026000 0x00026000 0x001000>, /* ap 6 */
- <0x00027000 0x00027000 0x001000>, /* ap 7 */
- <0x00028000 0x00028000 0x001000>, /* ap 8 */
- <0x00029000 0x00029000 0x001000>, /* ap 9 */
- <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
- <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
- <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
- <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
- <0x00030000 0x00030000 0x001000>, /* ap 14 */
- <0x00031000 0x00031000 0x001000>, /* ap 15 */
- <0x00032000 0x00032000 0x001000>, /* ap 16 */
- <0x00033000 0x00033000 0x001000>, /* ap 17 */
- <0x00038000 0x00038000 0x001000>, /* ap 18 */
- <0x00039000 0x00039000 0x001000>, /* ap 19 */
- <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
- <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
- <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
- <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
- <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
- <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
- <0x00080000 0x00080000 0x010000>, /* ap 26 */
- <0x00080000 0x00080000 0x001000>, /* ap 27 */
- <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
- <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
- <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
- <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
- <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
- <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
-
- /* L3 to L4 ABE mapping */
- <0x49000000 0x49000000 0x000400>, /* ap 0 */
- <0x49000400 0x49000400 0x000400>, /* ap 1 */
- <0x49022000 0x49022000 0x001000>, /* ap 2 */
- <0x49023000 0x49023000 0x001000>, /* ap 3 */
- <0x49024000 0x49024000 0x001000>, /* ap 4 */
- <0x49025000 0x49025000 0x001000>, /* ap 5 */
- <0x49026000 0x49026000 0x001000>, /* ap 6 */
- <0x49027000 0x49027000 0x001000>, /* ap 7 */
- <0x49028000 0x49028000 0x001000>, /* ap 8 */
- <0x49029000 0x49029000 0x001000>, /* ap 9 */
- <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
- <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
- <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
- <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
- <0x49030000 0x49030000 0x001000>, /* ap 14 */
- <0x49031000 0x49031000 0x001000>, /* ap 15 */
- <0x49032000 0x49032000 0x001000>, /* ap 16 */
- <0x49033000 0x49033000 0x001000>, /* ap 17 */
- <0x49038000 0x49038000 0x001000>, /* ap 18 */
- <0x49039000 0x49039000 0x001000>, /* ap 19 */
- <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
- <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
- <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
- <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
- <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
- <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
- <0x49080000 0x49080000 0x010000>, /* ap 26 */
- <0x49080000 0x49080000 0x001000>, /* ap 27 */
- <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
- <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
- <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
- <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
- <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
- <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
-
- target-module@22000 { /* 0x40122000, ap 2 02.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2208c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x22000 0x1000>,
- <0x49022000 0x49022000 0x1000>;
-
- mcbsp1: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49022000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@24000 { /* 0x40124000, ap 4 04.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2408c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x24000 0x1000>,
- <0x49024000 0x49024000 0x1000>;
-
- mcbsp2: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49024000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@26000 { /* 0x40126000, ap 6 06.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2608c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x1000>,
- <0x49026000 0x49026000 0x1000>;
-
- mcbsp3: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49026000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@28000 { /* 0x40128000, ap 8 08.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x28000 0x1000>,
- <0x49028000 0x49028000 0x1000>;
- };
-
- target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2a000 0x1000>,
- <0x4902a000 0x4902a000 0x1000>;
- };
-
- target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x2e000 0x4>,
- <0x2e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2e000 0x1000>,
- <0x4902e000 0x4902e000 0x1000>;
-
- dmic: dmic@0 {
- compatible = "ti,omap4-dmic";
- reg = <0x0 0x7f>, /* MPU private access */
- <0x4902e000 0x7f>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 67>;
- dma-names = "up_link";
- status = "disabled";
- };
- };
-
- target-module@30000 { /* 0x40130000, ap 14 0e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x30000 0x1000>,
- <0x49030000 0x49030000 0x1000>;
- };
-
- mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x32000 0x4>,
- <0x32010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x32000 0x1000>,
- <0x49032000 0x49032000 0x1000>;
-
- /* Must be only enabled for boards with pdmclk wired */
- status = "disabled";
-
- mcpdm: mcpdm@0 {
- compatible = "ti,omap4-mcpdm";
- reg = <0x0 0x7f>, /* MPU private access */
- <0x49032000 0x7f>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 65>,
- <&sdma 66>;
- dma-names = "up_link", "dn_link";
- };
- };
-
- target-module@38000 { /* 0x40138000, ap 18 12.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x38000 0x4>,
- <0x38010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x38000 0x1000>,
- <0x49038000 0x49038000 0x1000>;
-
- timer5: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x49038000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3a000 0x4>,
- <0x3a010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3a000 0x1000>,
- <0x4903a000 0x4903a000 0x1000>;
-
- timer6: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903a000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3c000 0x4>,
- <0x3c010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3c000 0x1000>,
- <0x4903c000 0x4903c000 0x1000>;
-
- timer7: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903c000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- };
- };
-
- target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3e000 0x4>,
- <0x3e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3e000 0x1000>,
- <0x4903e000 0x4903e000 0x1000>;
-
- timer8: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903e000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@80000 { /* 0x40180000, ap 26 1a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80000 0x10000>,
- <0x49080000 0x49080000 0x10000>;
- };
-
- target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa0000 0x10000>,
- <0x490a0000 0x490a0000 0x10000>;
- };
-
- target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc0000 0x10000>,
- <0x490c0000 0x490c0000 0x10000>;
- };
-
- target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xf1000 0x4>,
- <0xf1010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xf1000 0x1000>,
- <0x490f1000 0x490f1000 0x1000>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi
deleted file mode 100644
index 4521b6447f..0000000000
--- a/arch/arm/dts/omap5-l4.dtsi
+++ /dev/null
@@ -1,2437 +0,0 @@
-&l4_cfg { /* 0x4a000000 */
- compatible = "ti,omap5-l4-cfg", "simple-bus";
- reg = <0x4a000000 0x800>,
- <0x4a000800 0x800>,
- <0x4a001000 0x1000>;
- reg-names = "ap", "la", "ia0";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
- <0x00080000 0x4a080000 0x080000>, /* segment 1 */
- <0x00100000 0x4a100000 0x080000>, /* segment 2 */
- <0x00180000 0x4a180000 0x080000>, /* segment 3 */
- <0x00200000 0x4a200000 0x080000>, /* segment 4 */
- <0x00280000 0x4a280000 0x080000>, /* segment 5 */
- <0x00300000 0x4a300000 0x080000>; /* segment 6 */
-
- segment@0 { /* 0x4a000000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x001000>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00002000 0x00002000 0x001000>, /* ap 3 */
- <0x00003000 0x00003000 0x001000>, /* ap 4 */
- <0x00004000 0x00004000 0x001000>, /* ap 5 */
- <0x00005000 0x00005000 0x001000>, /* ap 6 */
- <0x00056000 0x00056000 0x001000>, /* ap 7 */
- <0x00057000 0x00057000 0x001000>, /* ap 8 */
- <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
- <0x00058000 0x00058000 0x001000>, /* ap 10 */
- <0x00062000 0x00062000 0x001000>, /* ap 11 */
- <0x00063000 0x00063000 0x001000>, /* ap 12 */
- <0x00008000 0x00008000 0x002000>, /* ap 21 */
- <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
- <0x00066000 0x00066000 0x001000>, /* ap 23 */
- <0x00067000 0x00067000 0x001000>, /* ap 24 */
- <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
- <0x00060000 0x00060000 0x001000>, /* ap 70 */
- <0x00064000 0x00064000 0x001000>, /* ap 71 */
- <0x00065000 0x00065000 0x001000>, /* ap 72 */
- <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
- <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
- <0x00070000 0x00070000 0x004000>, /* ap 79 */
- <0x00074000 0x00074000 0x001000>, /* ap 80 */
- <0x00075000 0x00075000 0x001000>, /* ap 81 */
- <0x00076000 0x00076000 0x001000>, /* ap 82 */
- <0x00020000 0x00020000 0x020000>, /* ap 109 */
- <0x00040000 0x00040000 0x001000>, /* ap 110 */
- <0x00059000 0x00059000 0x001000>; /* ap 111 */
-
- target-module@2000 { /* 0x4a002000, ap 3 44.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x2000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
-
- scm_core: scm@0 {
- compatible = "ti,omap5-scm-core", "simple-bus";
- reg = <0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x800>;
-
- scm_conf: scm_conf@0 {
- compatible = "syscon";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-
- scm_padconf_core: scm@800 {
- compatible = "ti,omap5-scm-padconf-core",
- "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x800 0x800>;
-
- omap5_pmx_core: pinmux@40 {
- compatible = "ti,omap5-padconf",
- "pinctrl-single";
- reg = <0x40 0x01b6>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0x7fff>;
- };
-
- omap5_padconf_global: omap5_padconf_global@5a0 {
- compatible = "syscon",
- "simple-bus";
- reg = <0x5a0 0xec>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x5a0 0xec>;
-
- pbias_regulator: pbias_regulator@60 {
- compatible = "ti,pbias-omap5", "ti,pbias-omap";
- reg = <0x60 0x4>;
- syscon = <&omap5_padconf_global>;
- pbias_mmc_reg: pbias_mmc_omap5 {
- regulator-name = "pbias_mmc_omap5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
- };
-
- target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x4000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- cm_core_aon: cm_core_aon@0 {
- compatible = "ti,omap5-cm-core-aon",
- "simple-bus";
- reg = <0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000>;
-
- cm_core_aon_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_aon_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x8000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x2000>;
-
- cm_core: cm_core@0 {
- compatible = "ti,omap5-cm-core", "simple-bus";
- reg = <0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x2000>;
-
- cm_core_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@20000 { /* 0x4a020000, ap 109 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss";
- reg = <0x20000 0x4>,
- <0x20010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x20000>;
-
- usb3: omap_dwc3@0 {
- compatible = "ti,dwc3";
- reg = <0x0 0x10000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <2>;
- ranges = <0 0 0x20000>;
- dwc3: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- phys = <&usb2_phy>, <&usb3_phy>;
- phy-names = "usb2-phy", "usb3-phy";
- dr_mode = "peripheral";
- };
- };
- };
-
- target-module@56000 { /* 0x4a056000, ap 7 02.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x56000 0x4>,
- <0x5602c 0x4>,
- <0x56028 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
- clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x56000 0x1000>;
-
- sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma", "ti,omap-sdma";
- reg = <0x0 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <127>;
- };
- };
-
- target-module@58000 { /* 0x4a058000, ap 10 06.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00058000 0x00001000>,
- <0x00001000 0x00059000 0x00001000>,
- <0x00002000 0x0005a000 0x00001000>,
- <0x00003000 0x0005b000 0x00001000>;
- };
-
- target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5e000 0x2000>;
- };
-
- target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "usb_tll_hs";
- reg = <0x62000 0x4>,
- <0x62010 0x4>,
- <0x62014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x62000 0x1000>;
-
- usbhstll: usbhstll@0 {
- compatible = "ti,usbhs-tll";
- reg = <0x0 0x1000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_host_hs";
- reg = <0x64000 0x4>,
- <0x64010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x64000 0x1000>;
-
- usbhshost: usbhshost@0 {
- compatible = "ti,usbhs-host";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000>;
- clocks = <&l3init_60m_fclk>,
- <&xclk60mhsp1_ck>,
- <&xclk60mhsp2_ck>;
- clock-names = "refclk_60m_int",
- "refclk_60m_ext_p1",
- "refclk_60m_ext_p2";
-
- usbhsohci: ohci@800 {
- compatible = "ti,ohci-omap3";
- reg = <0x800 0x400>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- remote-wakeup-connected;
- };
-
- usbhsehci: ehci@c00 {
- compatible = "ti,ehci-omap";
- reg = <0xc00 0x400>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-
- target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x66000 0x4>,
- <0x66010 0x4>,
- <0x66014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
- clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
- clock-names = "fck";
- resets = <&prm_dsp 1>;
- reset-names = "rstctrl";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x66000 0x1000>;
-
- mmu_dsp: mmu@0 {
- compatible = "ti,omap4-iommu";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <0>;
- };
- };
-
- target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x70000 0x4000>;
- };
-
- target-module@75000 { /* 0x4a075000, ap 81 32.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x75000 0x1000>;
- };
- };
-
- segment@80000 { /* 0x4a080000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
- <0x0005a000 0x000da000 0x001000>, /* ap 14 */
- <0x0005b000 0x000db000 0x001000>, /* ap 15 */
- <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
- <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
- <0x0005e000 0x000de000 0x001000>, /* ap 18 */
- <0x00060000 0x000e0000 0x001000>, /* ap 19 */
- <0x00061000 0x000e1000 0x001000>, /* ap 20 */
- <0x00074000 0x000f4000 0x001000>, /* ap 25 */
- <0x00075000 0x000f5000 0x001000>, /* ap 26 */
- <0x00076000 0x000f6000 0x001000>, /* ap 27 */
- <0x00077000 0x000f7000 0x001000>, /* ap 28 */
- <0x00036000 0x000b6000 0x001000>, /* ap 65 */
- <0x00037000 0x000b7000 0x001000>, /* ap 66 */
- <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
- <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
- <0x00000000 0x00080000 0x004000>, /* ap 83 */
- <0x00004000 0x00084000 0x001000>, /* ap 84 */
- <0x00005000 0x00085000 0x001000>, /* ap 85 */
- <0x00006000 0x00086000 0x001000>, /* ap 86 */
- <0x00007000 0x00087000 0x001000>, /* ap 87 */
- <0x00008000 0x00088000 0x001000>, /* ap 88 */
- <0x00010000 0x00090000 0x004000>, /* ap 89 */
- <0x00014000 0x00094000 0x001000>, /* ap 90 */
- <0x00015000 0x00095000 0x001000>, /* ap 91 */
- <0x00016000 0x00096000 0x001000>, /* ap 92 */
- <0x00017000 0x00097000 0x001000>, /* ap 93 */
- <0x00018000 0x00098000 0x001000>, /* ap 94 */
- <0x00020000 0x000a0000 0x004000>, /* ap 95 */
- <0x00024000 0x000a4000 0x001000>, /* ap 96 */
- <0x00025000 0x000a5000 0x001000>, /* ap 97 */
- <0x00026000 0x000a6000 0x001000>, /* ap 98 */
- <0x00027000 0x000a7000 0x001000>, /* ap 99 */
- <0x00028000 0x000a8000 0x001000>; /* ap 100 */
-
- target-module@0 { /* 0x4a080000, ap 83 28.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x0 0x4>,
- <0x10 0x4>,
- <0x14 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x00004000>,
- <0x00004000 0x00004000 0x00001000>,
- <0x00005000 0x00005000 0x00001000>,
- <0x00006000 0x00006000 0x00001000>,
- <0x00007000 0x00007000 0x00001000>;
-
- ocp2scp@0 {
- compatible = "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0x20>;
- };
-
- usb2_phy: usb2phy@4000 {
- compatible = "ti,omap-usb2";
- reg = <0x4000 0x7c>;
- syscon-phy-power = <&scm_conf 0x300>;
- clocks = <&usb_phy_cm_clk32k>,
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- usb3_phy: usb3phy@4400 {
- compatible = "ti,omap-usb3";
- reg = <0x4400 0x80>,
- <0x4800 0x64>,
- <0x4c00 0x40>;
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- syscon-phy-power = <&scm_conf 0x370>;
- clocks = <&usb_phy_cm_clk32k>,
- <&sys_clkin>,
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
- clock-names = "wkupclk",
- "sysclk",
- "refclk";
- #phy-cells = <0>;
- };
- };
-
- target-module@10000 { /* 0x4a090000, ap 89 36.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x10000 0x4>,
- <0x10010 0x4>,
- <0x10014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00010000 0x00004000>,
- <0x00004000 0x00014000 0x00001000>,
- <0x00005000 0x00015000 0x00001000>,
- <0x00006000 0x00016000 0x00001000>,
- <0x00007000 0x00017000 0x00001000>;
-
- ocp2scp@0 {
- compatible = "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x20>;
- };
-
- sata_phy: phy@6000 {
- compatible = "ti,phy-pipe3-sata";
- reg = <0x6000 0x80>, /* phy_rx */
- <0x6400 0x64>, /* phy_tx */
- <0x6800 0x40>; /* pll_ctrl */
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin>,
- <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
- clock-names = "sysclk", "refclk";
- #phy-cells = <0>;
- };
- };
-
- target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00020000 0x00004000>,
- <0x00004000 0x00024000 0x00001000>,
- <0x00005000 0x00025000 0x00001000>,
- <0x00006000 0x00026000 0x00001000>,
- <0x00007000 0x00027000 0x00001000>;
- };
-
- target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x36000 0x1000>;
- };
-
- target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4d000 0x1000>;
- };
-
- target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x59000 0x1000>;
- };
-
- target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5b000 0x1000>;
- };
-
- target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5d000 0x1000>;
- };
-
- target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x60000 0x1000>;
- };
-
- target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x74000 0x4>,
- <0x74010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
- clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x74000 0x1000>;
-
- mailbox: mailbox@0 {
- compatible = "ti,omap4-mailbox";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <3>;
- ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox-ipu {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <3 0 0>;
- ti,mbox-rx = <2 0 0>;
- };
- };
- };
-
- target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x76000 0x4>,
- <0x76010 0x4>,
- <0x76014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
- clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x76000 0x1000>;
-
- hwspinlock: spinlock@0 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x0 0x1000>;
- #hwlock-cells = <1>;
- };
- };
- };
-
- segment@100000 { /* 0x4a100000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
- <0x00003000 0x00103000 0x001000>, /* ap 60 */
- <0x00008000 0x00108000 0x001000>, /* ap 61 */
- <0x00009000 0x00109000 0x001000>, /* ap 62 */
- <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
- <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
- <0x00040000 0x00140000 0x010000>, /* ap 101 */
- <0x00050000 0x00150000 0x001000>; /* ap 102 */
-
- target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@8000 { /* 0x4a108000, ap 61 26.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
- };
-
- target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
- };
-
- target-module@40000 { /* 0x4a140000, ap 101 16.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x40000 0x10000>;
- };
- };
-
- segment@180000 { /* 0x4a180000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- segment@200000 { /* 0x4a200000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
- <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
- <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
- <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
- <0x00006000 0x00206000 0x001000>, /* ap 33 */
- <0x00007000 0x00207000 0x001000>, /* ap 34 */
- <0x00004000 0x00204000 0x001000>, /* ap 35 */
- <0x00005000 0x00205000 0x001000>, /* ap 36 */
- <0x00012000 0x00212000 0x001000>, /* ap 37 */
- <0x00013000 0x00213000 0x001000>, /* ap 38 */
- <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
- <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
- <0x00010000 0x00210000 0x001000>, /* ap 41 */
- <0x00011000 0x00211000 0x001000>, /* ap 42 */
- <0x00016000 0x00216000 0x001000>, /* ap 43 */
- <0x00017000 0x00217000 0x001000>, /* ap 44 */
- <0x00014000 0x00214000 0x001000>, /* ap 45 */
- <0x00015000 0x00215000 0x001000>, /* ap 46 */
- <0x00018000 0x00218000 0x001000>, /* ap 47 */
- <0x00019000 0x00219000 0x001000>, /* ap 48 */
- <0x00020000 0x00220000 0x001000>, /* ap 49 */
- <0x00021000 0x00221000 0x001000>, /* ap 50 */
- <0x00026000 0x00226000 0x001000>, /* ap 51 */
- <0x00027000 0x00227000 0x001000>, /* ap 52 */
- <0x00028000 0x00228000 0x001000>, /* ap 53 */
- <0x00029000 0x00229000 0x001000>, /* ap 54 */
- <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
- <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
- <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
- <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
- <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
- <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
- <0x00024000 0x00224000 0x001000>, /* ap 75 */
- <0x00025000 0x00225000 0x001000>, /* ap 76 */
- <0x00002000 0x00202000 0x001000>, /* ap 103 */
- <0x00003000 0x00203000 0x001000>, /* ap 104 */
- <0x00008000 0x00208000 0x001000>, /* ap 105 */
- <0x00009000 0x00209000 0x001000>, /* ap 106 */
- <0x00022000 0x00222000 0x001000>, /* ap 107 */
- <0x00023000 0x00223000 0x001000>; /* ap 108 */
-
- target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@4000 { /* 0x4a204000, ap 35 46.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
- };
-
- target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6000 0x1000>;
- };
-
- target-module@8000 { /* 0x4a208000, ap 105 34.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
- };
-
- target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
- };
-
- target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
- };
-
- target-module@10000 { /* 0x4a210000, ap 41 56.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x10000 0x1000>;
- };
-
- target-module@12000 { /* 0x4a212000, ap 37 52.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x12000 0x1000>;
- };
-
- target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x14000 0x1000>;
- };
-
- target-module@16000 { /* 0x4a216000, ap 43 42.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x16000 0x1000>;
- };
-
- target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000 0x1000>;
- };
-
- target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1a000 0x1000>;
- };
-
- target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1c000 0x1000>;
- };
-
- target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1e000 0x1000>;
- };
-
- target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
- };
-
- target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x22000 0x1000>;
- };
-
- target-module@24000 { /* 0x4a224000, ap 75 48.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x24000 0x1000>;
- };
-
- target-module@26000 { /* 0x4a226000, ap 51 24.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x1000>;
- };
-
- target-module@28000 { /* 0x4a228000, ap 53 38.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x28000 0x1000>;
- };
-
- target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2a000 0x1000>;
- };
- };
-
- segment@280000 { /* 0x4a280000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- segment@300000 { /* 0x4a300000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&l4_per { /* 0x48000000 */
- compatible = "ti,omap5-l4-per", "simple-bus";
- reg = <0x48000000 0x800>,
- <0x48000800 0x800>,
- <0x48001000 0x400>,
- <0x48001400 0x400>,
- <0x48001800 0x400>,
- <0x48001c00 0x400>;
- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
- <0x00200000 0x48200000 0x200000>; /* segment 1 */
-
- segment@0 { /* 0x48000000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x000400>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00020000 0x00020000 0x001000>, /* ap 3 */
- <0x00021000 0x00021000 0x001000>, /* ap 4 */
- <0x00032000 0x00032000 0x001000>, /* ap 5 */
- <0x00033000 0x00033000 0x001000>, /* ap 6 */
- <0x00034000 0x00034000 0x001000>, /* ap 7 */
- <0x00035000 0x00035000 0x001000>, /* ap 8 */
- <0x00036000 0x00036000 0x001000>, /* ap 9 */
- <0x00037000 0x00037000 0x001000>, /* ap 10 */
- <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
- <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
- <0x00055000 0x00055000 0x001000>, /* ap 13 */
- <0x00056000 0x00056000 0x001000>, /* ap 14 */
- <0x00057000 0x00057000 0x001000>, /* ap 15 */
- <0x00058000 0x00058000 0x001000>, /* ap 16 */
- <0x00059000 0x00059000 0x001000>, /* ap 17 */
- <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
- <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
- <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
- <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
- <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
- <0x00060000 0x00060000 0x001000>, /* ap 23 */
- <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
- <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
- <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
- <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
- <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
- <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
- <0x00070000 0x00070000 0x001000>, /* ap 30 */
- <0x00071000 0x00071000 0x001000>, /* ap 31 */
- <0x00072000 0x00072000 0x001000>, /* ap 32 */
- <0x00073000 0x00073000 0x001000>, /* ap 33 */
- <0x00061000 0x00061000 0x001000>, /* ap 34 */
- <0x00053000 0x00053000 0x001000>, /* ap 35 */
- <0x00054000 0x00054000 0x001000>, /* ap 36 */
- <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
- <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
- <0x00078000 0x00078000 0x001000>, /* ap 39 */
- <0x00079000 0x00079000 0x001000>, /* ap 40 */
- <0x00086000 0x00086000 0x001000>, /* ap 41 */
- <0x00087000 0x00087000 0x001000>, /* ap 42 */
- <0x00088000 0x00088000 0x001000>, /* ap 43 */
- <0x00089000 0x00089000 0x001000>, /* ap 44 */
- <0x00051000 0x00051000 0x001000>, /* ap 45 */
- <0x00052000 0x00052000 0x001000>, /* ap 46 */
- <0x00098000 0x00098000 0x001000>, /* ap 47 */
- <0x00099000 0x00099000 0x001000>, /* ap 48 */
- <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
- <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
- <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
- <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
- <0x00068000 0x00068000 0x001000>, /* ap 53 */
- <0x00069000 0x00069000 0x001000>, /* ap 54 */
- <0x00090000 0x00090000 0x002000>, /* ap 55 */
- <0x00092000 0x00092000 0x001000>, /* ap 56 */
- <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
- <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
- <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
- <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
- <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
- <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
- <0x00066000 0x00066000 0x001000>, /* ap 63 */
- <0x00067000 0x00067000 0x001000>, /* ap 64 */
- <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
- <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
- <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
- <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
- <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
- <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
- <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
- <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
- <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
- <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
- <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
- <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
- <0x00001400 0x00001400 0x000400>, /* ap 77 */
- <0x00001800 0x00001800 0x000400>, /* ap 78 */
- <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
- <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
- <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
- <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
- <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
- <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
-
- target-module@20000 { /* 0x48020000, ap 3 04.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x20050 0x4>,
- <0x20054 0x4>,
- <0x20058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
-
- uart3: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@32000 { /* 0x48032000, ap 5 3e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x32000 0x4>,
- <0x32010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x32000 0x1000>;
-
- timer2: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@34000 { /* 0x48034000, ap 7 46.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x34000 0x4>,
- <0x34010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x34000 0x1000>;
-
- timer3: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@36000 { /* 0x48036000, ap 9 4e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x36000 0x4>,
- <0x36010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x36000 0x1000>;
-
- timer4: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3e000 0x4>,
- <0x3e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3e000 0x1000>;
-
- timer9: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- target-module@51000 { /* 0x48051000, ap 45 2e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x51000 0x4>,
- <0x51010 0x4>,
- <0x51114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x51000 0x1000>;
-
- gpio7: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@53000 { /* 0x48053000, ap 35 36.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x53000 0x4>,
- <0x53010 0x4>,
- <0x53114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x53000 0x1000>;
-
- gpio8: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@55000 { /* 0x48055000, ap 13 0e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x55000 0x4>,
- <0x55010 0x4>,
- <0x55114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x55000 0x1000>;
-
- gpio2: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@57000 { /* 0x48057000, ap 15 06.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x57000 0x4>,
- <0x57010 0x4>,
- <0x57114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x57000 0x1000>;
-
- gpio3: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@59000 { /* 0x48059000, ap 17 16.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x59000 0x4>,
- <0x59010 0x4>,
- <0x59114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x59000 0x1000>;
-
- gpio4: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5b000 0x4>,
- <0x5b010 0x4>,
- <0x5b114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5b000 0x1000>;
-
- gpio5: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5d000 0x4>,
- <0x5d010 0x4>,
- <0x5d114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5d000 0x1000>;
-
- gpio6: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@60000 { /* 0x48060000, ap 23 24.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x60000 0x8>,
- <0x60010 0x8>,
- <0x60090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x60000 0x1000>;
-
- i2c3: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@66000 { /* 0x48066000, ap 63 4c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x66050 0x4>,
- <0x66054 0x4>,
- <0x66058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x66000 0x1000>;
-
- uart5: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@68000 { /* 0x48068000, ap 53 54.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x68050 0x4>,
- <0x68054 0x4>,
- <0x68058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x68000 0x1000>;
-
- uart6: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6a050 0x4>,
- <0x6a054 0x4>,
- <0x6a058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6a000 0x1000>;
-
- uart1: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6c050 0x4>,
- <0x6c054 0x4>,
- <0x6c058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6c000 0x1000>;
-
- uart2: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6e050 0x4>,
- <0x6e054 0x4>,
- <0x6e058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6e000 0x1000>;
-
- uart4: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@70000 { /* 0x48070000, ap 30 14.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x70000 0x8>,
- <0x70010 0x8>,
- <0x70090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x70000 0x1000>;
-
- i2c1: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@72000 { /* 0x48072000, ap 32 1c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x72000 0x8>,
- <0x72010 0x8>,
- <0x72090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x72000 0x1000>;
-
- i2c2: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@78000 { /* 0x48078000, ap 39 12.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x78000 0x1000>;
- };
-
- target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x7a000 0x8>,
- <0x7a010 0x8>,
- <0x7a090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x7a000 0x1000>;
-
- i2c4: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x7c000 0x8>,
- <0x7c010 0x8>,
- <0x7c090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x7c000 0x1000>;
-
- i2c5: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@86000 { /* 0x48086000, ap 41 5e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x86000 0x4>,
- <0x86010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x86000 0x1000>;
-
- timer10: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- target-module@88000 { /* 0x48088000, ap 43 66.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x88000 0x4>,
- <0x88010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x88000 0x1000>;
-
- timer11: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x91fe0 0x4>,
- <0x91fe4 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
- clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x90000 0x2000>;
-
- rng: rng@0 {
- compatible = "ti,omap4-rng";
- reg = <0x0 0x2000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@98000 { /* 0x48098000, ap 47 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x98000 0x4>,
- <0x98010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x98000 0x1000>;
-
- mcspi1: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
- };
-
- target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x9a000 0x4>,
- <0x9a010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x9a000 0x1000>;
-
- mcspi2: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
- };
-
- target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x9c000 0x4>,
- <0x9c010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x9c000 0x1000>;
-
- mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- ti,dual-volt;
- ti,needs-special-reset;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
- };
-
- target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa2000 0x1000>;
- };
-
- target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x000a4000 0x00001000>,
- <0x00001000 0x000a5000 0x00001000>;
- };
-
- target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa8000 0x4000>;
- };
-
- target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xad000 0x4>,
- <0xad010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xad000 0x1000>;
-
- mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 77>, <&sdma 78>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb2000 0x1000>;
- };
-
- target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xb4000 0x4>,
- <0xb4010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb4000 0x1000>;
-
- mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xb8000 0x4>,
- <0xb8010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb8000 0x1000>;
-
- mcspi3: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
- dma-names = "tx0", "rx0";
- };
- };
-
- target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xba000 0x4>,
- <0xba010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xba000 0x1000>;
-
- mcspi4: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
- dma-names = "tx0", "rx0";
- };
- };
-
- target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xd1000 0x4>,
- <0xd1010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xd1000 0x1000>;
-
- mmc4: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 57>, <&sdma 58>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xd5000 0x4>,
- <0xd5010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xd5000 0x1000>;
-
- mmc5: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 59>, <&sdma 60>;
- dma-names = "tx", "rx";
- };
- };
- };
-
- segment@200000 { /* 0x48200000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&l4_wkup { /* 0x4ae00000 */
- compatible = "ti,omap5-l4-wkup", "simple-bus";
- reg = <0x4ae00000 0x800>,
- <0x4ae00800 0x800>,
- <0x4ae01000 0x1000>;
- reg-names = "ap", "la", "ia0";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
- <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
- <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
-
- segment@0 { /* 0x4ae00000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x001000>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00006000 0x00006000 0x002000>, /* ap 3 */
- <0x00008000 0x00008000 0x001000>, /* ap 4 */
- <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
- <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
- <0x00004000 0x00004000 0x001000>, /* ap 17 */
- <0x00005000 0x00005000 0x001000>, /* ap 18 */
- <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
- <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
-
- target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
- reg = <0x4000 0x4>,
- <0x4010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0x0 0x40>;
- };
- };
-
- target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x6000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6000 0x2000>;
-
- prm: prm@0 {
- compatible = "ti,omap5-prm", "simple-bus";
- reg = <0x0 0x2000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x2000>;
-
- prm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prm_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xa000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
-
- scrm: scrm@0 {
- compatible = "ti,omap5-scrm";
- reg = <0x0 0x1000>;
-
- scrm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- scrm_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xc000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
-
- omap5_pmx_wkup: pinmux@840 {
- compatible = "ti,omap5-padconf",
- "pinctrl-single";
- reg = <0x840 0x003c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0x7fff>;
- };
-
- omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
- compatible = "ti,omap5-scm-wkup-pad-conf",
- "simple-bus";
- reg = <0xda0 0x60>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x60>;
-
- scm_wkup_pad_conf: scm_conf@0 {
- compatible = "syscon", "simple-bus";
- reg = <0x0 0x60>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x60>;
-
- scm_wkup_pad_conf_clocks: clocks@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
- };
- };
- };
-
- segment@10000 { /* 0x4ae10000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
- <0x00001000 0x00011000 0x001000>, /* ap 6 */
- <0x00004000 0x00014000 0x001000>, /* ap 7 */
- <0x00005000 0x00015000 0x001000>, /* ap 8 */
- <0x00008000 0x00018000 0x001000>, /* ap 9 */
- <0x00009000 0x00019000 0x001000>, /* ap 10 */
- <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
- <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
-
- target-module@0 { /* 0x4ae10000, ap 5 10.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x0 0x4>,
- <0x10 0x4>,
- <0x114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
- <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x1000>;
-
- gpio1: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- ti,gpio-always-on;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x4000 0x4>,
- <0x4010 0x4>,
- <0x4014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- wdt2: wdt@0 {
- compatible = "ti,omap5-wdt", "ti,omap3-wdt";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
- reg = <0x8000 0x4>,
- <0x8010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-alwon;
- };
- };
-
- target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0xc000 0x4>,
- <0xc010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
-
- keypad: keypad@0 {
- compatible = "ti,omap4-keypad";
- reg = <0x0 0x400>;
- };
- };
- };
-
- segment@20000 { /* 0x4ae20000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
- <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
- <0x00000000 0x00020000 0x001000>, /* ap 21 */
- <0x00001000 0x00021000 0x001000>, /* ap 22 */
- <0x00002000 0x00022000 0x001000>, /* ap 23 */
- <0x00003000 0x00023000 0x001000>, /* ap 24 */
- <0x00007000 0x00027000 0x000400>, /* ap 25 */
- <0x00008000 0x00028000 0x000800>, /* ap 26 */
- <0x00009000 0x00029000 0x000100>, /* ap 27 */
- <0x00008800 0x00028800 0x000200>, /* ap 28 */
- <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
-
- target-module@0 { /* 0x4ae20000, ap 21 04.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x1000>;
- };
-
- target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00006000 0x00001000>,
- <0x00001000 0x00007000 0x00000400>,
- <0x00002000 0x00008000 0x00000800>,
- <0x00002800 0x00008800 0x00000200>,
- <0x00002a00 0x00008a00 0x00000100>,
- <0x00003000 0x00009000 0x00000100>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts
deleted file mode 100644
index b289b57d05..0000000000
--- a/arch/arm/dts/omap5-uevm.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap5-board-common.dtsi"
-
-/ {
- model = "TI OMAP5 uEVM board";
- compatible = "ti,omap5-uevm", "ti,omap5";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
- };
-
- aliases {
- ethernet = &ethernet;
- };
-
- leds {
- compatible = "gpio-leds";
- led1 {
- label = "omap5:blue:usr1";
- gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- evm_keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&evm_keys_pins>;
-
- #address-cells = <7>;
- #size-cells = <0>;
-
- btn1 {
- label = "BTN1";
- linux,code = <169>;
- gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
- wakeup-source;
- autorepeat;
- debounce-interval = <50>;
- };
- };
-
- evm_leds {
- compatible = "gpio-leds";
-
- led1 {
- label = "omap5:red:led";
- gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led2 {
- label = "omap5:green:led";
- gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
-
- led3 {
- label = "omap5:blue:led";
- gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- default-state = "off";
- };
-
- led4 {
- label = "omap5:green:led1";
- gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led5 {
- label = "omap5:green:led2";
- gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- default-state = "off";
- };
-
- led6 {
- label = "omap5:green:led3";
- gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led7 {
- label = "omap5:green:led4";
- gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- default-state = "off";
- };
-
- led8 {
- label = "omap5:green:led5";
- gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-};
-
-&hdmi {
- vdda-supply = <&ldo4_reg>;
-};
-
-&i2c1 {
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- };
-};
-
-&i2c5 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
-
- clock-frequency = <400000>;
-
- gpio9: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
-
- cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
-};
-
-&omap5_pmx_core {
- evm_keys_pins: pinmux_evm_keys_gpio_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
- OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
- >;
- };
-};
-
-&tpd12s015 {
- gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
- <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
- <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
-};
-
-&twl6040 {
- ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
-};
-
-&twl6040_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
- >;
-};
-
-&usbhsehci {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub@2 {
- compatible = "usb424,3503";
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ethernet: ethernet@3 {
- compatible = "usb424,9730";
- reg = <3>;
- };
-};
-
-&wlcore {
- compatible = "ti,wl1837";
-};
diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi
deleted file mode 100644
index 76ab2cb08f..0000000000
--- a/arch/arm/dts/omap5.dtsi
+++ /dev/null
@@ -1,583 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Based on "omap4.dtsi"
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/omap.h>
-#include <dt-bindings/clock/omap5.h>
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
-
- compatible = "ti,omap5";
- interrupt-parent = <&wakeupgen>;
- chosen { };
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- i2c3 = &i2c4;
- i2c4 = &i2c5;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- serial5 = &uart6;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x0>;
-
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1500000 1250000
- >;
-
- clocks = <&dpll_mpu_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
-
- /* cooling options */
- #cooling-cells = <2>; /* min followed by max */
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x1>;
-
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1500000 1250000
- >;
-
- clocks = <&dpll_mpu_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
-
- /* cooling options */
- #cooling-cells = <2>; /* min followed by max */
- };
- };
-
- thermal-zones {
- #include "omap4-cpu-thermal.dtsi"
- #include "omap5-gpu-thermal.dtsi"
- #include "omap5-core-thermal.dtsi"
- };
-
- timer {
- compatible = "arm,armv7-timer";
- /* PPI secure/nonsecure IRQ */
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&gic>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gic: interrupt-controller@48211000 {
- compatible = "arm,cortex-a15-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0 0x48211000 0 0x1000>,
- <0 0x48212000 0 0x2000>,
- <0 0x48214000 0 0x2000>,
- <0 0x48216000 0 0x2000>;
- interrupt-parent = <&gic>;
- };
-
- wakeupgen: interrupt-controller@48281000 {
- compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0 0x48281000 0 0x1000>;
- interrupt-parent = <&gic>;
- };
-
- /*
- * The soc node represents the soc top level view. It is used for IPs
- * that are not memory mapped in the MPU view or for the MPU itself.
- */
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap4-mpu";
- ti,hwmods = "mpu";
- sram = <&ocmcram>;
- };
- };
-
- /*
- * XXX: Use a flat representation of the OMAP3 interconnect.
- * The real OMAP interconnect network is quite complex.
- * Since it will not bring real advantage to represent that in DT for
- * the moment, just use a fake OCP bus entry to represent the whole bus
- * hierarchy.
- */
- ocp {
- compatible = "ti,omap5-l3-noc", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xc0000000>;
- dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
- ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
- reg = <0 0x44000000 0 0x2000>,
- <0 0x44800000 0 0x3000>,
- <0 0x45000000 0 0x4000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-
- l4_wkup: interconnect@4ae00000 {
- };
-
- l4_cfg: interconnect@4a000000 {
- };
-
- l4_per: interconnect@48000000 {
- };
-
- l4_abe: interconnect@40100000 {
- };
-
- ocmcram: sram@40300000 {
- compatible = "mmio-sram";
- reg = <0x40300000 0x20000>; /* 128k */
- };
-
- gpmc: gpmc@50000000 {
- compatible = "ti,omap4430-gpmc";
- reg = <0x50000000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 4>;
- dma-names = "rxtx";
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- clocks = <&l3_iclk_div>;
- clock-names = "fck";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- target-module@55082000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x55082000 0x4>,
- <0x55082010 0x4>,
- <0x55082014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
- clock-names = "fck";
- resets = <&prm_core 2>;
- reset-names = "rstctrl";
- ranges = <0x0 0x55082000 0x100>;
- #size-cells = <1>;
- #address-cells = <1>;
-
- mmu_ipu: mmu@0 {
- compatible = "ti,omap4-iommu";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- };
- };
-
- dmm@4e000000 {
- compatible = "ti,omap5-dmm";
- reg = <0x4e000000 0x800>;
- interrupts = <0 113 0x4>;
- ti,hwmods = "dmm";
- };
-
- emif1: emif@4c000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif1";
- ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4c000000 0x400>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
- hw-caps-temp-alert;
- };
-
- emif2: emif@4d000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif2";
- ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4d000000 0x400>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
- hw-caps-temp-alert;
- };
-
- bandgap: bandgap@4a0021e0 {
- reg = <0x4a0021e0 0xc
- 0x4a00232c 0xc
- 0x4a002380 0x2c
- 0x4a0023C0 0x3c>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- compatible = "ti,omap5430-bandgap";
-
- #thermal-sensor-cells = <1>;
- };
-
- /* OCP2SCP3 */
- sata: sata@4a141100 {
- compatible = "snps,dwc-ahci";
- reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&sata_phy>;
- phy-names = "sata-phy";
- clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
- ti,hwmods = "sata";
- ports-implemented = <0x1>;
- };
-
- target-module@56000000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x5600fe00 0x4>,
- <0x5600fe10 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x56000000 0x2000000>;
-
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
- };
-
- target-module@58000000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x58000000 4>,
- <0x58000014 4>;
- reg-names = "rev", "syss";
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
- clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x58000000 0x1000000>;
-
- dss: dss@0 {
- compatible = "ti,omap5-dss";
- reg = <0 0x80>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000000>;
-
- target-module@1000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x1000 0x4>,
- <0x1010 0x4>,
- <0x1014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1000 0x1000>;
-
- dispc@0 {
- compatible = "ti,omap5-dispc";
- reg = <0 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@2000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2000 0x4>,
- <0x2010 0x4>,
- <0x2014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x2000 0x1000>;
-
- rfbi: encoder@0 {
- compatible = "ti,omap5-rfbi";
- reg = <0 0x100>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
- clock-names = "fck", "ick";
- };
- };
-
- target-module@5000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5000 0x4>,
- <0x5010 0x4>,
- <0x5014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x5000 0x1000>;
-
- dsi1: encoder@0 {
- compatible = "ti,omap5-dsi";
- reg = <0 0x200>,
- <0x200 0x40>,
- <0x300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@9000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x9000 0x4>,
- <0x9010 0x4>,
- <0x9014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x9000 0x1000>;
-
- dsi2: encoder@0 {
- compatible = "ti,omap5-dsi";
- reg = <0 0x200>,
- <0x200 0x40>,
- <0x300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@40000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x40000 0x4>,
- <0x40010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck", "dss_clk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40000 0x40000>;
-
- hdmi: encoder@0 {
- compatible = "ti,omap5-hdmi";
- reg = <0 0x200>,
- <0x200 0x80>,
- <0x300 0x80>,
- <0x20000 0x19000>;
- reg-names = "wp", "pll", "phy", "core";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- dmas = <&sdma 76>;
- dma-names = "audio_tx";
- };
- };
- };
- };
-
- abb_mpu: regulator-abb-mpu {
- compatible = "ti,abb-v2";
- regulator-name = "abb_mpu";
- #address-cells = <0>;
- #size-cells = <0>;
- clocks = <&sys_clkin>;
- ti,settling-time = <50>;
- ti,clock-cycles = <16>;
-
- reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
- <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
- reg-names = "base-address", "int-address",
- "efuse-address", "ldo-address";
- ti,tranxdone-status-mask = <0x80>;
- /* LDOVBBMPU_MUX_CTRL */
- ti,ldovbb-override-mask = <0x400>;
- /* LDOVBBMPU_VSET_OUT */
- ti,ldovbb-vset-mask = <0x1F>;
-
- /*
- * NOTE: only FBB mode used but actual vset will
- * determine final biasing
- */
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1060000 0 0x0 0 0x02000000 0x01F00000
- 1250000 0 0x4 0 0x02000000 0x01F00000
- >;
- };
-
- abb_mm: regulator-abb-mm {
- compatible = "ti,abb-v2";
- regulator-name = "abb_mm";
- #address-cells = <0>;
- #size-cells = <0>;
- clocks = <&sys_clkin>;
- ti,settling-time = <50>;
- ti,clock-cycles = <16>;
-
- reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
- <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
- reg-names = "base-address", "int-address",
- "efuse-address", "ldo-address";
- ti,tranxdone-status-mask = <0x80000000>;
- /* LDOVBBMM_MUX_CTRL */
- ti,ldovbb-override-mask = <0x400>;
- /* LDOVBBMM_VSET_OUT */
- ti,ldovbb-vset-mask = <0x1F>;
-
- /*
- * NOTE: only FBB mode used but actual vset will
- * determine final biasing
- */
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1025000 0 0x0 0 0x02000000 0x01F00000
- 1120000 0 0x4 0 0x02000000 0x01F00000
- >;
- };
- };
-};
-
-&cpu_thermal {
- polling-delay = <500>; /* milliseconds */
- coefficients = <65 (-1791)>;
-};
-
-#include "omap5-l4.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&gpu_thermal {
- coefficients = <117 (-2992)>;
-};
-
-&core_thermal {
- coefficients = <0 2000>;
-};
-
-#include "omap5-l4-abe.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&prm {
- prm_dsp: prm@400 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x400 0x100>;
- #reset-cells = <1>;
- };
-
- prm_core: prm@700 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x700 0x100>;
- #reset-cells = <1>;
- };
-
- prm_iva: prm@1200 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x1200 0x100>;
- #reset-cells = <1>;
- };
-
- prm_device: prm@1c00 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x1c00 0x100>;
- #reset-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi
deleted file mode 100644
index 4dd3c93e45..0000000000
--- a/arch/arm/dts/omap54xx-clocks.dtsi
+++ /dev/null
@@ -1,1208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP5 clock data
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- */
-&cm_core_aon_clocks {
- pad_clks_src_ck: pad_clks_src_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- pad_clks_ck: pad_clks_ck@108 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_src_ck>;
- ti,bit-shift = <8>;
- reg = <0x0108>;
- };
-
- secure_32k_clk_src_ck: secure_32k_clk_src_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- slimbus_src_clk: slimbus_src_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- slimbus_clk: slimbus_clk@108 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_src_clk>;
- ti,bit-shift = <10>;
- reg = <0x0108>;
- };
-
- sys_32k_ck: sys_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12000000_ck: virt_12000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13000000_ck: virt_13000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_16800000_ck: virt_16800000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16800000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26000000_ck: virt_26000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- virt_27000000_ck: virt_27000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <27000000>;
- };
-
- virt_38400000_ck: virt_38400000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- };
-
- xclk60mhsp1_ck: xclk60mhsp1_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <60000000>;
- };
-
- xclk60mhsp2_ck: xclk60mhsp2_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <60000000>;
- };
-
- dpll_abe_ck: dpll_abe_ck@1e0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-m4xen-clock";
- clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
- reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
- };
-
- dpll_abe_x2_ck: dpll_abe_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_abe_ck>;
- };
-
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_x2_ck>;
- ti,max-div = <31>;
- reg = <0x01f0>;
- ti,index-starts-at-one;
- };
-
- abe_24m_fclk: abe_24m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- abe_clk: abe_clk@108 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- ti,max-div = <4>;
- reg = <0x0108>;
- ti,index-power-of-two;
- };
-
- abe_iclk: abe_iclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&aess_fclk>;
- ti,bit-shift = <24>;
- reg = <0x0528>;
- ti,dividers = <2>, <1>;
- };
-
- abe_lp_clk_div: abe_lp_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_x2_ck>;
- ti,max-div = <31>;
- reg = <0x01f4>;
- ti,index-starts-at-one;
- };
-
- dpll_core_byp_mux: dpll_core_byp_mux@12c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x012c>;
- };
-
- dpll_core_ck: dpll_core_ck@120 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-core-clock";
- clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
- reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
- };
-
- dpll_core_x2_ck: dpll_core_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_core_ck>;
- };
-
- dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- c2c_fclk: c2c_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h21x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- c2c_iclk: c2c_iclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&c2c_fclk>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0138>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x013c>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0140>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0144>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0154>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0158>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x015c>;
- ti,index-starts-at-one;
- };
-
- dpll_core_m2_ck: dpll_core_m2_ck@130 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_ck>;
- ti,max-div = <31>;
- reg = <0x0130>;
- ti,index-starts-at-one;
- };
-
- dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0134>;
- ti,index-starts-at-one;
- };
-
- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h12x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x01ac>;
- };
-
- dpll_iva_ck: dpll_iva_ck@1a0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
- reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
- assigned-clocks = <&dpll_iva_ck>;
- assigned-clock-rates = <1165000000>;
- };
-
- dpll_iva_x2_ck: dpll_iva_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_iva_ck>;
- };
-
- dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_iva_x2_ck>;
- ti,max-div = <63>;
- reg = <0x01b8>;
- ti,index-starts-at-one;
- assigned-clocks = <&dpll_iva_h11x2_ck>;
- assigned-clock-rates = <465920000>;
- };
-
- dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_iva_x2_ck>;
- ti,max-div = <63>;
- reg = <0x01bc>;
- ti,index-starts-at-one;
- assigned-clocks = <&dpll_iva_h12x2_ck>;
- assigned-clock-rates = <388300000>;
- };
-
- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h12x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_mpu_ck: dpll_mpu_ck@160 {
- #clock-cells = <0>;
- compatible = "ti,omap5-mpu-dpll-clock";
- clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
- reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
- };
-
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_mpu_ck>;
- ti,max-div = <31>;
- reg = <0x0170>;
- ti,index-starts-at-one;
- };
-
- per_dpll_hs_clk_div: per_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- l3_iclk_div: l3_iclk_div@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- ti,max-div = <2>;
- ti,bit-shift = <4>;
- reg = <0x100>;
- clocks = <&dpll_core_h12x2_ck>;
- ti,index-power-of-two;
- };
-
- gpu_l3_iclk: gpu_l3_iclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_iclk_div>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- l4_root_clk_div: l4_root_clk_div@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- ti,max-div = <2>;
- ti,bit-shift = <8>;
- reg = <0x100>;
- clocks = <&l3_iclk_div>;
- ti,index-power-of-two;
- };
-
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
- };
-
- aess_fclk: aess_fclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&abe_clk>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x0528>;
- };
-
- mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0540>;
- };
-
- mcasp_gfclk: mcasp_gfclk@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0540>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-};
-&prm_clocks {
- sys_clkin: sys_clkin@110 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
- reg = <0x0110>;
- ti,index-starts-at-one;
- };
-
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- reg = <0x0108>;
- };
-
- abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- reg = <0x010c>;
- };
-
- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_clkin>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- dss_syc_gfclk_div: dss_syc_gfclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_clkin>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&abe_lp_clk_div>;
- reg = <0x0108>;
- };
-
- l3instr_ts_gclk_div: l3instr_ts_gclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&wkupaon_iclk_mux>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-};
-
-&cm_core_clocks {
-
- dpll_per_byp_mux: dpll_per_byp_mux@14c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x014c>;
- };
-
- dpll_per_ck: dpll_per_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
- reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
- };
-
- dpll_per_x2_ck: dpll_per_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_per_ck>;
- };
-
- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0158>;
- ti,index-starts-at-one;
- };
-
- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x015c>;
- ti,index-starts-at-one;
- };
-
- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0164>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m2_ck: dpll_per_m2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_ck>;
- ti,max-div = <31>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0154>;
- ti,index-starts-at-one;
- };
-
- dpll_unipro1_ck: dpll_unipro1_ck@200 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&sys_clkin>;
- reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
- };
-
- dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_unipro1_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_unipro1_ck>;
- ti,max-div = <127>;
- reg = <0x0210>;
- ti,index-starts-at-one;
- };
-
- dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&sys_clkin>;
- reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
- };
-
- dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_unipro2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_unipro2_ck>;
- ti,max-div = <127>;
- reg = <0x01d0>;
- ti,index-starts-at-one;
- };
-
- dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x018c>;
- };
-
- dpll_usb_ck: dpll_usb_ck@180 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-j-type-clock";
- clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
- reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
- };
-
- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_usb_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_usb_ck>;
- ti,max-div = <127>;
- reg = <0x0190>;
- ti,index-starts-at-one;
- };
-
- func_128m_clk: func_128m_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_h11x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- func_12m_fclk: func_12m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- func_24m_clk: func_24m_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- func_48m_fclk: func_48m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- func_96m_fclk: func_96m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- l3init_60m_fclk: l3init_60m_fclk@104 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_usb_m2_ck>;
- reg = <0x0104>;
- ti,dividers = <1>, <8>;
- };
-
- iss_ctrlclk: iss_ctrlclk@1320 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1320>;
- };
-
- lli_txphy_clk: lli_txphy_clk@f20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_unipro1_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x0f20>;
- };
-
- lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_unipro1_m2_ck>;
- ti,bit-shift = <9>;
- reg = <0x0f20>;
- };
-
- usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x0640>;
- };
-
- fdif_fclk: fdif_fclk@1328 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_h11x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x1328>;
- };
-
- gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1520>;
- };
-
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1520>;
- };
-
- hsi_fclk: hsi_fclk@1638 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x1638>;
- };
-};
-
-&cm_core_clockdomains {
- l3init_clkdm: l3init_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>;
- };
-};
-
-&scrm_clocks {
- auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0310>;
- };
-
- auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0310>;
- };
-
- auxclk0_src_ck: auxclk0_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
- };
-
- auxclk0_ck: auxclk0_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk0_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0310>;
- };
-
- auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0314>;
- };
-
- auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0314>;
- };
-
- auxclk1_src_ck: auxclk1_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
- };
-
- auxclk1_ck: auxclk1_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk1_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0314>;
- };
-
- auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0318>;
- };
-
- auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0318>;
- };
-
- auxclk2_src_ck: auxclk2_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
- };
-
- auxclk2_ck: auxclk2_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk2_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0318>;
- };
-
- auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x031c>;
- };
-
- auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x031c>;
- };
-
- auxclk3_src_ck: auxclk3_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
- };
-
- auxclk3_ck: auxclk3_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk3_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x031c>;
- };
-
- auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0320>;
- };
-
- auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0320>;
- };
-
- auxclk4_src_ck: auxclk4_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
- };
-
- auxclk4_ck: auxclk4_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk4_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0320>;
- };
-
- auxclkreq0_ck: auxclkreq0_ck@210 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0210>;
- };
-
- auxclkreq1_ck: auxclkreq1_ck@214 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0214>;
- };
-
- auxclkreq2_ck: auxclkreq2_ck@218 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0218>;
- };
-
- auxclkreq3_ck: auxclkreq3_ck@21c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x021c>;
- };
-};
-
-&cm_core_aon {
- mpu_cm: mpu_cm@300 {
- compatible = "ti,omap4-cm";
- reg = <0x300 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x300 0x100>;
-
- mpu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- dsp_cm: dsp_cm@400 {
- compatible = "ti,omap4-cm";
- reg = <0x400 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x400 0x100>;
-
- dsp_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- abe_cm: abe_cm@500 {
- compatible = "ti,omap4-cm";
- reg = <0x500 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x500 0x100>;
-
- abe_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x64>;
- #clock-cells = <2>;
- };
- };
-
-};
-
-&cm_core {
- l3main1_cm: l3main1_cm@700 {
- compatible = "ti,omap4-cm";
- reg = <0x700 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x700 0x100>;
-
- l3main1_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- l3main2_cm: l3main2_cm@800 {
- compatible = "ti,omap4-cm";
- reg = <0x800 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x800 0x100>;
-
- l3main2_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- ipu_cm: ipu_cm@900 {
- compatible = "ti,omap4-cm";
- reg = <0x900 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x900 0x100>;
-
- ipu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- dma_cm: dma_cm@a00 {
- compatible = "ti,omap4-cm";
- reg = <0xa00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xa00 0x100>;
-
- dma_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- emif_cm: emif_cm@b00 {
- compatible = "ti,omap4-cm";
- reg = <0xb00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xb00 0x100>;
-
- emif_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x1c>;
- #clock-cells = <2>;
- };
- };
-
- l4cfg_cm: l4cfg_cm@d00 {
- compatible = "ti,omap4-cm";
- reg = <0xd00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xd00 0x100>;
-
- l4cfg_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x14>;
- #clock-cells = <2>;
- };
- };
-
- l3instr_cm: l3instr_cm@e00 {
- compatible = "ti,omap4-cm";
- reg = <0xe00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xe00 0x100>;
-
- l3instr_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0xc>;
- #clock-cells = <2>;
- };
- };
-
- l4per_cm: clock@1000 {
- compatible = "ti,omap4-cm";
- reg = <0x1000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1000 0x200>;
-
- l4per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4per", "ti,clkctrl";
- reg = <0x20 0x15c>;
- #clock-cells = <2>;
- };
-
- l4sec_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
- reg = <0x1a0 0x3c>;
- #clock-cells = <2>;
- };
- };
-
- dss_cm: dss_cm@1400 {
- compatible = "ti,omap4-cm";
- reg = <0x1400 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1400 0x100>;
-
- dss_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- gpu_cm: gpu_cm@1500 {
- compatible = "ti,omap4-cm";
- reg = <0x1500 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1500 0x100>;
-
- gpu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- l3init_cm: l3init_cm@1600 {
- compatible = "ti,omap4-cm";
- reg = <0x1600 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1600 0x100>;
-
- l3init_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0xd4>;
- #clock-cells = <2>;
- };
- };
-};
-
-&prm {
- wkupaon_cm: wkupaon_cm@1900 {
- compatible = "ti,omap4-cm";
- reg = <0x1900 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1900 0x100>;
-
- wkupaon_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x5c>;
- #clock-cells = <2>;
- };
- };
-};
-
-&scm_wkup_pad_conf_clocks {
- fref_xtal_ck: fref_xtal_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin>;
- ti,bit-shift = <28>;
- reg = <0x14>;
- };
-};
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