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| author | Michal Simek <michal.simek@xilinx.com> | 2022-02-23 16:17:41 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2022-03-07 16:33:47 +0100 |
| commit | 8b82a3a7feb06e25b4b731dc5485a1da315d2a93 (patch) | |
| tree | af4ad7cf845f9d69349783157f2d2e5e230beace /arch/arm/dts/zynqmp-sck-kv-g-revB.dts | |
| parent | ff7944829497ce94feb62268d0652487ea873ac2 (diff) | |
| download | u-boot-8b82a3a7feb06e25b4b731dc5485a1da315d2a93.tar.gz | |
arm64: zynqmp: Enable DP driver for SOMs
The main reason is to send pmufw cfg overlay from U-Boot to PMUFW to enable
access to DP. Overlay is sent when cls command is called and for that IP
has to be enabled in carrier cards.
And IP needs to be also enabled in SOM dt because with DTB reselection new
DT is not parsed in pre reloc U-Boot instance. It is called from board_f
via embedded_dtb_select(). That's why bind function is not able to allocate
memory and it ends up with error:
"Video device 'display@fd4a0000' cannot allocate frame buffer memory
-ensure the device is set up before relocation"
To avoid this situation DP is placed also to SOM where bind function is
called and frame buffer memory is allocated and just reused after DTB
reselection. Result is the same. There could be a problem in Linux with
different DP configurations but that's need to be solved there because
console should be on from u-boot already.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/c4f31641f917fddb09d976f56875057c658f264c.1645629459.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm/dts/zynqmp-sck-kv-g-revB.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 6ea950a13f..28a3f3c219 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -92,7 +92,7 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; |