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authorSandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>2019-09-27 13:08:45 +0000
committerEugen Hristev <eugen.hristev@microchip.com>2019-10-08 09:16:11 +0300
commitf99e0ad25a9e085adffb47b7bc794f0a450a36e8 (patch)
tree91bcb6347e3076da30d407b42b5c584b5154a2bc /arch/arm/dts/sam9x60ek-u-boot.dtsi
parent9cf7f46307c701638af37a1b506bbfc0c1b5d7d1 (diff)
downloadu-boot-f99e0ad25a9e085adffb47b7bc794f0a450a36e8.tar.gz
ARM: dts: Add dts files for sam9x60ek
add device tree files for sam9x60ek board with below changes. - Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit) - Add the reg property for the pinctrl node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [prasanthi.chellakumar@microchip.com: fix style/whitespace issues] Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com> [nicolas.ferre@microchip.com: - fix gclk, - fix pio/pinctrl controller definition and allow to have more than only PIOA for this SoC, - removing pinctrl address] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [claudiu.beznea@microchip.com: - use SAM9X60's compatible for pinctrl - add drive strength and slew rate options for SDMMC0 pins.] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> [tudor.ambarus@microchip.com: - u-boot,dm-pre-reloc property in dedicated file, - fix pit len, starts from 0xFFFFFE40 and it is of len 0x10] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'arch/arm/dts/sam9x60ek-u-boot.dtsi')
-rw-r--r--arch/arm/dts/sam9x60ek-u-boot.dtsi104
1 files changed, 104 insertions, 0 deletions
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi
new file mode 100644
index 0000000000..68e220926e
--- /dev/null
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ */
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ ahb {
+ u-boot,dm-pre-reloc;
+
+ apb {
+ u-boot,dm-pre-reloc;
+
+ pinctrl {
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+};
+
+&dbgu {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_dbgu {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_sdhci0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pioA {
+ u-boot,dm-pre-reloc;
+};
+
+&pmc {
+ u-boot,dm-pre-reloc;
+};
+
+&main {
+ u-boot,dm-pre-reloc;
+};
+
+&plla {
+ u-boot,dm-pre-reloc;
+};
+
+&mck {
+ u-boot,dm-pre-reloc;
+};
+
+&periph {
+ u-boot,dm-pre-reloc;
+};
+
+&pioA_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci0_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&dbgu_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&generic {
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci0_gclk {
+ u-boot,dm-pre-reloc;
+};
+
+&slowckc {
+ u-boot,dm-pre-reloc;
+};
+
+&slow_osc {
+ u-boot,dm-pre-reloc;
+};
+
+&slow_rc_osc {
+ u-boot,dm-pre-reloc;
+};
+
+&td_slck {
+ u-boot,dm-pre-reloc;
+};
+
+&md_slck {
+ u-boot,dm-pre-reloc;
+};