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authorZhao Qiang <qiang.zhao@nxp.com>2020-12-11 17:31:39 +0800
committerPriyanka Jain <priyanka.jain@nxp.com>2021-02-08 14:01:15 +0530
commit905c8e649e58a28a08086375ac3b16cbf32c793b (patch)
tree54c1380acb883dc25fe45f9d4699c8eb4746e83a /arch/arm/dts/fsl-lx2162a-qds.dts
parentcbfa8f7c7ae9a31e664b088119588518abe7ac41 (diff)
downloadu-boot-905c8e649e58a28a08086375ac3b16cbf32c793b.tar.gz
armv8: dts: fsl-lx2162a: add dspi node into qds dts
Add dspi node into lx2162aqds device tree Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/dts/fsl-lx2162a-qds.dts')
-rw-r--r--arch/arm/dts/fsl-lx2162a-qds.dts105
1 files changed, 105 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index a2592c990f..341610ccf4 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -13,6 +13,12 @@
/ {
model = "NXP Layerscape LX2162AQDS Board";
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+ aliases {
+ spi1 = &dspi0;
+ spi2 = &dspi1;
+ spi3 = &dspi2;
+ };
};
&usb1 {
@@ -30,3 +36,102 @@
&pcie6 {
status = "disabled";
};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash3: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash4: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash5: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi2 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash6: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash7: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash8: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};