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| author | Alexander Graf <agraf@suse.de> | 2016-08-16 21:08:48 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2016-10-19 09:01:31 +0200 |
| commit | 8069821fc2cb55a458efef1c4c614810302b6ab2 (patch) | |
| tree | 51d5fdddc627a48c6055b8f2ab2a30a654d3a9fd /arch/arm/cpu/armv8/fwcall.c | |
| parent | 3ee655ed83ada67912cbbd14b6685bc0c7102553 (diff) | |
| download | u-boot-8069821fc2cb55a458efef1c4c614810302b6ab2.tar.gz | |
arm: Provide common PSCI based reset handler
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.
On these systems, we do not need to implement system reset manually,
but can instead rely on higher level firmware to deal with it.
The exclude list seems excessive right now, but NXP is working on
providing an in-tree PSCI implementation, so that all NXP systems
can eventually use PSCI as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: fix meson]
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu/armv8/fwcall.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fwcall.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index b3ef7c0f73..c57b15f17f 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -112,3 +112,10 @@ void __noreturn psci_system_off(void) while (1) ; } + +#ifdef CONFIG_PSCI_RESET +void reset_misc(void) +{ + psci_system_reset(); +} +#endif /* CONFIG_PSCI_RESET */ |