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| author | Neil Armstrong <narmstrong@baylibre.com> | 2017-10-18 10:02:11 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-17 07:44:13 -0500 |
| commit | ea990816fe96c86d3acb9aaa38776c10de2fb4b0 (patch) | |
| tree | 76553f81bf3c599a6baa73a0c6abe54f385660dc | |
| parent | 8995a96d1d6760c930e37fc92fb718624f5d8fbf (diff) | |
| download | u-boot-ea990816fe96c86d3acb9aaa38776c10de2fb4b0.tar.gz | |
arm: meson: Add supplementary ethernet registers definitions
On Amlogic Meson GXL/GXM, supplementary ethernet configuration registers
were added to configure the internal RMII PHY interface.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| -rw-r--r-- | arch/arm/include/asm/arch-meson/gxbb.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h index ce41349792..74d5290340 100644 --- a/arch/arm/include/asm/arch-meson/gxbb.h +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -22,11 +22,14 @@ #define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) #define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) +#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56) +#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57) #define GXBB_ETH_REG_0_PHY_INTF BIT(0) #define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) #define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) #define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11) #define GXBB_ETH_REG_0_CLK_EN BIT(12) /* HIU registers */ |