diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2020-08-13 14:56:17 +0530 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-09-15 18:51:53 +0530 |
| commit | c07d06855ec32c4a4bdce4d2854bf3eb4ff49d5c (patch) | |
| tree | 044a5e1544ab685aff577d6fa5d370b28cb6fc89 | |
| parent | e85382fc53cbcd3a348815016b71af7e7542f18e (diff) | |
| download | u-boot-c07d06855ec32c4a4bdce4d2854bf3eb4ff49d5c.tar.gz | |
ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
Enable HyperBus and HyperFlash to support HyperFlash boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 28 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 40 |
2 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 4972a7559f..0a5faa2134 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -131,3 +131,31 @@ dr_mode = "peripheral"; u-boot,dm-spl; }; + +&wkup_gpio_pins_default { + u-boot,dm-spl; +}; + +&wkup_gpio0 { + u-boot,dm-spl; +}; + +&mcu_fss0_hpb0_pins_default { + u-boot,dm-spl; +}; + +&fss { + u-boot,dm-spl; +}; + +&hbmc { + u-boot,dm-spl; + + flash@0,0 { + u-boot,dm-spl; + }; +}; + +&hbmc_mux { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f5e4166926..bd30284755 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -107,6 +107,31 @@ J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; }; &main_pmx0 { @@ -214,4 +239,19 @@ maximum-speed = "high-speed"; }; +&hbmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; + ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; + #include "k3-j7200-common-proc-board-u-boot.dtsi" |