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| author | Shiraz Hashim <shiraz.hashim@st.com> | 2011-06-11 21:32:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-08-04 13:50:01 +0200 |
| commit | a39fcfb24be1520859af038971f1eb1b5e06e927 (patch) | |
| tree | 6c47737d2935c4ff35ddf637c1f234d53b01822a | |
| parent | ceb1d6d75e1a3102ceb7f4407840d9f92b87a926 (diff) | |
| download | u-boot-a39fcfb24be1520859af038971f1eb1b5e06e927.tar.gz | |
spear: fix build errors for spear3xx/spear600 platforms
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
| -rw-r--r-- | board/spear/common/spr_misc.c | 10 | ||||
| -rw-r--r-- | include/configs/spear-common.h | 12 |
2 files changed, 19 insertions, 3 deletions
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 0562222ac8..0812c20b8c 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -46,9 +46,7 @@ int dram_init(void) struct xloader_table_1_2 *table_1_2; struct chip_data *chip = &chip_data; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, - PHYS_SDRAM_1_MAXSIZE); + gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { table_1_1 = &xloader_tb->table.table_1_1; @@ -66,6 +64,12 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = gd->ram_size; +} + int misc_init_r(void) { #if defined(CONFIG_CMD_NET) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 4e5bdea369..55d19b5ce3 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -86,6 +86,8 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* NAND FLASH Configuration */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS #define CONFIG_NAND_SPEAR 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 @@ -209,4 +211,14 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + #endif |