diff options
| author | Stefan Roese <sr@denx.de> | 2013-08-26 12:08:48 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2013-09-07 09:48:06 +0200 |
| commit | 9055f66c2dfb637d0f30372a7e79cca854e45bae (patch) | |
| tree | 6c88973acb2a27d8468dafc753fb880581afa5b4 | |
| parent | 1affd4d4a3fe512050e1ad1636d9360c670da531 (diff) | |
| download | u-boot-9055f66c2dfb637d0f30372a7e79cca854e45bae.tar.gz | |
ppc4xx: Fix GPIO handling in lwmon5 and lcd4_lwmon5 BSP
LCD4 needs a slightly different GPIO configuration than the
original LWMON5 variant. GPIO49 needs to be configured to a
default output value of 0 (permanent voltage supply).
Additionally lcd4 also needs to enable the LSB transmitter.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/lwmon5/lwmon5.c | 3 | ||||
| -rw-r--r-- | include/configs/lwmon5.h | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 4e4a5944de..e9aa0b77de 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -527,6 +527,9 @@ void spl_board_init(void) */ board_early_init_f(); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* * Clear resets */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 8f5eb956ae..96f3ba5a13 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -565,6 +565,7 @@ #define CONFIG_SYS_GPIO_PHY1_RST 12 #define CONFIG_SYS_GPIO_FLASH_WP 14 #define CONFIG_SYS_GPIO_PHY0_RST 22 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 #define CONFIG_SYS_GPIO_DSPIC_READY 51 #define CONFIG_SYS_GPIO_CAN_ENABLE 53 #define CONFIG_SYS_GPIO_LSB_ENABLE 54 @@ -577,6 +578,13 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 +/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ +#ifdef CONFIG_LCD4_LWMON5 +#define GPIO49_VAL 0 +#else +#define GPIO49_VAL 1 +#endif + /* * PPC440 GPIO Configuration */ @@ -635,7 +643,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ |