powerpc: remove rsdproto board support

Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/rsdproto/*
 - Remove include/configs/rsdproto.h
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

8 files changed, 1 insertions, 1310 deletions

diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile
deleted file mode 100644
index 9351e94e74..0000000000
--- a/board/rsdproto/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= rsdproto.o flash.o
-obj-y	+= flash_asm.o
diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
deleted file mode 100644
index 37326d587a..0000000000
--- a/board/rsdproto/flash.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * (C) Copyright 2000
- * Marius Groeger <mgroeger@sysgo.de>
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for AM290[48]0B devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* flash hardware ids */
-#define VENDOR_AMD     0x0001
-#define AMD_29DL323C_B 0x2253
-
-/* Define this to include autoselect sequence in flash_init(). Does NOT
- * work when executing from flash itself, so this should be turned
- * on only when debugging the RAM version.
- */
-#undef WITH_AUTOSELECT
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-#if 1
-#define D(x)
-#else
-#define D(x) printf x
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static unsigned char write_ull(flash_info_t *info,
-			       unsigned long address,
-			       volatile unsigned long long data);
-
-/* from flash_asm.S */
-extern void ull_write(unsigned long long volatile *address,
-		      unsigned long long volatile *data);
-extern void ull_read(unsigned long long volatile *address,
-		     unsigned long long volatile *data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-    int i;
-    ulong addr;
-
-#ifdef WITH_AUTOSELECT
-	{
-		unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH;
-		unsigned long long f_command, vendor, device;
-		/* Perform Autoselect */
-		f_command	= 0x00AA00AA00AA00AAULL;
-		ull_write(&f_addr[0x555], &f_command);
-		f_command	= 0x0055005500550055ULL;
-		ull_write(&f_addr[0x2AA], &f_command);
-		f_command	= 0x0090009000900090ULL;
-		ull_write(&f_addr[0x555], &f_command);
-		ull_read(&f_addr[0], &vendor);
-		vendor &= 0xffff;
-		ull_read(&f_addr[1], &device);
-		device &= 0xffff;
-		f_command	= 0x00F000F000F000F0ULL;
-		ull_write(&f_addr[0x555], &f_command);
-		if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
-		  return 0;
-	}
-#endif
-
-    /* Init: no FLASHes known */
-    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-    }
-
-	/* 1st bank: 8 x 32 KB sectors */
-	flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
-	flash_info[0].sector_count = 8;
-	flash_info[0].size = flash_info[0].sector_count * 32 * 1024;
-	addr = PHYS_FLASH;
-    for(i = 0; i < flash_info[0].sector_count; i++) {
-		flash_info[0].start[i] = addr;
-		addr += flash_info[0].size / flash_info[0].sector_count;
-	}
-	/* 1st bank: 63 x 256 KB sectors */
-	flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
-	flash_info[1].sector_count = 63;
-	flash_info[1].size = flash_info[1].sector_count * 256 * 1024;
-    for(i = 0; i < flash_info[1].sector_count; i++) {
-		flash_info[1].start[i] = addr;
-		addr += flash_info[1].size / flash_info[1].sector_count;
-	}
-
-	/*
-	 * protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[1]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-		      &flash_info[0]);
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-		      &flash_info[1]);
-#endif
-
-    return flash_info[0].size + flash_info[1].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-    int i;
-
-    if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-    }
-
-    switch (info->flash_id >> 16) {
-    case VENDOR_AMD:
-		printf ("AMD ");
-		break;
-    default:
-		printf ("Unknown Vendor ");
-		break;
-    }
-
-    switch (info->flash_id & FLASH_TYPEMASK) {
-    case AMD_29DL323C_B:
-		printf ("AM29DL323CB (32 Mbit)\n");
-		break;
-    default:
-		printf ("Unknown Chip Type\n");
-		break;
-    }
-
-    printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-    printf ("  Sector Start Addresses:");
-    for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-		  printf ("\n   ");
-		printf (" %08lX%s",
-				info->start[i],
-				info->protect[i] ? " (RO)" : "     "
-				);
-    }
-    printf ("\n");
-    return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-    int flag, prot, sect, l_sect;
-    ulong start;
-	unsigned long long volatile *f_addr;
-	unsigned long long volatile f_command;
-
-    if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-    }
-
-    prot = 0;
-    for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-    }
-    if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-    } else {
-		printf ("\n");
-    }
-
-	f_addr	= (unsigned long long *)info->start[0];
-	f_command	= 0x00AA00AA00AA00AAULL;
-	ull_write(&f_addr[0x555], &f_command);
-	f_command	= 0x0055005500550055ULL;
-	ull_write(&f_addr[0x2AA], &f_command);
-	f_command	= 0x0080008000800080ULL;
-	ull_write(&f_addr[0x555], &f_command);
-	f_command	= 0x00AA00AA00AA00AAULL;
-	ull_write(&f_addr[0x555], &f_command);
-	f_command	= 0x0055005500550055ULL;
-	ull_write(&f_addr[0x2AA], &f_command);
-
-    /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
-
-    /* Start erase on unprotected sectors */
-    for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-
-			f_addr	=
-			  (unsigned long long *)(info->start[sect]);
-			f_command	= 0x0030003000300030ULL;
-			ull_write(f_addr, &f_command);
-			l_sect = sect;
-		}
-    }
-
-    /* re-enable interrupts if necessary */
-    if (flag)
-      enable_interrupts();
-
-	start = get_timer (0);
-	do
-	{
-		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
-		{	/* write reset command, command address is unimportant */
-			/* this command turns the flash back to read mode     */
-			f_addr =
-			  (unsigned long long *)(info->start[l_sect]);
-			f_command	= 0x00F000F000F000F0ULL;
-			ull_write(f_addr, &f_command);
-			printf (" timeout\n");
-			return 1;
-	}
-	} while(*f_addr != 0xFFFFFFFFFFFFFFFFULL);
-
-    printf (" done\n");
-    return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-    unsigned long cp, wp;
-	unsigned long long data;
-    int i, l, rc;
-
-    wp = (addr & ~7);	/* get lower long long aligned address */
-
-    /*
-     * handle unaligned start bytes
-     */
-    if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<8 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<8; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_ull(info, wp, data)) != 0) {
-			return rc;
-		}
-		wp += 4;
-    }
-
-    /*
-     * handle long long aligned part
-     */
-    while (cnt >= 8) {
-		data = 0;
-		for (i=0; i<8; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_ull(info, wp, data)) != 0) {
-			return rc;
-		}
-		wp  += 8;
-		cnt -= 8;
-    }
-
-    if (cnt == 0) {
-		return ERR_OK;
-    }
-
-    /*
-     * handle unaligned tail bytes
-     */
-    data = 0;
-    for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-    }
-    for (; i<8; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-    }
-
-    return write_ull(info, wp, data);
-}
-
-/*---------------------------------------------------------------------------
-*
-* FUNCTION NAME:  write_ull
-*
-* DESCRIPTION:   writes 8 bytes to flash
-*
-* EXTERNAL EFFECT: nothing
-*
-* PARAMETERS:   32 bit long pointer to address, 64 bit long pointer to data
-*
-* RETURNS:	0 if OK, 1 if timeout, 4 if parameter error
-*--------------------------------------------------------------------------*/
-
-static unsigned char write_ull(flash_info_t *info,
-							   unsigned long address,
-							   volatile unsigned long long data)
-{
-	static unsigned long long f_command;
-	static unsigned long long *f_addr;
-	ulong start;
-
-	/* address muss be 8-aligned! */
-	if (address & 0x7)
-	  return ERR_ALIGN;
-
-	f_addr	= (unsigned long long *)info->start[0];
-	f_command	= 0x00AA00AA00AA00AAULL;
-	ull_write(&f_addr[0x555], &f_command);
-	f_command	= 0x0055005500550055ULL;
-	ull_write(&f_addr[0x2AA], &f_command);
-	f_command	= 0x00A000A000A000A0ULL;
-	ull_write(&f_addr[0x555], &f_command);
-
-	f_addr	= (unsigned long long *)address;
-	f_command	= data;
-	ull_write(f_addr, &f_command);
-
-	start = get_timer (0);
-	do
-	{
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-		{
-			/* write reset command, command address is unimportant */
-			/* this command turns the flash back to read mode     */
-			f_addr	= (unsigned long long *)info->start[0];
-			f_command	= 0x00F000F000F000F0ULL;
-			ull_write(f_addr, &f_command);
-			return ERR_TIMOUT;
-		}
-	} while(*((unsigned long long *)address) != data);
-
-	return 0;
-}
diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S
deleted file mode 100644
index 557cac0279..0000000000
--- a/board/rsdproto/flash_asm.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * -*- mode:c -*-
- *
- * (C) Copyright 2000
- * Marius Groeger <mgroeger@sysgo.de>
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * void ull_write(unsigned long long volatile *address,
- *                unsigned long long volatile *data)
- * r3 = address
- * r4 = data
- *
- * void ull_read(unsigned long long volatile *address,
- *                unsigned long long volatile *data)
- * r3 = address
- * r4 = data
- *
- * Uses the floating point unit to read and write 64 bit wide
- * data (unsigned long long) on the 60x bus. This is necessary
- * because all 4 flash chips use the /WE line from byte lane 0
- *
- * IMPORTANT: data should always be 8-aligned, otherwise an exception will
- * occur.
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-	.globl	ull_write
-ull_write:
-	lfd		0,0(r4)
-	stfd	0,0(r3)
-	blr
-
-	.globl	ull_read
-ull_read:
-	lfd		0, 0(r3)
-	stfd	0, 0(r4)
-	blr
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
deleted file mode 100644
index 1e85c2710d..0000000000
--- a/board/rsdproto/rsdproto.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <i2c.h>
-#include <bcd.h>
-
-/* define to initialise the SDRAM on the local bus */
-#undef INIT_LOCAL_BUS_SDRAM
-
-/* I2C Bus adresses for PPC & Protocol board */
-#define PPC8260_I2C_ADR		0x30	/*(0)011.0000 */
-#define LM84_PPC_I2C_ADR	0x2A	/*(0)010.1010 */
-#define LM84_SHARC_I2C_ADR	0x29	/*(0)010.1001 */
-#define VIRTEX_I2C_ADR		0x25	/*(0)010.0101 */
-#define X24645_PPC_I2C_ADR	0x00	/*(0)00X.XXXX  -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
-#define RS5C372_PPC_I2C_ADR	0x32	/*(0)011.0010  -> this adress is programmed by the manufacturer and cannot be changed !!! */
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
-    },
-
-
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   },
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDC: GP */
-	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDIO: GP */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
-    },
-
-
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-struct tm {
-	unsigned int tm_sec;
-	unsigned int tm_min;
-	unsigned int tm_hour;
-	unsigned int tm_wday;
-	unsigned int tm_mday;
-	unsigned int tm_mon;
-	unsigned int tm_year;
-};
-
-void read_RS5C372_time (struct tm *timedate)
-{
-	unsigned char buffer[8];
-
-	if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
-		timedate->tm_sec = bcd2bin (buffer[0]);
-		timedate->tm_min = bcd2bin (buffer[1]);
-		timedate->tm_hour = bcd2bin (buffer[2]);
-		timedate->tm_wday = bcd2bin (buffer[3]);
-		timedate->tm_mday = bcd2bin (buffer[4]);
-		timedate->tm_mon = bcd2bin (buffer[5]);
-		timedate->tm_year = bcd2bin (buffer[6]) + 2000;
-	} else {
-		/*printf("i2c error %02x\n", rc); */
-		memset (timedate, 0, sizeof (struct tm));
-	}
-}
-
-/* ------------------------------------------------------------------------- */
-
-int read_LM84_temp (int address)
-{
-	unsigned char buffer[8];
-	/*int rc;*/
-
-	if (! i2c_read (address, 0, 1, buffer, 1)) {
-		return (int) buffer[0];
-	} else {
-		/*printf("i2c error %02x\n", rc); */
-		return -42;
-	}
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	struct tm timedate;
-	unsigned int ppctemp, prottemp;
-
-	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
-
-	/* initialise i2c */
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	read_RS5C372_time (&timedate);
-	printf ("  Time:  %02d:%02d:%02d\n",
-			timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
-	printf ("  Date:  %02d-%02d-%04d\n",
-			timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
-	ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
-	prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
-	printf ("  Temp:  PPC %d C, Protocol Board %d C\n",
-			ppctemp, prottemp);
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations while still
- * running in flash
- */
-
-int misc_init_f (void)
-{
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifdef INIT_LOCAL_BUS_SDRAM
-	volatile uchar *ramaddr8;
-#endif
-	volatile ulong *ramaddr32;
-	ulong sdmr;
-	int i;
-
-	/*
-	 * Only initialize SDRAM when running from FLASH.
-	 * When running from RAM, don't touch it.
-	 */
-	if ((ulong) initdram & 0xff000000) {
-		immap->im_siu_conf.sc_ppc_acr = 0x02;
-		immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
-		immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
-		immap->im_siu_conf.sc_lcl_acr = 0x02;
-		immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
-		immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
-		/*
-		 * Program local/60x bus Transfer Error Status and Control Regs:
-		 * Disable parity errors
-		 */
-		immap->im_siu_conf.sc_tescr1 = 0x00040000;
-		immap->im_siu_conf.sc_ltescr1 = 0x00040000;
-
-		/*
-		 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
-		 *
-		 * The appropriate BRx/ORx registers have already
-		 * been set when we get here (see cpu_init_f). The
-		 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-		 */
-		memctl->memc_mptpr = 0x2000;
-		memctl->memc_mar = 0x0200;
-#ifdef INIT_LOCAL_BUS_SDRAM
-		/* initialise local bus ram
-		 *
-		 * (using the PSRMR_ definitions is NOT an error here
-		 * - the LSDMR has the same fields as the PSDMR!)
-		 */
-		memctl->memc_lsrt = 0x0b;
-		memctl->memc_lurt = 0x00;
-		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
-		sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
-		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
-		*ramaddr = 0xff;
-		for (i = 0; i < 8; i++) {
-			memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
-			*ramaddr = 0xff;
-		}
-		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
-		*ramaddr = 0xff;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
-#endif
-		/* initialise 60x bus ram */
-		memctl->memc_psrt = 0x0b;
-		memctl->memc_purt = 0x08;
-		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
-		sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
-		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
-		ramaddr32[0] = 0x00ff00ff;
-		ramaddr32[1] = 0x00ff00ff;
-		memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
-		for (i = 0; i < 8; i++) {
-			ramaddr32[0] = 0x00ff00ff;
-			ramaddr32[1] = 0x00ff00ff;
-		}
-		memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
-		ramaddr32[0] = 0x00ff00ff;
-		ramaddr32[1] = 0x00ff00ff;
-		memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	}
-
-	/* return the size of the 60x bus ram */
-	return PHYS_SDRAM_60X_SIZE;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations after monitor
- * has been relocated into ram
- */
-
-int misc_init_r (void)
-{
-	printf ("misc_init_r\n");
-	return (0);
-}
diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds
deleted file mode 100644
index 44bcd19fb1..0000000000
--- a/board/rsdproto/u-boot.lds
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8260/start.o	(.text)
-    *(.text)
-    *(.got1)
-    /*. = env_offset; */
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.eh_frame)
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/boards.cfg b/boards.cfg
index d90091708b..d0df823a14 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1244,4 +1244,3 @@ Orphan  arm         arm1136        mx31        freescale       -
 Orphan  arm         pxa            -           -               -                   lubbock                              -                                                                                                                                 (dead address) Kyle Harris <kharris@nexus-tech.net>
 Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260                             -                                                                                                                                 -
 Orphan  powerpc     mpc824x        -           -               mousse              MOUSSE                               -                                                                                                                                 -
-Orphan  powerpc     mpc8260        -           -               -                   rsdproto                             -                                                                                                                                 -
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 125ba809c9..adcf163a81 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+rsdproto         powerpc     mpc8260        -           2014-04-04
 RPXsuper         powerpc     mpc8260        -           2014-04-04
 RPXClassic       powerpc     mpc8xx         -           2014-04-04
 RPXlite          powerpc     mpc8xx         -           2014-04-04
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
deleted file mode 100644
index 06211380d4..0000000000
--- a/include/configs/rsdproto.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the R&S Protocol Board board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xff000000
-#define	CONFIG_SYS_LDSCRIPT	"board/rsdproto/u-boot.lds"
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
-#define	CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-
-#if (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* enable I2C */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE		0x30
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	50000000	/* in Hz */
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_KGDB
-
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CONFIG_SYS_RSD_BOOT_LOW 1
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTARGS		"devfs=mount root=ramfs"
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5a
-#define CONFIG_NETMASK          255.255.0.0
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define PHYS_SDRAM_60X		0x00000000 /* SDRAM (60x Bus) */
-#define PHYS_SDRAM_60X_SIZE	0x08000000 /* 128 MB */
-
-#define PHYS_SDRAM_LOCAL	0x40000000 /* SDRAM (Local Bus) */
-#define PHYS_SDRAM_LOCAL_SIZE	0x04000000 /* 64 MB */
-
-#define PHYS_DPRAM_PCI		0xE8000000 /* DPRAM PPC/PCI */
-#define PHYS_DPRAM_PCI_SIZE	0x00020000 /* 128 KB */
-
-/*#define PHYS_DPRAM_PCI_SEM	0x04020000 / * DPRAM PPC/PCI Semaphore */
-/*#define PHYS_DPRAM_PCI_SEM_SIZE	0x00000001 / * 1 Byte */
-
-#define PHYS_DPRAM_SHARC	0xE8100000 /* DPRAM PPC/Sharc */
-#define PHYS_DPRAM_SHARC_SIZE	0x00040000 /* 256 KB */
-
-/*#define PHYS_DPRAM_SHARC_SEM	0x04140000 / * DPRAM PPC/Sharc Semaphore */
-/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
-
-#define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
-#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
-
-#define PHYS_USB		0x04200000 /* USB Controller (60x Bus) */
-#define PHYS_USB_SIZE		0x00000002 /* 2 Bytes */
-
-#define PHYS_IMMR		0xF0000000 /* Internal Memory Mapped Reg. */
-
-#define PHYS_FLASH		0xFF000000 /* Flash (60x Bus) */
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
-
-#define CONFIG_SYS_IMMR		PHYS_IMMR
-
-/*-----------------------------------------------------------------------
- * Reset Address
- *
- * In order to reset the CPU, U-Boot jumps to a special address which
- * causes a machine check exception. The default address for this is
- * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
- * testing the monitor in RAM using a JTAG debugger.
- *
- * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
- * cause a bus error on your hardware.
- */
-#define CONFIG_SYS_RESET_ADDRESS	0x20000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-
-#if defined(CONFIG_SYS_RSD_BOOT_LOW)
-#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
-
-/* get the HRCW ISB field from CONFIG_SYS_IMMR */
-#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
-			    ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
-			    ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
-
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_L2CPC10 | \
-			 HRCW_DPPC11 | \
-			 CONFIG_SYS_RSD_HRCW_IMMR |\
-			 HRCW_MMR00 | \
-			 HRCW_APPC10 | \
-			 HRCW_CS10PC00 | \
-			 HRCW_MODCK_H0000 |\
-			 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1	0
-#define CONFIG_SYS_HRCW_SLAVE2	0
-#define CONFIG_SYS_HRCW_SLAVE3	0
-#define CONFIG_SYS_HRCW_SLAVE4	0
-#define CONFIG_SYS_HRCW_SLAVE5	0
-#define CONFIG_SYS_HRCW_SLAVE6	0
-#define CONFIG_SYS_HRCW_SLAVE7	0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
- */
-#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_60X
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH
-/*#define	CONFIG_SYS_MONITOR_BASE	0x200000 */
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMBOOT
-#endif
-#define	CONFIG_SYS_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/
-
-/* turn off NVRAM env feature */
-#undef CONFIG_NVRAM_ENV
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR	(PHYS_FLASH + 0x28000)	/* Addr of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x8000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		0x100c0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
-					 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
-			 SYPCR_SWRI | SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR	0x00000000
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-/*
- * Init Memory Controller:
- */
-
-#define CONFIG_SYS_PSDMR	0x494D2452
-#define CONFIG_SYS_LSDMR	0x49492552
-
-/* Flash */
-#define CONFIG_SYS_BR0_PRELIM	(PHYS_FLASH | BRx_V)
-#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
-			 ORxG_BCTLD | \
-			 ORxG_SCY_5_CLK)
-
-/* DPRAM to the PCI BUS on the protocol board */
-#define CONFIG_SYS_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
-#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
-			 ORxG_ACS_DIV4)
-
-/* 60x Bus SDRAM */
-#define CONFIG_SYS_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
-#define CONFIG_SYS_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
-			 ORxS_BPD_4 | \
-			 ORxS_ROWST_PBI1_A2 | \
-			 ORxS_NUMR_13 | \
-			 ORxS_IBID)
-
-/* Virtex-FPGA - Register */
-#define CONFIG_SYS_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
-#define CONFIG_SYS_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
-			 ORxG_SCY_1_CLK | \
-			 ORxG_ACS_DIV2 | \
-			 ORxG_CSNT )
-
-/* local bus SDRAM */
-#define CONFIG_SYS_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
-#define CONFIG_SYS_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
-			 ORxS_BPD_4 | \
-			 ORxS_ROWST_PBI1_A4 | \
-			 ORxS_NUMR_13)
-
-/* DPRAM to the Sharc-Bus on the protocol board */
-#define CONFIG_SYS_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
-#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
-			 ORxG_ACS_DIV4)
-
-#endif	/* __CONFIG_H */