arm: Remove OMAP2420H4 and all omap24xx support

The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini <trini@ti.com>

22 files changed, 2 insertions, 3104 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 21b498bb7f..a406f6af8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1029,10 +1029,6 @@ Matthias Weisser <weisserm@arcor.de>
 	jadecpu		ARM926EJS (MB86R01 SoC)
 	zmx25		ARM926EJS (imx25 SoC)
 
-Richard Woodruff <r-woodruff2@ti.com>
-
-	omap2420h4	ARM1136EJS
-
 Josh Wu <josh.wu@atmel.com>
 	at91sam9n12ek	ARM926EJS (AT91SAM9N12 SoC)
 
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index edf249d902..a7e0c28c90 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -142,24 +142,6 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		/* r0 <- current position of code   */
-		add     r0, r0, #4				/* skip reset vector			*/
-	mov	r2, #64			/* r2 <- size to copy  */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next			/* loop until equal */
-	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
-#endif
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h
deleted file mode 100644
index 8522335bfc..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/bits.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0  (1<<0)
-#define BIT1  (1<<1)
-#define BIT2  (1<<2)
-#define BIT3  (1<<3)
-#define BIT4  (1<<4)
-#define BIT5  (1<<5)
-#define BIT6  (1<<6)
-#define BIT7  (1<<7)
-#define BIT8  (1<<8)
-#define BIT9  (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/clock.h b/arch/arm/include/asm/arch-omap24xx/clock.h
deleted file mode 100644
index 2e92569a9c..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/clock.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS  0x1
-
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK        0xc
-#ifdef CONFIG_APTIX
-#define DPLL_LOCK        0x1   /* stay in bypass mode */
-#else
-#define DPLL_LOCK        0x3   /* DPLL lock */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II
-;
-; Enable clocks and DPLL for:
-;  DPLL=300,	DPLLout=600	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
-;  Core=600	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=300	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
-;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
-;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
-;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
-;  IVAF=200    (dsp domain)    3          CM_CLKSEL_DSP[12:8]
-;  IVAF=100        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S          bypass                  CM_CLKSEL_DSP[13]
-;  GFXF=50      (gfx domain)	12         CM_CLKSEL_FGX[2:0]
-;  SSI_SSRF=200                 3         CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=100     auto
-;  L3=100Mhz (sdram)            6         CM_CLKSEL1_CORE[4:0]
-;  L4=100Mhz                    6
-;  C_L4_USB=50                 12         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2   0x2    /* x2 core out */
-#define II_MPU_DIV       0x2    /* mpu = core/2 */
-#define II_DSP_DIV       0x343  /* dsp & iva divider */
-#define II_GFX_DIV       0x2
-#define II_BUS_DIV       0x04601026
-#define II_DPLL_300      0x01832100
-
-/****************************************************************************;
-; PRCM Scheme III
-;
-; Enable clocks and DPLL for:
-;  DPLL=266,	DPLLout=532	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
-;  Core=532	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
-;  MPUF=266	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
-;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
-;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
-;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
-;  IVAF=88.67    (dsp domain)   /3          CM_CLKSEL_DSP[12:8]
-;  IVAF=88.67        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S         ACTIVATED                  CM_CLKSEL_DSP[13]
-;  GFXF=66.5      (gfx domain)	/8          CM_CLKSEL_FGX[2:0]:
-;  SSI_SSRF=177.3               /3          CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=88.67     auto
-;  L3=133Mhz (sdram)            /4          CM_CLKSEL1_CORE[4:0]
-;  L4=66.5Mhz                   /8
-;  C_L4_USB=33.25               /16         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2   0x2    /* x2 core out */
-#define III_MPU_DIV       0x2    /* mpu = core/2 */
-#define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV       0x2
-#define III_BUS_DIV       0x08301044
-#define III_DPLL_266      0x01885500
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_II
-# define DPLL_OUT         II_DPLL_OUT_X2
-# define MPU_DIV          II_MPU_DIV
-# define DSP_DIV          II_DSP_DIV
-# define GFX_DIV          II_GFX_DIV
-# define BUS_DIV          II_BUS_DIV
-# define DPLL_VAL         II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT         III_DPLL_OUT_X2
-# define MPU_DIV          III_MPU_DIV
-# define DSP_DIV          III_DSP_DIV
-# define GFX_DIV          III_GFX_DIV
-# define BUS_DIV          III_BUS_DIV
-# define DPLL_VAL         III_DPLL_266
-#endif
-
-/* lock delay time out */
-#define LDELAY           12000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h
deleted file mode 100644
index 6f645192a7..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/i2c.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_I2C_H_
-#define _OMAP24XX_I2C_H_
-
-#define I2C_BASE1		0x48070000
-#define I2C_BASE2               0x48072000 /* nothing hooked up on h4 */
-
-#define I2C_DEFAULT_BASE	I2C_BASE1
-
-struct i2c {
-	unsigned short rev;	/* 0x00 */
-	unsigned short res1;
-	unsigned short ie;	/* 0x04 */
-	unsigned short res2;
-	unsigned short stat;	/* 0x08 */
-	unsigned short res3;
-	unsigned short iv;	/* 0x0C */
-	unsigned short res4;
-	unsigned short syss;	/* 0x10 */
-	unsigned short res4p1;
-	unsigned short buf;	/* 0x14 */
-	unsigned short res5;
-	unsigned short cnt;	/* 0x18 */
-	unsigned short res6;
-	unsigned short data;	/* 0x1C */
-	unsigned short res7;
-	unsigned short sysc;	/* 0x20 */
-	unsigned short res8;
-	unsigned short con;	/* 0x24 */
-	unsigned short res9;
-	unsigned short oa;	/* 0x28 */
-	unsigned short res10;
-	unsigned short sa;	/* 0x2C */
-	unsigned short res11;
-	unsigned short psc;	/* 0x30 */
-	unsigned short res12;
-	unsigned short scll;	/* 0x34 */
-	unsigned short res13;
-	unsigned short sclh;	/* 0x38 */
-	unsigned short res14;
-	unsigned short systest;	/* 0x3c */
-	unsigned short res15;
-};
-
-#define I2C_BUS_MAX	2
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h
deleted file mode 100644
index 42e8ab2bce..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/mem.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET	 0x0
-#define SDRC_CS1_OSET	 0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
-   early in init when NO global access are there */
-struct sdrc_data_s {
-	u32    sdrc_sharing;
-	u32    sdrc_mdcfg_0_ddr;
-	u32    sdrc_mdcfg_0_sdr;
-	u32    sdrc_actim_ctrla_0;
-	u32    sdrc_actim_ctrlb_0;
-	u32    sdrc_rfr_ctrl;
-	u32    sdrc_mr_0_ddr;
-	u32    sdrc_mr_0_sdr;
-	u32    sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
-	STACKED		= 0,
-	IP_DDR		= 1,
-	COMBO_DDR	= 2,
-	IP_SDR		= 3,
-} mem_t;
-
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING		0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR	0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR		0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR	0x01702011 /* descrite ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR	0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR		0x00000032
-
-#define H4_2422_SDRC_SHARING		0x00004b00
-#define H4_2422_SDRC_MDCFG_0_DDR	0x00801011 /* stacked ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR		0x00000032
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1	0x9bead909  /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1	0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1	    0x00002401	/* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz  0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz  0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz  0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz  0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz	   0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz	   0x0003de01
-#define H4_242x_SDRC_DLLAB_CTRL_100MHz	   0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
-#define H4_242x_SDRC_DLLAB_CTRL_133MHz	   0x0000690E /* 72deg, for ES2 */
-
-#ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-#elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_II	     /* L3 at 100MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-#  define H4_24XX_GPMC_CONFIG1_0   0x0
-#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-# else	/* else NOR */
-#  define H4_24XX_GPMC_CONFIG1_0   0x3
-#  define H4_24XX_GPMC_CONFIG2_0   0x000f0f01
-#  define H4_24XX_GPMC_CONFIG3_0   0x00050502
-#  define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
-#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
-# define H4_24XX_GPMC_CONFIG2_1	  0x001F1F00
-# define H4_24XX_GPMC_CONFIG3_1	  0x00080802
-# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1	  0x031A1F1F
-# define H4_24XX_GPMC_CONFIG6_1	  0x000003C2
-# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III	/* L3 at 133MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-#  define H4_24XX_GPMC_CONFIG1_0   0x0
-#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-# else	/* NOR boot */
-#  define H4_24XX_GPMC_CONFIG1_0   0x3
-#  define H4_24XX_GPMC_CONFIG2_0   0x00151501
-#  define H4_24XX_GPMC_CONFIG3_0   0x00060602
-#  define H4_24XX_GPMC_CONFIG4_0   0x10081008
-#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-#  define H4_24XX_GPMC_CONFIG6_0   0x000004c4
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
-# define H4_24XX_GPMC_CONFIG2_1	  0x001f1f01
-# define H4_24XX_GPMC_CONFIG3_1	  0x00080803
-# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1	  0x041f1F1F
-# define H4_24XX_GPMC_CONFIG6_1	  0x000004C4
-# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif CONFIG_SYS_PRCM_III */
-
-#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h
deleted file mode 100644
index 4fdb9c635f..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/mux.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP2420_MUX_H_
-#define _OMAP2420_MUX_H_
-
-#ifndef __ASSEMBLY__
-typedef  unsigned char uint8;
-typedef  unsigned int uint32;
-
-void muxSetupSDRC(void);
-void muxSetupGPMC(void);
-void muxSetupUsb0(void);
-void muxSetupUsbHost(void);
-void muxSetupUart3(void);
-void muxSetupI2C1(void);
-void muxSetupUART1(void);
-void muxSetupLCD(void);
-void muxSetupCamera(void);
-void muxSetupMMCSD(void) ;
-void muxSetupTouchScreen(void) ;
-void muxSetupHDQ(void);
-#endif
-
-#define USB_OTG_CTRL			        ((volatile uint32 *)0x4805E30C)
-
-/* Pin Muxing registers used for HDQ (Smart battery) */
-#define CONTROL_PADCONF_HDQ_SIO         ((volatile unsigned char *)0x48000115)
-
-/* Pin Muxing registers used for GPMC */
-#define CONTROL_PADCONF_GPMC_D2_BYTE0	((volatile unsigned char *)0x48000088)
-#define CONTROL_PADCONF_GPMC_D2_BYTE1	((volatile unsigned char *)0x48000089)
-#define CONTROL_PADCONF_GPMC_D2_BYTE2	((volatile unsigned char *)0x4800008A)
-#define CONTROL_PADCONF_GPMC_D2_BYTE3	((volatile unsigned char *)0x4800008B)
-
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE0	((volatile unsigned char *)0x4800008C)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE1	((volatile unsigned char *)0x4800008D)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE2	((volatile unsigned char *)0x4800008E)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE3	((volatile unsigned char *)0x4800008F)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE4	(0x48000090)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE5	(0x48000091)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE6	(0x48000092)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE7	(0x48000093)
-
-/* Pin Muxing registers used for SDRC */
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
-
-#define CONTROL_PADCONF_SDRC_A14_BYTE0	((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A14_BYTE1	((volatile unsigned char *)0x48000031)
-#define CONTROL_PADCONF_SDRC_A14_BYTE2	((volatile unsigned char *)0x48000032)
-#define CONTROL_PADCONF_SDRC_A14_BYTE3	((volatile unsigned char *)0x48000033)
-
-/* Pin Muxing registers used for Touch Screen (SPI) */
-#define CONTROL_PADCONF_SPI1_CLK        ((volatile unsigned char *)0x480000FF)
-#define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
-#define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
-#define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
-#define CONTROL_PADCONF_SPI1_NCS1       (0x48000103)
-
-#define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
-
-/* Pin Muxing registers used for MMCSD */
-#define CONTROL_PADCONF_MMC_CLKI        ((volatile unsigned char *)0x480000FE)
-#define CONTROL_PADCONF_MMC_CLKO        ((volatile unsigned char *)0x480000F3)
-#define CONTROL_PADCONF_MMC_CMD         ((volatile unsigned char *)0x480000F4)
-#define CONTROL_PADCONF_MMC_DAT0        ((volatile unsigned char *)0x480000F5)
-#define CONTROL_PADCONF_MMC_DAT1        ((volatile unsigned char *)0x480000F6)
-#define CONTROL_PADCONF_MMC_DAT2        ((volatile unsigned char *)0x480000F7)
-#define CONTROL_PADCONF_MMC_DAT3        ((volatile unsigned char *)0x480000F8)
-#define CONTROL_PADCONF_MMC_DAT_DIR0    ((volatile unsigned char *)0x480000F9)
-#define CONTROL_PADCONF_MMC_DAT_DIR1    ((volatile unsigned char *)0x480000FA)
-#define CONTROL_PADCONF_MMC_DAT_DIR2    ((volatile unsigned char *)0x480000FB)
-#define CONTROL_PADCONF_MMC_DAT_DIR3    ((volatile unsigned char *)0x480000FC)
-#define CONTROL_PADCONF_MMC_CMD_DIR     ((volatile unsigned char *)0x480000FD)
-
-#define CONTROL_PADCONF_SDRC_A14        ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A13        ((volatile unsigned char *)0x48000031)
-
-/* Pin Muxing registers used for CAMERA */
-#define CONTROL_PADCONF_SYS_NRESWARM    ((volatile unsigned char *)0x4800012B)
-
-#define CONTROL_PADCONF_CAM_XCLK        ((volatile unsigned char *)0x480000DC)
-#define CONTROL_PADCONF_CAM_LCLK        ((volatile unsigned char *)0x480000DB)
-#define CONTROL_PADCONF_CAM_VS          ((volatile unsigned char *)0x480000DA)
-#define CONTROL_PADCONF_CAM_HS          ((volatile unsigned char *)0x480000D9)
-#define CONTROL_PADCONF_CAM_D0          ((volatile unsigned char *)0x480000D8)
-#define CONTROL_PADCONF_CAM_D1          ((volatile unsigned char *)0x480000D7)
-#define CONTROL_PADCONF_CAM_D2          ((volatile unsigned char *)0x480000D6)
-#define CONTROL_PADCONF_CAM_D3          ((volatile unsigned char *)0x480000D5)
-#define CONTROL_PADCONF_CAM_D4          ((volatile unsigned char *)0x480000D4)
-#define CONTROL_PADCONF_CAM_D5          ((volatile unsigned char *)0x480000D3)
-#define CONTROL_PADCONF_CAM_D6          ((volatile unsigned char *)0x480000D2)
-#define CONTROL_PADCONF_CAM_D7          ((volatile unsigned char *)0x480000D1)
-#define CONTROL_PADCONF_CAM_D8          ((volatile unsigned char *)0x480000D0)
-#define CONTROL_PADCONF_CAM_D9          ((volatile unsigned char *)0x480000CF)
-
-/* Pin Muxing registers used for LCD */
-#define CONTROL_PADCONF_DSS_D0          ((volatile unsigned char *)0x480000B3)
-#define CONTROL_PADCONF_DSS_D1          ((volatile unsigned char *)0x480000B4)
-#define CONTROL_PADCONF_DSS_D2          ((volatile unsigned char *)0x480000B5)
-#define CONTROL_PADCONF_DSS_D3          ((volatile unsigned char *)0x480000B6)
-#define CONTROL_PADCONF_DSS_D4          ((volatile unsigned char *)0x480000B7)
-#define CONTROL_PADCONF_DSS_D5          ((volatile unsigned char *)0x480000B8)
-#define CONTROL_PADCONF_DSS_D6          ((volatile unsigned char *)0x480000B9)
-#define CONTROL_PADCONF_DSS_D7          ((volatile unsigned char *)0x480000BA)
-#define CONTROL_PADCONF_DSS_D8          ((volatile unsigned char *)0x480000BB)
-#define CONTROL_PADCONF_DSS_D9          ((volatile unsigned char *)0x480000BC)
-#define CONTROL_PADCONF_DSS_D10         ((volatile unsigned char *)0x480000BD)
-#define CONTROL_PADCONF_DSS_D11         ((volatile unsigned char *)0x480000BE)
-#define CONTROL_PADCONF_DSS_D12         ((volatile unsigned char *)0x480000BF)
-#define CONTROL_PADCONF_DSS_D13         ((volatile unsigned char *)0x480000C0)
-#define CONTROL_PADCONF_DSS_D14         ((volatile unsigned char *)0x480000C1)
-#define CONTROL_PADCONF_DSS_D15         ((volatile unsigned char *)0x480000C2)
-#define CONTROL_PADCONF_DSS_D16         ((volatile unsigned char *)0x480000C3)
-#define CONTROL_PADCONF_DSS_D17         ((volatile unsigned char *)0x480000C4)
-#define CONTROL_PADCONF_DSS_PCLK        ((volatile unsigned char *)0x480000CB)
-#define CONTROL_PADCONF_DSS_VSYNC       ((volatile unsigned char *)0x480000CC)
-#define CONTROL_PADCONF_DSS_HSYNC       ((volatile unsigned char *)0x480000CD)
-#define CONTROL_PADCONF_DSS_ACBIAS      ((volatile unsigned char *)0x480000CE)
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS       ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS       ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX        ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX        ((volatile unsigned char *)0x480000C8)
-
-/* Pin Muxing registers used for I2C1 */
-#define CONTROL_PADCONF_I2C1_SCL        ((volatile unsigned char *)0x48000111)
-#define CONTROL_PADCONF_I2C1_SDA        ((volatile unsigned char *)0x48000112)
-
-/* Pin Muxing registres used for USB0. */
-#define CONTROL_PADCONF_USB0_PUEN		((volatile uint8 *)0x4800011D)
-#define CONTROL_PADCONF_USB0_VP			((volatile uint8 *)0x4800011E)
-#define CONTROL_PADCONF_USB0_VM			((volatile uint8 *)0x4800011F)
-#define CONTROL_PADCONF_USB0_RCV		((volatile uint8 *)0x48000120)
-#define CONTROL_PADCONF_USB0_TXEN		((volatile uint8 *)0x48000121)
-#define CONTROL_PADCONF_USB0_SE0		((volatile uint8 *)0x48000122)
-#define CONTROL_PADCONF_USB0_DAT		((volatile uint8 *)0x48000123)
-
-/* Pin Muxing registres used for USB1. */
-#define CONTROL_PADCONF_USB1_RCV	(0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN	(0x480000EC)
-
-/* Pin Muxing registers used for UART3/IRDA */
-#define CONTROL_PADCONF_UART3_TX_IRTX	((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_UART3_RX_IRRX	((volatile uint8 *)0x48000119)
-
-/* Pin Muxing registers used for GPIO */
-#define CONTROL_PADCONF_GPIO69		(0x480000ED)
-#define CONTROL_PADCONF_GPIO70		(0x480000EE)
-#define CONTROL_PADCONF_GPIO102		(0x48000116)
-#define CONTROL_PADCONF_GPIO103		(0x48000117)
-#define CONTROL_PADCONF_GPIO104		(0x48000118)
-#define CONTROL_PADCONF_GPIO105		(0x48000119)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h
deleted file mode 100644
index 5724f5d4ba..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/omap2420.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/sizes.h>
-
-/*
- * 2420 specific Section
- */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0        0x68005048
-#define A_READPERM0           0x68005050
-#define A_WRITEPERM0          0x68005058
-/* #define GP_DEVICE	(BIT8|BIT9)  FIXME -- commented out to make compile -- FIXME */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0        0x68005048
-#define A_READPERM0           0x68005050
-#define A_WRITEPERM0          0x68005058
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE    (0x48000000)
-#define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* device type */
-#define TST_DEVICE	0x0
-#define EMU_DEVICE	0x1
-#define HS_DEVICE	0x2
-#define GP_DEVICE	0x3
-
-/* TAP information */
-#define OMAP2420_TAP_BASE     (0x48014000)
-#define TAP_IDCODE_REG        (OMAP2420_TAP_BASE+0x204)
-#define PRODUCTION_ID         (OMAP2420_TAP_BASE+0x208)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE    (0x6800A000)
-#define GPMC_SYSCONFIG        (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_IRQENABLE        (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL  (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG           (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0        (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0        (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0        (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0        (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0        (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0        (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0	      (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1        (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1        (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1        (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1        (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_2        (OMAP2420_GPMC_BASE+0xC0)
-#define GPMC_CONFIG2_2        (OMAP2420_GPMC_BASE+0xC4)
-#define GPMC_CONFIG3_2        (OMAP2420_GPMC_BASE+0xC8)
-#define GPMC_CONFIG4_2        (OMAP2420_GPMC_BASE+0xCC)
-#define GPMC_CONFIG5_2        (OMAP2420_GPMC_BASE+0xD0)
-#define GPMC_CONFIG6_2        (OMAP2420_GPMC_BASE+0xD4)
-#define GPMC_CONFIG7_2        (OMAP2420_GPMC_BASE+0xD8)
-#define GPMC_CONFIG1_3        (OMAP2420_GPMC_BASE+0xF0)
-#define GPMC_CONFIG2_3        (OMAP2420_GPMC_BASE+0xF4)
-#define GPMC_CONFIG3_3        (OMAP2420_GPMC_BASE+0xF8)
-#define GPMC_CONFIG4_3        (OMAP2420_GPMC_BASE+0xFC)
-#define GPMC_CONFIG5_3        (OMAP2420_GPMC_BASE+0x100)
-#define GPMC_CONFIG6_3        (OMAP2420_GPMC_BASE+0x104)
-#define GPMC_CONFIG7_3	      (OMAP2420_GPMC_BASE+0x108)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG     (OMAP2420_SMS_BASE+0x10)
-#define SMS_CLASS_ARB0    (OMAP2420_SMS_BASE+0xD0)
-# define BURSTCOMPLETE_GROUP7    BIT31
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG     (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS        (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_CS_CFG        (OMAP2420_SDRC_BASE+0x40)
-#define SDRC_SHARING       (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL     (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLB_CTRL     (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER         (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0        (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0          (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL      (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0      (OMAP2420_SDRC_BASE+0xA8)
-#define OMAP2420_SDRC_CS0  0x80000000
-#define OMAP2420_SDRC_CS1  0xA0000000
-#define CMD_NOP            0x0
-#define CMD_PRECHARGE      0x1
-#define CMD_AUTOREFRESH    0x2
-#define CMD_ENTR_PWRDOWN   0x3
-#define CMD_EXIT_PWRDOWN   0x4
-#define CMD_ENTR_SRFRSH    0x5
-#define CMD_CKE_HIGH       0x6
-#define CMD_CKE_LOW        0x7
-#define SOFTRESET          BIT1
-#define SMART_IDLE         (0x2 << 3)
-#define REF_ON_IDLE        (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1	      0x4806A000
-#define OMAP2420_UART2	      0x4806C000
-#define OMAP2420_UART3        0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1         0x48028000
-#define OMAP2420_GPT2         0x4802A000
-#define OMAP2420_GPT3         0x48078000
-#define OMAP2420_GPT4         0x4807A000
-#define OMAP2420_GPT5         0x4807C000
-#define OMAP2420_GPT6         0x4807E000
-#define OMAP2420_GPT7         0x48080000
-#define OMAP2420_GPT8         0x48082000
-#define OMAP2420_GPT9         0x48084000
-#define OMAP2420_GPT10        0x48086000
-#define OMAP2420_GPT11        0x48088000
-#define OMAP2420_GPT12        0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR       0x0      /* r */
-#define TIOCP_CFG  0x10     /* rw */
-#define TISTAT     0x14     /* r */
-#define TISR       0x18     /* rw */
-#define TIER       0x1C     /* rw */
-#define TWER       0x20     /* rw */
-#define TCLR       0x24     /* rw */
-#define TCRR       0x28     /* rw */
-#define TLDR       0x2C     /* rw */
-#define TTGR       0x30     /* rw */
-#define TWPS       0x34     /* r */
-#define TMAR       0x38     /* rw */
-#define TCAR1      0x3c     /* r */
-#define TSICR      0x40     /* rw */
-#define TCAR2      0x44     /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE              0x48020000
-#define WD2_BASE              0x48022000
-#define WD3_BASE              0x48024000
-#define WD4_BASE              0x48026000
-#define WWPS       0x34     /* r */
-#define WSPR       0x48     /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU    (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE  (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE  (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE  (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE  (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE  (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP   (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE  (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX    (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP  (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL     (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN  (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL   (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL   (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP    (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- *  The 2420's chip selects are programmable.  The mask ROM
- *  does configure CS0 to 0x08000000 before dispatch.  So, if
- *  you want your code to live below that address, you have to
- *  be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A        /* Pre version B */
-# define H4_CS0_BASE           0x08000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x04000000  /* debug board */
-# define H4_CS2_BASE           0x0A000000  /* wifi board */
-#else
-# define H4_CS0_BASE           0x08000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x04000000  /* debug board */
-# define H4_CS2_BASE           0x0C000000  /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0          0x40000000
-#define SRAM_OFFSET1          0x00200000
-#define SRAM_OFFSET2          0x0000F800
-#define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
-#endif  /* endif CONFIG_2420H4 */
-
-/* Common */
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h
deleted file mode 100644
index 53c231a5e4..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_info.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-typedef struct  h4_system_data {
-	/* base board info */
-	u32 base_b_rev;		/* rev from base board i2c */
-	/* cpu board info */
-	u32 cpu_b_rev;		/* rev from cpu board i2c */
-	u32 cpu_b_mux;		/* mux type on daughter board */
-	u32 cpu_b_ddr_type;	/* mem type */
-	u32 cpu_b_ddr_speed;	/* ddr speed rating */
-	u32 cpu_b_switches;	/* boot ctrl switch settings */
-	/* cpu info */
-	u32 cpu_type;		/* type of cpu; 2420, 2422, 2430,...*/
-	u32 cpu_rev;		/* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define XDR_POP           5      /* package on package part */
-#define SDR_DISCRETE      4      /* 128M memory SDR module*/
-#define DDR_STACKED       3      /* stacked part on 2422 */
-#define DDR_COMBO         2      /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE      1      /* 2x16 parts on daughter card */
-
-#define DDR_100           100    /* type found on most mem d-boards */
-#define DDR_111           111    /* some combo parts */
-#define DDR_133           133    /* most combo, some mem d-boards */
-#define DDR_165           165    /* future parts */
-
-#define CPU_2420          0x2420
-#define CPU_2422          0x2422 /* 2420 + 64M stacked */
-#define CPU_2423          0x2423 /* 2420 + 96M stacked */
-
-#define CPU_2422_ES1      1
-#define CPU_2422_ES2      2
-#define CPU_2420_ES1      1
-#define CPU_2420_ES2      2
-#define CPU_2420_2422_ES1 1
-
-#define CPU_2420_CHIPID   0x0B5D9000
-#define CPU_24XX_ID_MASK  0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS 1
-#define BOARD_H4_SDP      2
-
-#define GPMC_MUXED        1
-#define GPMC_NONMUXED     0
-
-#define TYPE_NAND         0x800   /* bit pos for nand in gpmc reg */
-#define TYPE_NOR          0x000
-
-#define WIDTH_8BIT        0x0000
-#define WIDTH_16BIT       0x1000  /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72	/* i2c id for companion chip */
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h
deleted file mode 100644
index 9d8e5b2622..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_proto.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP24XX_SYS_PROTO_H_
-#define _OMAP24XX_SYS_PROTO_H_
-
-void prcm_init(void);
-void memif_init(void);
-void sdrc_init(void);
-void do_sdrc_init(u32,u32);
-void gpmc_init(void);
-
-void ether_init(void);
-void watchdog_init(void);
-void set_muxconf_regs(void);
-void peripheral_enable(void);
-
-u32 get_cpu_type(void);
-u32 get_cpu_rev(void);
-u32 get_mem_type(void);
-u32 get_sysboot_value(void);
-u32 get_gpmc0_base(void);
-u32 is_gpmc_muxed(void);
-u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
-u32 get_board_type(void);
-void display_board_info(u32);
-void update_mux(u32,u32);
-u32 get_sdr_cs_size(u32 offset);
-
-u32 running_in_sdram(void);
-u32 running_in_sram(void);
-u32 running_in_flash(void);
-u32 running_from_internal_boot(void);
-u32 get_device_type(void);
-#endif
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index b545fb79bc..8b1c8ed4bf 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -27,7 +27,7 @@
 
 void  __flush_cache(unsigned long start, unsigned long size)
 {
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
+#if defined(CONFIG_ARM1136)
 	void arm1136_cache_flush(void);
 
 	arm1136_cache_flush();
diff --git a/board/ti/omap2420h4/Makefile b/board/ti/omap2420h4/Makefile
deleted file mode 100644
index cddd7e6985..0000000000
--- a/board/ti/omap2420h4/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= omap2420h4.o mem.o sys_info.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk
deleted file mode 100644
index e5dff69a15..0000000000
--- a/board/ti/omap2420h4/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-#CONFIG_SYS_TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-#CONFIG_SYS_TEXT_BASE = 0x40270000
-
-
-# Handy to get symbols to debug ROM version.
-#CONFIG_SYS_TEXT_BASE = 0x0
-CONFIG_SYS_TEXT_BASE = 0x08000000
-#CONFIG_SYS_TEXT_BASE = 0x04000000
diff --git a/board/ti/omap2420h4/lowlevel_init.S b/board/ti/omap2420h4/lowlevel_init.S
deleted file mode 100644
index 2b5f338545..0000000000
--- a/board/ti/omap2420h4/lowlevel_init.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clock.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
-	/* Copy DPLL code into SRAM */
-	adr	r0, go_to_speed		/* get addr of clock setting code */
-	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
-	mov	r1, r1			/* r1 <- dest address (passed in) */
-	add	r2, r2, r0		/* r2 <- source end address */
-next2:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next2
-	mov	pc, lr			/* back to caller */
-
-/* ****************************************************************************
- *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- *		 -executed from SRAM.
- *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- *  R2 = dpll value
- *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
-	sub	sp, sp, #0x4 /* get some stack space */
-	str	r4, [sp]     /* save r4's value */
-
-	/* move into fast relock bypass */
-	ldr	r8, pll_ctl_add
-	mov	r4, #0x2
-	str	r4, [r8]
-	ldr	r4, pll_stat
-block:
-	ldr	r8, [r4]	/* wait for bypass to take effect */
-	and	r8, r8, #0x3
-	cmp	r8, #0x1
-	bne	block
-
-	/* set new dpll dividers _after_ in bypass */
-	ldr	r4, pll_div_add
-	ldr	r8, pll_div_val
-	str	r8, [r4]
-
-	/* now prepare GPMC (flash) for new dpll speed */
-	/* flash needs to be stable when we jump back to it */
-	ldr	r4, cfg3_0_addr
-	ldr	r8, cfg3_0_val
-	str	r8, [r4]
-	ldr	r4, cfg4_0_addr
-	ldr	r8, cfg4_0_val
-	str	r8, [r4]
-	ldr	r4, cfg1_0_addr
-	ldr	r8, [r4]
-	orr	r8, r8, #0x3	 /* up gpmc divider */
-	str	r8, [r4]
-
-	/* setup to 2x loop though code.  The first loop pre-loads the
-	 * icache, the 2nd commits the prcm config, and locks the dpll
-	 */
-	mov	r4, #0x1000	 /* spin spin spin */
-	mov	r8, #0x4	 /* first pass condition & set registers */
-	cmp	r8, #0x4
-2:
-	ldrne	r8, [r3]	 /* DPLL lock check */
-	and	r8, r8, #0x7
-	cmp	r8, #0x2
-	beq	4f
-3:
-	subeq	r8, r8, #0x1
-	streq	r8, [r0]	 /* commit dividers (2nd time) */
-	nop
-lloop1:
-	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
-	nop
-	cmp	r4, #0x0
-	bne	lloop1
-	mov	r4, #0x40000
-	cmp	r8, #0x1
-	nop
-	streq	r2, [r1]	/* lock dpll (2nd time) */
-	nop
-lloop2:
-	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
-	nop
-	cmp	r4, #0x0
-	bne	lloop2
-	mov	r4, #0x40000
-	cmp	r8, #0x1
-	nop
-	ldreq	r8, [r3]	 /* get lock condition for dpll */
-	cmp	r8, #0x4	 /* first time though? */
-	bne	2b
-	moveq	r8, #0x2	 /* set to dpll check condition. */
-	beq	3b		 /* if condition not true branch */
-4:
-	ldr	r4, [sp]
-	add	sp, sp, #0x4	 /* return stack space */
-	mov	pc, lr		 /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
-    .word  GPMC_CONFIG3_0
-cfg3_0_val:
-    .word  H4_24XX_GPMC_CONFIG3_0
-cfg4_0_addr:
-    .word  GPMC_CONFIG4_0
-cfg4_0_val:
-    .word  H4_24XX_GPMC_CONFIG4_0
-cfg1_0_addr:
-    .word  GPMC_CONFIG1_0
-pll_ctl_add:
-    .word CM_CLKEN_PLL
-pll_stat:
-    .word CM_IDLEST_CKGEN
-pll_div_add:
-    .word CM_CLKSEL1_PLL
-pll_div_val:
-    .word DPLL_VAL	/* DPLL setting (300MHz default) */
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr	sp,	SRAM_STACK
-	str	ip,	[sp]	/* stash old link register */
-	mov	ip,	lr	/* save link reg across call */
-	bl	s_init		/* go setup pll,mux,memory */
-	ldr	ip,	[sp]	/* restore save ip */
-	mov	lr,	ip	/* restore link reg */
-
-	/* map interrupt controller */
-	ldr	r0,	VAL_INTH_SETUP
-	mcr	p15, 0, r0, c15, c2, 4
-
-	/* back to arch calling code */
-	mov	pc,	lr
-
-	/* the literal pools origin */
-	.ltorg
-
-REG_CONTROL_STATUS:
-	.word CONTROL_STATUS
-VAL_INTH_SETUP:
-	.word PERIFERAL_PORT_BASE
-SRAM_STACK:
-	.word LOW_LEVEL_SRAM_STACK
diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c
deleted file mode 100644
index b0832389ee..0000000000
--- a/board/ti/omap2420h4/mem.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in 12MHz bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*********************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
- *   -- called from SRAM, or Flash (using temp SRAM stack).
- *********************************************************************************/
-void prcm_init(void)
-{
-	u32 div;
-	void (*f_lock_pll) (u32, u32, u32, u32);
-	extern void *_end_vect, *_start;
-
-	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
-
-	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
-	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
-	__raw_writel(0, CM_ICLKEN1_CORE);
-	__raw_writel(0, CM_ICLKEN2_CORE);
-
-	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
-	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
-	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
-	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
-
-	div = BUS_DIV;
-	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
-	sdelay(1000);
-
-	if(running_in_sram()){
-		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
-		* but then comes back.  If running from Flash this sequence kills you, thus you need
-		* to run it using CONFIG_PARTIAL_SRAM.
-		*/
-		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
-		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
-		sdelay(1000);
-		/* set clock selection and dpll dividers. */
-		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
-		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
-		sdelay(10000);
-		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
-		sdelay(10000);
-		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
-	}else if(running_in_flash()){
-		/* if running from flash, need to jump to small relocated code area in SRAM.
-		 * This is the only safe spot to do configurations from.
-		 */
-		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
-	}
-
-	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
-	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
-	sdelay(1000);
-}
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontigious support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(SDRC_CS0_OSET);
-	size /= SZ_32M;  /* find size to offset CS1 */
-	a_add_high = (size & 3) << 8;   /* set up low field */
-	a_add_low = (size & 0x3C) >> 2; /* set up high field */
-	__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
-
-}
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in gussing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(void)
-{
-	u32 val1, val2;
-	u32 pattern = 0x12345678;
-
-	__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400);   /* clear pos A */
-	__raw_writel(pattern, OMAP2420_SDRC_CS0);    /* pattern to pos B */
-	__raw_writel(0x0,OMAP2420_SDRC_CS0+4);       /* remove pattern off the bus */
-	val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
-	val2 = __raw_readl(OMAP2420_SDRC_CS0);       /* get val2 */
-
-	if ((val1 != 0) || (val2 != pattern))        /* see if pos A value changed*/
-		return(0);
-	else
-		return(1);
-}
-
-
-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-	#define EARLY_INIT 1
-	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);  /* only init up first bank here */
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -called from low level code with stack only.
- *  -code sets up SDRAM timing and muxing for 2422 or 2420.
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  This is a bit ugly, but should handle all memory moduels
- *   used with the H4. The first time though this code from s_init()
- *   we configure the first chip select.  Later on we come back and
- *   will configure the 2nd chip select if it exists.
- *
- **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early)
-{
-	u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
-	sdrc_data_t *sdata;	 /* do not change type */
-	u32 a, b, r;
-
-	static const sdrc_data_t sdrc_2422 =
-	{
-		H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
-		H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
-		0, H4_2422_SDRC_DLLAB_CTRL
-	};
-	static const sdrc_data_t sdrc_2420 =
-	{
-		H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
-		H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
-		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
-		H4_2420_SDRC_DLLAB_CTRL
-	};
-
-	if (offset == SDRC_CS0_OSET)
-		cs0 = common = 1;  /* int regs shared between both chip select */
-
-	cpu = get_cpu_type();
-	rev = get_cpu_rev();
-
-	/* warning generated, though code generation is correct. this may bite later,
-	 * but is ok for now. there is only so much C code you can do on stack only
-	 * operation.
-	 */
-	if (cpu == CPU_2422){
-		sdata = (sdrc_data_t *)&sdrc_2422;
-		pass_type = STACKED;
-	} else{
-		sdata = (sdrc_data_t *)&sdrc_2420;
-		pass_type = IP_DDR;
-	}
-
-	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
-
-	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
-		if(mtype == DDR_COMBO){
-			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
-			pass_type = COMBO_DDR; /* CS1 config */
-			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
-		}
-		if(rev != CPU_2420_2422_ES1)	/* for es2 and above smooth things out */
-			make_cs1_contiguous();
-	}
-
-next_mem_type:
-	if (common) {	/* do a SDRC reset between types to clear regs*/
-		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
-		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
-		__raw_writel(0, SDRC_SYSCONFIG);		/* clear soft reset */
-		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
-#ifdef POWER_SAVE
-		__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
-		__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
-		__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
-#endif
-	}
-
-	if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
-		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
-	else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
-		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
-	} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
-		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
-	}
-
-	a = sdata->sdrc_actim_ctrla_0;
-	b = sdata->sdrc_actim_ctrlb_0;
-	r = sdata->sdrc_dllab_ctrl;
-
-	/* work around ES1 DDR issues */
-	if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
-		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
-		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
-		r = H4_242x_SDRC_RFR_CTRL_ES1;
-	}
-
-	if (cs0) {
-		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
-		__raw_writel(b, SDRC_ACTIM_CTRLB_0);
-	} else {
-		__raw_writel(a, SDRC_ACTIM_CTRLA_1);
-		__raw_writel(b, SDRC_ACTIM_CTRLB_1);
-	}
-	__raw_writel(r, SDRC_RFR_CTRL+offset);
-
-	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
-	__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
-	sdelay(5000);  /* susposed to be 100us per design spec for mddr/msdr */
-	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
-	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
-	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
-
-	/*
-	 * CSx SDRC Mode Register
-	 * Burst length = (4 - DDR) (2-SDR)
-	 * Serial mode
-	 * CAS latency = x
-	 */
-	if(pass_type == IP_SDR)
-		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
-	else
-		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
-
-	/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
-	if (rev == CPU_2420_2422_ES1){
-		dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
-		__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
-			,SMS_CLASS_ARB0);/* enable bust complete for lcd */
-	}
-	else
-		dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
-
-	/* enable & load up DLL with good value for 75MHz, and set phase to 90
-	 * ES1 recommends 90 phase, ES2 recommends 72 phase.
-	 */
-	if (common && (pass_type != IP_SDR)) {
-		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
-	}
-	sdelay(90000);
-
-	if(mem_ok())
-		return; /* STACKED, other configued type */
-	++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
-	goto next_mem_type;
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	u32 mux=0, mtype, mwidth, rev, tval;
-
-	rev  = get_cpu_rev();
-	if (rev == CPU_2420_2422_ES1)
-		tval = 1;
-	else
-		tval = 0;  /* disable bit switched meaning */
-
-	/* global settings */
-	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
-	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
-	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CONFIG_SYS_NAND_BOOT
-	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
-#else
-	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
-#endif
-
-	/* discover bus connection from sysboot */
-	if (is_gpmc_muxed() == GPMC_MUXED)
-		mux = BIT9;
-	mtype = get_gpmc0_type();
-	mwidth = get_gpmc0_width();
-
-	/* setup cs0 */
-	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
-	sdelay(1000);
-
-#ifdef CONFIG_SYS_NAND_BOOT
-	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
-#else
-	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
-#endif
-
-#ifdef PRCM_CONFIG_III
-	__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
-#endif
-	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
-	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
-#ifdef PRCM_CONFIG_III
-	__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
-	__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
-#endif
-	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
-	sdelay(2000);
-
-	/* setup cs1 */
-	__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
-	sdelay(1000);
-	__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
-	sdelay(2000);
-}
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
deleted file mode 100644
index 532e989bac..0000000000
--- a/board/ti/omap2420h4/omap2420h4.c
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/mem.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void wait_for_command_complete(unsigned int wd_base);
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
-	gpmc_init(); /* in SRAM or SDRM, finish GPMC */
-
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;		/* board id for linux */
-	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);	/* adress of boot parameters */
-
-	return 0;
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- *  general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
-	/* if GP device unlock device SRAM for general use */
-	if (get_device_type() == GP_DEVICE) {
-		__raw_writel(0xFF, A_REQINFOPERM0);
-		__raw_writel(0xCFDE, A_READPERM0);
-		__raw_writel(0xCFDE, A_WRITEPERM0);
-	}
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with sram stack.
- **********************************************************/
-void s_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	watchdog_init();
-	set_muxconf_regs();
-	delay(100);
-	try_unlock_sram();
-
-	if(!in_sdram)
-		prcm_init();
-
-	peripheral_enable();
-	icache_enable();
-	if (!in_sdram)
-		sdrc_init();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
-	ether_init(); /* better done here so timers are init'ed */
-	return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
-	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
-	* The ROM takes care of the secure one. Of the 3 GP ones,
-	* 1 can reset us directly, the other 2 only generate MPU interrupts.
-	*/
-	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
-	wait_for_command_complete(WD2_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
-	__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
-	wait_for_command_complete(WD3_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
-
-	__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
-	wait_for_command_complete(WD4_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
-#endif
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
-	int pending = 1;
-	do {
-		pending = __raw_readl(wd_base+WWPS);
-	} while (pending);
-}
-
-/*******************************************************************
- * Routine:ether_init
- * Description: take the Ethernet controller out of reset and wait
- *		   for the EEPROM load to complete.
- ******************************************************************/
-void ether_init (void)
-{
-#ifdef CONFIG_LAN91C96
-	int cnt = 20;
-
-	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
-
-	__raw_writew(0x0, LAN_RESET_REGISTER);
-	do {
-		__raw_writew(0x1, LAN_RESET_REGISTER);
-		udelay (100);
-		if (cnt == 0)
-			goto h4reset_err_out;
-		--cnt;
-	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-
-	cnt = 20;
-
-	do {
-		__raw_writew(0x0, LAN_RESET_REGISTER);
-		udelay (100);
-		if (cnt == 0)
-			goto h4reset_err_out;
-		--cnt;
-	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
-	udelay (1000);
-
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (1000);
-
-	h4reset_err_out:
-	return;
-#endif
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
-	unsigned int size0=0,size1=0;
-	u32 mtype, btype;
-	u8 chg_on = 0x5; /* enable charge of back up battery */
-	u8 vmode_on = 0x8C;
-	#define NOT_EARLY 0
-
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
-
-	btype = get_board_type();
-	mtype = get_mem_type();
-
-	display_board_info(btype);
-	if (btype == BOARD_H4_MENELAUS){
-		update_mux(btype,mtype); /* combo part on menelaus */
-		i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
-		i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
-	}
-
-	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
-		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
-	}
-	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
-	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	unsigned int size0, size1;
-	u32 rev;
-
-	rev = get_cpu_rev();
-	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
-	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
-	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
-		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	else /* ES2 and above can remap at 32MB granularity */
-		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
-	gd->bd->bi_dram[1].size = size1;
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-}
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- *              specific to the hardware
- *********************************************************/
-void set_muxconf_regs (void)
-{
-	muxSetupSDRC();
-	muxSetupGPMC();
-	muxSetupUsb0();
-	muxSetupUart3();
-	muxSetupI2C1();
-	muxSetupUART1();
-	muxSetupLCD();
-	muxSetupCamera();
-	muxSetupMMCSD();
-	muxSetupTouchScreen();
-	muxSetupHDQ();
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void peripheral_enable(void)
-{
-	unsigned int v, if_clks=0, func_clks=0;
-
-	/* Enable GP2 timer.*/
-	if_clks |= BIT4;
-	func_clks |= BIT4;
-	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP2420_GPT2 */
-	__raw_writel(v, CM_CLKSEL2_CORE);
-	__raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CONFIG_SYS_NS16550
-	/* Enable UART1 clock */
-	func_clks |= BIT21;
-	if_clks |= BIT21;
-#endif
-	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
-	__raw_writel(v,CM_ICLKEN1_CORE );
-	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
-	__raw_writel(v, CM_FCLKEN1_CORE);
-	delay(1000);
-
-#ifndef KERNEL_UPDATED
-	{
-#define V1 0xffffffff
-#define V2 0x00000007
-
-		__raw_writel(V1, CM_FCLKEN1_CORE);
-		__raw_writel(V2, CM_FCLKEN2_CORE);
-		__raw_writel(V1, CM_ICLKEN1_CORE);
-		__raw_writel(V1, CM_ICLKEN2_CORE);
-	}
-#endif
-}
-
-/****************************************
- * Routine: muxSetupUsb0   (ostboot)
- * Description: Setup usb muxing
- *****************************************/
-void muxSetupUsb0(void)
-{
-	volatile uint8   *MuxConfigReg;
-	volatile uint32  *otgCtrlReg;
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	/* setup for USB VBus detection */
-	otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
-	*otgCtrlReg |= 0x00040000; /* bit 18 */
-}
-
-/****************************************
- * Routine: muxSetupUart3   (ostboot)
- * Description: Setup uart3 muxing
- *****************************************/
-void muxSetupUart3(void)
-{
-	volatile uint8 *MuxConfigReg;
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
-	*MuxConfigReg &= (uint8)(~0x1F);
-}
-
-/****************************************
- * Routine: muxSetupI2C1   (ostboot)
- * Description: Setup i2c muxing
- *****************************************/
-void muxSetupI2C1(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* I2C1 Clock pin configuration, PIN = M19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* I2C1 Data pin configuration, PIN = L15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* Pull-up required on data line */
-	/* external pull-up already present. */
-	/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
-}
-
-/****************************************
- * Routine: muxSetupUART1  (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-void muxSetupUART1(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* UART1_CTS pin configuration, PIN = D21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RTS pin configuration, PIN = H21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_TX pin configuration, PIN = L20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RX pin configuration, PIN = T21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupLCD   (ostboot)
- * Description: Setup lcd muxing
- *****************************************/
-void muxSetupLCD(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* LCD_D0 pin configuration, PIN = Y7  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D1 pin configuration, PIN = P10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D2 pin configuration, PIN = V8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D3 pin configuration, PIN = Y8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D4 pin configuration, PIN = W8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D5 pin configuration, PIN = R10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D6 pin configuration, PIN = Y9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D7 pin configuration, PIN = V9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D8 pin configuration, PIN = W9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D9 pin configuration, PIN = P11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D10 pin configuration, PIN = V10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D11 pin configuration, PIN = Y10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D12 pin configuration, PIN = W10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D13 pin configuration, PIN = R11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D14 pin configuration, PIN = V11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D15 pin configuration, PIN = W11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D16 pin configuration, PIN = P12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D17 pin configuration, PIN = R12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_PCLK pin configuration,   PIN = W6   */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_VSYNC pin configuration,  PIN = V7  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_HSYNC pin configuration,  PIN = Y6  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_ACBIAS pin configuration, PIN = W7 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupCamera  (ostboot)
- * Description: Setup camera muxing
- *****************************************/
-void muxSetupCamera(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
-	/* CAM_RST is connected through the I2C IO expander.*/
-	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
-	/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
-
-	/* CAMERA_XCLK  pin configuration, PIN = U3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_LCLK  pin configuration, PIN = V5 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_VSYNC pin configuration, PIN = U2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_HSYNC pin configuration, PIN = T3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT0 pin configuration, PIN = T4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT1 pin configuration, PIN = V2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT2 pin configuration, PIN = V3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT3 pin configuration, PIN = U4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT4 pin configuration, PIN = W2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT5 pin configuration, PIN = V4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT6 pin configuration, PIN = W3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT9 pin configuration, PIN = V6 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupMMCSD (ostboot)
- * Description: set up MMC muxing
- *****************************************/
-void muxSetupMMCSD(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* SDMMC_CLKI pin configuration,  PIN = H15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CLKO pin configuration,  PIN = G19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CMD pin configuration,   PIN = H18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CDIR pin configuration,  PIN = G18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
-	/* MMC_CD for 2422IP=K1 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-
-	/* MMC_WP pin configuration,      PIN = B4  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/******************************************
- * Routine: muxSetupTouchScreen (ostboot)
- * Description:  Set up touch screen muxing
- *******************************************/
-void muxSetupTouchScreen(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* SPI1_CLK pin configuration,  PIN = U18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MOSI pin configuration, PIN = V20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MISO pin configuration, PIN = T18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_nCS0 pin configuration, PIN = U19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* PEN_IRQ pin configuration,   PIN = P20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupHDQ (ostboot)
- * Description: setup 1wire mux
- *****************************************/
-void muxSetupHDQ(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* HDQ_SIO pin configuration,  PIN = N18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/***************************************************************
- * Routine: muxSetupGPMC (ostboot)
- * Description: Configures balls which cam up in protected mode
- ***************************************************************/
-void muxSetupGPMC(void)
-{
-	volatile uint8 *MuxConfigReg;
-	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
-
-	/* gpmc_io_dir */
-	*MCR = 0x19000000;
-
-	/* NOR FLASH CS0 */
-	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
-				   *MuxConfigReg = 0x01 ;
-
-	/* MPDB(Multi Port Debug Port) CS1 */
-	/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
-				   *MuxConfigReg = 0x00 ;
-}
-
-/****************************************************************
- * Routine: muxSetupSDRC  (ostboot)
- * Description: Configures balls which come up in protected mode
- ****************************************************************/
-void muxSetupSDRC(void)
-{
-	volatile uint8 *MuxConfigReg;
-
-	/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
-				   *MuxConfigReg = 0x00;
-
-	if (get_cpu_type() == CPU_2422) {
-		MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
-					   *MuxConfigReg = 0x1b;
-	}
-}
-
-/*****************************************************************************
- * Routine: update_mux()
- * Description: Update balls which are different beween boards.  All should be
- *              updated to match functionaly.  However, I'm only updating ones
- *              which I'll be using for now.  When power comes into play they
- *              all need updating.
- *****************************************************************************/
-void update_mux(u32 btype,u32 mtype)
-{
-	u32 cpu, base = OMAP2420_CTRL_BASE;
-	cpu = get_cpu_type();
-
-	if (btype == BOARD_H4_MENELAUS) {
-		if (cpu == CPU_2420) {
-			/* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
-			__raw_writeb(0x3, base+0x30);
-			/* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
-			__raw_writeb(0x3, base+0xa3);
-			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
-			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
-			/* PIN = M1 (HSUSBOTG) */
-			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
-			__raw_writeb(0x3, base+0x9d);
-			/* PIN = U32, (WLAN_CLKREQ) */
-			/* PIN = Y11, WLAN */
-			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
-			__raw_writeb(0x3, base+0xe7);
-			/* PIN = AA8, mDOC */
-			/* PIN = AA10, BT */
-			/* PIN = AA13, WLAN */
-			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 HHUSB */
-			/* PIN = H19 HSUSB */
-			/* PIN = W13, P13, R13, W16 ... */
-			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
-			__raw_writeb(0x3, base+0xde);
-			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
-			__raw_writeb(0x0, base+0x12c);
-			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
-			__raw_writeb(0x0, base+0x136);
-		} else if (cpu == CPU_2422) {
-			/* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
-			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
-			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
-			__raw_writeb(0x0, base+0x92);
-			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
-			/* PIN = M1 (HSUSBOTG) */
-			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
-			__raw_writeb(0x3, base+0x10c);
-			/* PIN = U32, (WLAN_CLKREQ) */
-			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
-			__raw_writeb(0x3, base+0x30);
-			/* PIN = AA8, mDOC */
-			/* PIN = AA10, BT */
-			/* PIN = AA12, WLAN */
-			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 HHUSB */
-			/* PIN = H19 HSUSB */
-			/* PIN = W13, P13, R13, W16 ... */
-			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
-			__raw_writeb(0x3, base+0xde);
-			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
-			__raw_writeb(0x0, base+0x12c);
-			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
-			__raw_writeb(0x0, base+0x136);
-		}
-
-	} else if (btype == BOARD_H4_SDP) {
-		if (cpu == CPU_2420) {
-			/* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
-			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
-			/* Pin = Y11 VLNQ */
-			/* Pin = AA4 VLNQ */
-			/* Pin = AA6 VLNQ */
-			/* Pin = AA8 VLNQ */
-			/* Pin = AA10 VLNQ */
-			/* Pin = AA12 VLNQ */
-			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 MDOC_nDMAREQ */
-			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
-			__raw_writeb(0x3, base+0x114);
-			/* PIN = W13, V12, P13, R13, W19, W16 ... */
-			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
-		} else if (cpu == CPU_2422) {
-			/* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
-			/* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
-			/* Pin = Y11 VLNQ */
-			/* Pin = AA4 VLNQ */
-			/* Pin = AA6 VLNQ */
-			/* Pin = AA8 VLNQ */
-			/* Pin = AA10 VLNQ */
-			/* Pin = AA12 VLNQ */
-			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 MDOC_nDMAREQ */
-			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
-			__raw_writeb(0x3, base+0x114);
-			/* PIN = W13, V12, P13, R13, W19, W16 ... */
-			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
-		}
-	}
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c
deleted file mode 100644
index b12011e04a..0000000000
--- a/board/ti/omap2420h4/sys_info.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h>  /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <i2c.h>
-
-/**************************************************************************
- * get_prod_id() - get id info from chips
- ***************************************************************************/
-static u32 get_prod_id(void)
-{
-	u32 p;
-	p = __raw_readl(PRODUCTION_ID); /* get production ID */
-	return((p & CPU_242X_PID_MASK) >> 16);
-}
-
-/**************************************************************************
- * get_cpu_type() - low level get cpu type
- * - no C globals yet.
- * - just looking to say if this is a 2422 or 2420 or ...
- * - to start with we will look at switch settings..
- * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
- *   (mux for 2420, non-mux for 2422).
- ***************************************************************************/
-u32 get_cpu_type(void)
-{
-	u32 v;
-
-	switch(get_prod_id()){
-		case 1:;/* 2420 */
-		case 2: return(CPU_2420); break; /* 2420 pop */
-		case 4: return(CPU_2422); break;
-		case 8: return(CPU_2423); break;
-		default: break;  /* early 2420/2422's unmarked */
-	}
-
-	v = __raw_readl(TAP_IDCODE_REG);
-	v &= CPU_24XX_ID_MASK;
-	if (v == CPU_2420_CHIPID) {	  /* currently 2420 and 2422 have same id */
-		if (is_gpmc_muxed() == GPMC_MUXED)	  /* if mux'ed */
-			return(CPU_2420);
-		else
-			return(CPU_2422);
-	} else
-		return(CPU_2420); /* don't know, say 2420 */
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
-	u32 v;
-	v = __raw_readl(TAP_IDCODE_REG);
-	v = v >> 28;
-	return(v+1);  /* currently 2422 and 2420 match up */
-}
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
-	if(*burst == H4_2420_SDRC_MR_0_SDR)
-		return(1);
-	return(0);
-}
-
-/***********************************************************
- * get_mem_type() - identify type of mDDR part used.
- * 2422 uses stacked DDR, 2 parts CS0/CS1.
- * 2420 may have 1 or 2, no good way to know...only init 1...
- * when eeprom data is up we can select 1 more.
- *************************************************************/
-u32 get_mem_type(void)
-{
-	u32 cpu, sdr = is_mem_sdr();
-
-	cpu = get_cpu_type();
-	if (cpu == CPU_2422 || cpu == CPU_2423)
-		return(DDR_STACKED);
-
-	if(get_prod_id() == 0x2)
-		return(XDR_POP);
-
-	if (get_board_type() == BOARD_H4_MENELAUS)
-		if(sdr)
-			return(SDR_DISCRETE);
-		else
-			return(DDR_COMBO);
-	else
-		if(sdr) /* SDP + SDR kit */
-			return(SDR_DISCRETE);
-		else
-			return(DDR_DISCRETE); /* origional SDP */
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
-{
-	u32 size;
-	size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
-	size &= 0x2FF;   /* remove unwanted bits */
-	size *= SZ_2M;   /* find size in MB */
-	return(size);
-}
-
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
- *      when they are available we can get info from there.  This should
- *      be correct of all known boards up until today.
- ************************************************************************/
-u32 get_board_type(void)
-{
-	if (i2c_probe(I2C_MENELAUS) == 0)
-		return(BOARD_H4_MENELAUS);
-	else
-		return(BOARD_H4_SDP);
-}
-
-/******************************************************************
- * get_sysboot_value() - get init word settings (dip switch on h4)
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
-	return(0x00000FFF & __raw_readl(CONTROL_STATUS));
-}
-
-/***************************************************************************
- *  get_gpmc0_base() - Return current address hardware will be
- *     fetching from. The below effectively gives what is correct, its a bit
- *   mis-leading compared to the TRM.  For the most general case the mask
- *   needs to be also taken into account this does work in practice.
- *   - for u-boot we currently map:
- *       -- 0 to nothing,
- *       -- 4 to flash
- *       -- 8 to enent
- *       -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
-	u32 b;
-
-	b = __raw_readl(GPMC_CONFIG7_0);
-	b &= 0x1F;	 /* keep base [5:0] */
-	b = b << 24; /* ret 0x0b000000 */
-	return(b);
-}
-
-/*****************************************************************
- *  is_gpmc_muxed() - tells if address/data lines are multiplexed
- *****************************************************************/
-u32 is_gpmc_muxed(void)
-{
-	u32 mux;
-	mux = get_sysboot_value();
-	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
-		return(GPMC_MUXED); /* NAND Boot mode */
-	if (mux & BIT1)	   /* if mux'ed */
-		return(GPMC_MUXED);
-	else
-		return(GPMC_NONMUXED);
-}
-
-/************************************************************************
- *  get_gpmc0_type() - read sysboot lines to see type of memory attached
- ************************************************************************/
-u32 get_gpmc0_type(void)
-{
-	u32 type;
-	type = get_sysboot_value();
-	if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
-		return(TYPE_NAND);
-	else
-		return(TYPE_NOR);
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
-	u32 width;
-	width = get_sysboot_value();
-	if ((width & 0xF) == (BIT3|BIT2))
-		return(WIDTH_8BIT);
-	else
-		return(WIDTH_16BIT);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- *   volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
-	u32 i = 0, val;
-	do {
-		++i;
-		val = __raw_readl(read_addr) & read_bit_mask;
-		if (val == match_value)
-			return(1);
-		if (i==bound)
-			return(0);
-	} while (1);
-}
-
-/*********************************************************************
- *  display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
-	static const char cpu_2420 [] = "2420";   /* cpu type */
-	static const char cpu_2422 [] = "2422";
-	static const char cpu_2423 [] = "2423";
-	static const char db_men [] = "Menelaus"; /* board type */
-	static const char db_ip [] = "IP";
-	static const char mem_sdr [] = "mSDR";    /* memory type */
-	static const char mem_ddr [] = "mDDR";
-	static const char t_tst [] = "TST";	    /* security level */
-	static const char t_emu [] = "EMU";
-	static const char t_hs [] = "HS";
-	static const char t_gp [] = "GP";
-	static const char unk [] = "?";
-
-	const char *cpu_s, *db_s, *mem_s, *sec_s;
-	u32 cpu, rev, sec;
-
-	rev = get_cpu_rev();
-	cpu = get_cpu_type();
-	sec = get_device_type();
-
-	if(is_mem_sdr())
-		mem_s = mem_sdr;
-	else
-		mem_s = mem_ddr;
-
-	if(cpu == CPU_2423)
-		cpu_s = cpu_2423;
-	else if (cpu == CPU_2422)
-		cpu_s = cpu_2422;
-	else
-		cpu_s = cpu_2420;
-
-	if(btype ==  BOARD_H4_MENELAUS)
-		db_s = db_men;
-	else
-		db_s = db_ip;
-
-	switch(sec){
-		case TST_DEVICE: sec_s = t_tst; break;
-		case EMU_DEVICE: sec_s = t_emu; break;
-		case HS_DEVICE:  sec_s = t_hs; break;
-		case GP_DEVICE:  sec_s = t_gp; break;
-		default: sec_s = unk;
-	}
-
-	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
-	printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- *          0 = 242x IP platform (first 2xx boards)
- *          1 = 242x Menelaus platfrom.
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	u32 rev = 0;
-	u32 btype = get_board_type();
-
-	if (btype == BOARD_H4_MENELAUS){
-		rev = 1;
-	}
-	return(rev);
-}
-
-/********************************************************
- *  get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
-	u32  val;
-	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
-	val &= 0xF0000000;
-	val >>= 28;
-	return(val);
-}
-
-/********************************************************
- *  get_base2(); get 2upper addr of current execution
- *******************************************************/
-u32 get_base2(void)
-{
-	u32  val;
-	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
-	val &= 0xFF000000;
-	val >>= 24;
-	return(val);
-}
-
-/********************************************************
- *  running_in_flash() - tell if currently running in
- *   flash.
- *******************************************************/
-u32 running_in_flash(void)
-{
-	if (get_base() < 4)
-		return(1);  /* in flash */
-	return(0); /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- *  running_in_sram() - tell if currently running in
- *   sram.
- *******************************************************/
-u32 running_in_sram(void)
-{
-	if (get_base() == 4)
-		return(1);  /* in SRAM */
-	return(0); /* running in FLASH or SDRAM */
-}
-/********************************************************
- *  running_in_sdram() - tell if currently running in
- *   flash.
- *******************************************************/
-u32 running_in_sdram(void)
-{
-	if (get_base() > 4)
-		return(1);  /* in sdram */
-	return(0); /* running in SRAM or FLASH */
-}
-
-/*************************************************************
- *  running_from_internal_boot() - am I a signed NOR image.
- *************************************************************/
-u32 running_from_internal_boot(void)
-{
-	u32 v, base;
-
-	v = get_sysboot_value() & BIT3;
-	base = get_base2();
-	/* if running at mask rom flash address and
-	 * sysboot3 says this was an internal boot
-	 */
-	if ((base == 0x08) && v)
-		return(1);
-	else
-		return(0);
-}
-
-/*************************************************************
- *  get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
-	int mode;
-	mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
-	return(mode >>= 8);
-}
diff --git a/boards.cfg b/boards.cfg
index 8876d88967..448ba66629 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -52,7 +52,6 @@ flea3                        arm         arm1136     -                   CarMedi
 mx35pdk                      arm         arm1136     -                   freescale      mx35
 woodburn                     arm         arm1136     -                   -              mx35
 woodburn_sd                  arm         arm1136     woodburn            -              mx35        woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
-omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
 rpi_b                        arm         arm1176     rpi_b               raspberrypi    bcm2835
 integratorap_cm720t          arm         arm720t     integrator          armltd         -           integratorap:CM720T
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 9223f6e436..a0f1fa30f8 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -96,3 +96,4 @@ R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. L
 CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 PCIPPC2          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 PCIPPC6	powerpc	MPC740/MPC750 -	  -		Wolfgang Denk <wd@denx.de>
+omap2420h4       arm         omap24xx       -           2013-06-04  Richard Woodruff <r-woodruff2@ti.com>
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 7f013ab33c..d77c25fa9b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -74,13 +74,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
 	defined(CONFIG_TI814X)
 
-#if defined(CONFIG_APTIX)
-	/* /13 mode so Aptix 6MHz can hit 115200 */
-	serial_out(3, &com_port->mdr1);
-#else
 	/* /16 is proper to hit 115200 with 48MHz */
 	serial_out(0, &com_port->mdr1);
-#endif
 #endif /* CONFIG_OMAP */
 }
 
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index b92eef4db9..3c07da3597 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -151,12 +151,7 @@ static int calc_divisor (NS16550_t port)
 	}
 #endif
 
-#ifdef CONFIG_APTIX
-#define MODE_X_DIV 13
-#else
 #define MODE_X_DIV 16
-#endif
-
 	/* Compute divisor value. Normally, we should simply return:
 	 *   CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
 	 * but we need to round that value by adding 0.5.
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
deleted file mode 100644
index 04e8d3ad51..0000000000
--- a/include/configs/omap2420h4.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the 242x TI H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
-#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
-/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
-/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
-
-#define CONFIG_STANDALONE_LOAD_ADDR	0x80300000
-
-/* Clock config to target*/
-#define PRCM_CONFIG_II	1
-/* #define PRCM_CONFIG_III		1 */
-
-#include <asm/arch/omap2420.h>        /* get chip and board defs */
-
-/* On H4, NOR and NAND flash are mutual exclusive.
-   Define this if you want to use NAND
- */
-/*#define CONFIG_SYS_NAND_BOOT */
-
-#ifdef CONFIG_APTIX
-#define V_SCLK                   1500000
-#else
-#define V_SCLK                   12000000
-#endif
-
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ      V_SCLK
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG        1
-#define CONFIG_REVISION_TAG      1
-#define CONFIG_OF_LIBFDT
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
-#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
-
-/*
- * Hardware drivers
- */
-
-/*
- * SMC91c96 Etherent
- */
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#ifdef CONFIG_APTIX
-#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
-#else
-#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
-#endif
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
-#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
-#define CONFIG_SYS_NS16550_COM1         OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on H4 */
-
-  /*
-   * I2C configuration
-   */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED          100000
-#define CONFIG_SYS_I2C_SLAVE          1
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX        1
-#define CONFIG_BAUDRATE          115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#ifdef CONFIG_SYS_NAND_BOOT
-    #define CONFIG_CMD_DHCP
-    #define CONFIG_CMD_I2C
-    #define CONFIG_CMD_NAND
-    #define CONFIG_CMD_JFFS2
-#else
-    #define CONFIG_CMD_DHCP
-    #define CONFIG_CMD_I2C
-    #define CONFIG_CMD_JFFS2
-
-    #undef CONFIG_CMD_SOURCE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTDELAY         3
-
-#ifdef NFS_BOOT_DEFAULTS
-#define CONFIG_BOOTARGS	         "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
-#else
-#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-#endif
-
-#define CONFIG_NETMASK           255.255.254.0
-#define CONFIG_IPADDR            128.247.77.90
-#define CONFIG_SERVERIP          128.247.77.158
-#define CONFIG_BOOTFILE          "uImage"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP             /* undef to save memory */
-#ifdef CONFIG_APTIX
-# define CONFIG_SYS_PROMPT		"OMAP2420 Aptix # "
-#else
-# define CONFIG_SYS_PROMPT		"OMAP242x H4 # "
-#endif
-#define CONFIG_SYS_CBSIZE               256  /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS              16          /* max number of command args */
-#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
-
-#define CONFIG_SYS_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
-
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#ifdef CONFIG_APTIX
-#define V_PTV			3
-#else
-#define V_PTV			7	/* use with 12MHz/128 */
-#endif
-
-#define CONFIG_SYS_TIMERBASE		OMAP2420_GPT2
-#define CONFIG_SYS_PTV			V_PTV	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			1000
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
-#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
-
-#define PHYS_FLASH_SECT_SIZE     SZ_128K
-#define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE_1        SZ_32M
-#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
-#define PHYS_FLASH_SIZE_2        SZ_32M
-
-#define PHYS_SRAM		0x4020F800
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_BANKS      2           /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
-
-#ifdef CONFIG_SYS_NAND_BOOT
-#define CONFIG_ENV_IS_IN_NAND	1
-#define CONFIG_ENV_OFFSET	0x80000	/* environment starts here  */
-#else
-#define CONFIG_ENV_ADDR             (CONFIG_SYS_FLASH_BASE + SZ_256K)
-#define	CONFIG_ENV_IS_IN_FLASH      1
-#define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
-#define CONFIG_ENV_OFFSET	( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
-#endif
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/mtd/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_SYS_JFFS2_MEM_NAND
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=omap2420-1"
-#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
-*/
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM
-
-#endif							/* __CONFIG_H */