Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net into nextWIP/29Sep2021-next

- Fix some non-NULL terminated strings in the networking subsystem
- net: tsec: Mark tsec_get_interface as __maybe_unused

86 files changed, 277 insertions, 255 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d0103fc881..1a359d060e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_RGMII
 	/* some dpmacs in armv8a based freescale layerscape SOCs can be
-	 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+	 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
 	 * EC*_PMUX(rgmii) bits in RCW.
 	 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
 	 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f33d05d053..f2efd4cc1d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
    - Hardware buffer management for buffer allocation and de-allocation (BMan)
    - Cryptography acceleration (SEC)
  - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x 10GBase-R supporting 10G interface
    - Up to 1 x QSGMII
    - Up to 4 x SGMII supporting 1000Mbps
    - Up to 2 x SGMII supporting 2500Mbps
@@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
    - Two PLLs per four-lane SerDes
    - Support for 10G operation
  - Ethernet interfaces by FMan
-   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+   - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
    - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
    - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
    - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
   Single WRIOP tile supporting 130Gbps using 18 MACs
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for XFI (and 10GBase-KR)
+  Support for 10GBase-R (and 10GBase-KR)
   Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.
@@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
   Ethernet interfaces
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for XFI (and 10GBase-KR)
+  Support for 10GBase-R (and 10GBase-KR)
   Support for CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 280afbbf98..26f8a49826 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 	/*
-	 * LS1044A/1048A  support only one XFI port
+	 * LS1044A/1048A  support only one 10GBase-R port
 	 * Disable MAC1 for LS1044A/1048A
 	 */
 	if (serdes == FSL_SRDS_1 && lane == 2) {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
index 23816da8ee..4063d9a114 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 1xxx
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
index c6558ae2e0..548ab2ba65 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 6xxx
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
@@ -14,6 +14,6 @@
 
 &enetc0 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
 };
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index 5a0f060c16..3991fb793f 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 7777
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
@@ -30,25 +30,25 @@
 
 &mscc_felix_port0 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
 };
 
 &mscc_felix_port1 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
 };
 
 &mscc_felix_port2 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
 };
 
 &mscc_felix_port3 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
 };
 
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index 39a83e10c4..d68c8c2be0 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 7xx7
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 &slot1 {
@@ -19,13 +19,13 @@
 
 &mscc_felix_port0 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
 };
 
 &mscc_felix_port3 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
 };
 
diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
index 7d4702e4ff..94b5081d61 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 8xxx
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index 021fe3fbc6..3b850268e6 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 9999
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index b6704d8089..eb632143e0 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 9999
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  *
  */
 
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 8c10897e56..ed86da6b26 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW x3xx
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 1d800dacef..c9de4ecc43 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW x5xx
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 1fb2cdf0c2..7f785507bf 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 7777
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 &slot2 {
@@ -19,7 +19,7 @@
 
 &mscc_felix_port1 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
 };
 
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 2333f74e5a..0fbe7721c8 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LS1028A-QDS device tree fragment for RCW 7777
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 &slot3 {
@@ -19,7 +19,7 @@
 
 &mscc_felix_port2 {
 	status = "okay";
-	phy-mode = "sgmii-2500";
+	phy-mode = "2500base-x";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
 };
 
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
index e0a6c04835..df39cca696 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
@@ -9,12 +9,12 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
index 65e95300ab..99f74c2fc4 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
@@ -9,10 +9,10 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
index ccbb5de1ea..72297f48ca 100644
--- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
+++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
@@ -9,40 +9,40 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac3 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac5 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac6 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac7 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac8 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 179ed19bf2..9e68c147e6 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -24,49 +24,49 @@
 &dpmac1 {
 	status = "okay";
 	phy-handle = <&mdio1_phy1>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
 	phy-handle = <&mdio1_phy2>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac3 {
 	status = "okay";
 	phy-handle = <&mdio1_phy3>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
 	status = "okay";
 	phy-handle = <&mdio1_phy4>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac5 {
 	status = "okay";
 	phy-handle = <&mdio2_phy1>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac6 {
 	status = "okay";
 	phy-handle = <&mdio2_phy2>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac7 {
 	status = "okay";
 	phy-handle = <&mdio2_phy3>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac8 {
 	status = "okay";
 	phy-handle = <&mdio2_phy4>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &emdio1 {
diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi
index 304afdabc5..d1b43aa002 100644
--- a/arch/arm/dts/fsl-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-sch-24801.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device tree fragment for RCW SCH-24801 card
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi
index 584f3fa68c..61245287b9 100644
--- a/arch/arm/dts/fsl-sch-28021.dtsi
+++ b/arch/arm/dts/fsl-sch-28021.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device tree fragment for RCW SCH-28021 card
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi
index ca437d1782..28b1bec18a 100644
--- a/arch/arm/dts/fsl-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-sch-30841.dtsi
@@ -2,14 +2,14 @@
 /*
  * Device tree fragment for RCW SCH-30841 card
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
  * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
  * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
  * together on a single lane or mapped 1:1 to serdes lanes.
- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
  * PHY addresses are 0x00 - 0x03.
  * On the card the first port is the bottom port (closest to PEX connector).
  */
diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi
index fa0f2cdb10..bff9e76570 100644
--- a/arch/arm/dts/fsl-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-sch-30842.dtsi
@@ -2,13 +2,13 @@
 /*
  * Device tree fragment for RCW SCH-30842 card
  *
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 /*
  * SCH-30842 is a single port add-on card used with various FSL QDS boards.
  * It integrates a AQR112 PHY, which supports several protocols - SGMII,
- * SGMII-2500, USXGMII, XFI.
+ * 2500base-x, USXGMII, 10GBase-R.
  * PHY address is 0x02.
  */
 phy@02 {
diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts
index f633074099..8e0f4eaf68 100644
--- a/arch/arm/dts/ls1021a-tsn.dts
+++ b/arch/arm/dts/ls1021a-tsn.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2018 NXP Semiconductors
+/* Copyright 2016-2018 NXP
  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  */
 
diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c
index 9aac5f0b09..e8e2d547c1 100644
--- a/board/Marvell/octeon_ebb7304/board.c
+++ b/board/Marvell/octeon_ebb7304/board.c
@@ -339,7 +339,7 @@ void __fixup_fdt(void)
 		case CVMX_QLM_MODE_XFI:
 		case CVMX_QLM_MODE_RGMII_XFI:
 		case CVMX_QLM_MODE_RGMII_XFI_1X1:
-			type_str = "xfi";
+			type_str = "10gbase-r";
 			break;
 		case CVMX_QLM_MODE_10G_KR:
 		case CVMX_QLM_MODE_RGMII_10G_KR:
@@ -393,7 +393,7 @@ void __fixup_fdt(void)
 				if (pmd_control.s.train_en)
 					type_str = "10G_KR";
 				else
-					type_str = "xfi";
+					type_str = "10gbase-r";
 				break;
 			case 4:
 				if (pmd_control.s.train_en)
@@ -618,7 +618,7 @@ static void board_configure_qlms(void)
 					speed[qlm] = 103125;
 			}
 			printf("QLM %d: XLAUI\n", qlm);
-		} else if (!strncmp(mode_str, "xfi", 3)) {
+		} else if (!strncmp(mode_str, "10gbase-r", 3)) {
 			bool rgmii = false;
 
 			speed[qlm] = 103125;
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
index 8189f41bec..27f69abf60 100644
--- a/board/freescale/ls1012aqds/eth.c
+++ b/board/freescale/ls1012aqds/eth.c
@@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev)
 		bus = miiphy_get_dev_by_name(mdio_name);
 		pfe_set_mdio(1, bus);
 		pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
-					 PHY_INTERFACE_MODE_SGMII_2500);
+					 PHY_INTERFACE_MODE_2500BASEX);
 
 		data8 = QIXIS_READ(brdcfg[12]);
 		data8 |= 0x20;
@@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev)
 		pfe_set_mdio(0, bus);
 		pfe_set_phy_address_mode(0,
 					 CONFIG_PFE_SGMII_2500_PHY1_ADDR,
-					 PHY_INTERFACE_MODE_SGMII_2500);
+					 PHY_INTERFACE_MODE_2500BASEX);
 	}
 		break;
 
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 33a0910a19..6e21040601 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
 						ETH_1_2_5G_MDIO_MUX);
 				prop_val.phy_mask = cpu_to_fdt32(
 						ETH_2_5G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "sgmii-2500";
+				prop_val.phy_mode = "2500base-x";
 				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 						   ETH_1_MDIO);
 			} else {
@@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
 						ETH_2_2_5G_MDIO_MUX);
 				prop_val.phy_mask = cpu_to_fdt32(
 						ETH_2_5G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "sgmii-2500";
+				prop_val.phy_mode = "2500base-x";
 				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 						   ETH_2_MDIO);
 			}
diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
index 05ccb71aa0..5ab283ce8d 100644
--- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h
+++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -17,7 +17,7 @@
 #define ETH_1_2_5G_PHY_ID	0x1
 #define ETH_1_2_5G_MDIO_MUX	0x2
 #define ETH_2_5G_MDIO_PHY_MASK	0xFFFFFFF9
-#define ETH_2_5G_PHY_MODE	"sgmii-2500"
+#define ETH_2_5G_PHY_MODE	"2500base-x"
 #define ETH_2_2_5G_BUS_ID	0x1
 #define ETH_2_2_5G_PHY_ID	0x2
 #define ETH_2_2_5G_MDIO_MUX	0x3
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index bb3fbc71ef..565f800596 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev)
 			/* MAC1 */
 			pfe_set_phy_address_mode(priv->gemac_port,
 						 CONFIG_PFE_EMAC1_PHY_ADDR,
-						 PHY_INTERFACE_MODE_SGMII_2500);
+						 PHY_INTERFACE_MODE_2500BASEX);
 		} else {
 			/* MAC2 */
 			pfe_set_phy_address_mode(priv->gemac_port,
 						 CONFIG_PFE_EMAC2_PHY_ADDR,
-						 PHY_INTERFACE_MODE_SGMII_2500);
+						 PHY_INTERFACE_MODE_2500BASEX);
 		}
 		break;
 	default:
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index c1acd3040c..f31e16c419 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP Semiconductors
+/* Copyright 2016-2019 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index 913537d451..f5aa51da87 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -18,7 +18,7 @@ SoC overview.
       - SGMII, SGMII 2.5
       - QSGMII
       - SATA 3.0
-      - XFI
+      - 10GBase-R
  - DDR Controller
      - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
  -IFC/Local Bus
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index c3efe8a0be..e156ba0104 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 					   "sgmii-riser-s4-p1");
 		}
 	} else if (fm_info_get_enet_if(port) ==
-		   PHY_INTERFACE_MODE_SGMII_2500) {
+		   PHY_INTERFACE_MODE_2500BASEX) {
 		/* 2.5G SGMII interface */
 		f_link.phy_id = cpu_to_fdt32(port);
 		f_link.duplex = cpu_to_fdt32(1);
@@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 		fdt_delprop(fdt, offset, "phy-handle");
 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "sgmii-2500");
+				   "2500base-x");
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
 		switch (mdio_mux[port]) {
 		case EMI1_SLOT1:
@@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				   "qsgmii");
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
 		   port == FM1_10GEC1) {
-		/* XFI interface */
+		/* 10GBase-R interface */
 		f_link.phy_id = cpu_to_fdt32(port);
 		f_link.duplex = cpu_to_fdt32(1);
 		f_link.link_speed = cpu_to_fdt32(10000);
 		f_link.pause = 0;
 		f_link.asym_pause = 0;
-		/* no PHY for XFI */
+		/* no PHY for 10GBase-R */
 		fdt_delprop(fdt, offset, "phy-handle");
 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
@@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis)
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_SGMII_2500:
+		case PHY_INTERFACE_MODE_2500BASEX:
 		case PHY_INTERFACE_MODE_QSGMII:
 			if (interface == PHY_INTERFACE_MODE_SGMII) {
 				lane = serdes_get_first_lane(FSL_SRDS_1,
 						SGMII_FM1_DTSEC1 + idx);
-			} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+			} else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
 				lane = serdes_get_first_lane(FSL_SRDS_1,
 						SGMII_2500_FM1_DTSEC1 + idx);
 			} else {
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 709ddbbef3..66ee578e99 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -17,7 +17,7 @@ SoC overview.
       - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
         standard PCIe card
       - QSGMII with x4 RJ45 connector
-      - XFI with x1 RJ45 connector
+      - 10GBase-R with x1 RJ45 connector
  - DDR Controller
      - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
  -IFC/Local Bus
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index 1f01c15516..fa59116ce5 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis)
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
 		fm_info_set_mdio(i, dev);
 
-	/* XFI on lane A, MAC 9 */
+	/* 10GBase-R on lane A, MAC 9 */
 	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 	fm_info_set_mdio(FM1_10GEC1, dev);
diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README
index b8fa32652b..d6469019bd 100644
--- a/board/freescale/ls1046aqds/README
+++ b/board/freescale/ls1046aqds/README
@@ -18,7 +18,7 @@ SoC overview.
       - SGMII, SGMII 2.5
       - QSGMII
       - SATA 3.0
-      - XFI
+      - 10GBase-R
  - DDR Controller
      - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
  -IFC/Local Bus
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 33db552adb..8233f5461e 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 		default:
 			break;
 		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
 		/* 2.5G SGMII interface */
 		f_link.phy_id = cpu_to_fdt32(port);
 		f_link.duplex = cpu_to_fdt32(1);
@@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 		fdt_delprop(fdt, offset, "phy-handle");
 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "sgmii-2500");
+				   "2500base-x");
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
 		switch (port) {
 		case FM1_DTSEC1:
@@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			/* Backplane KR mode: skip fixups */
 			printf("Interface %d in backplane KR mode\n", port);
 		} else {
-			/* XFI interface */
+			/* 10GBase-R interface */
 			f_link.phy_id = cpu_to_fdt32(port);
 			f_link.duplex = cpu_to_fdt32(1);
 			f_link.link_speed = cpu_to_fdt32(10000);
 			f_link.pause = 0;
 			f_link.asym_pause = 0;
-			/* no PHY for XFI */
+			/* no PHY for 10GBase-R */
 			fdt_delprop(fdt, offset, "phy-handle");
 			fdt_setprop(fdt, offset, "fixed-link", &f_link,
 				    sizeof(f_link));
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
index a38c9d4830..1660f7c7cf 100644
--- a/board/freescale/ls1046ardb/README
+++ b/board/freescale/ls1046ardb/README
@@ -14,8 +14,8 @@ SoC overview.
  LS1046ARDB board Overview
  -----------------------
  - SERDES1 Connections, 4 lanes supporting:
-      - Lane0: XFI with x1 RJ45 connector
-      - Lane1: XFI Cage
+      - Lane0: 10GBase-R with x1 RJ45 connector
+      - Lane1: 10GBase-R Cage
       - Lane2: SGMII.5
       - Lane3: SGMII.6
  - SERDES2 Connections, 4 lanes supporting:
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index 4905302d8c..a3e147a48b 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis)
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
 		fm_info_set_mdio(i, dev);
 
-	/* XFI on lane A, MAC 9 */
+	/* 10GBase-R on lane A, MAC 9 */
 	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 	fm_info_set_mdio(FM1_10GEC1, dev);
 
diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README
index aa0fb6ac67..5315909def 100644
--- a/board/freescale/ls1088a/README
+++ b/board/freescale/ls1088a/README
@@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0
       - SATA 3.0
-      - XFI
+      - 10GBase-R
       - QSGMII
  - DDR Controller
      - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
@@ -106,7 +106,7 @@ SW12 1111 1111
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0
       - SATA 3.0
-      - 2 XFI
+      - 2 10GBase-R
       - QSGMII, SGMII with help for Riser card
       - 2 RGMII
       - 5 slot for Riser card or PCIe NIC
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index a8e9ef15dc..1ba5e94d0a 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis)
 	switch (srds_s1) {
 	case 0x1D:
 		/*
-		 * XFI does not need a PHY to work, but to avoid U-boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * 10GBase-R does not need a PHY to work, but to avoid U-boot
+		 * use default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to 10GBase-R
 		 * MAC error.
 		 */
 		wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 8e31e9e41e..04c1941b05 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -19,7 +19,7 @@ LS2088A SoC overview.
       - QSGMII
       - SATA 3.0
       - XAUI
-      - XFI
+      - 10GBase-R
  - DDR Controller
      - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
        chip-selects and two DIMM connectors. Support is up to 2133MT/s.
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 914cd0a9ab..7db3789822 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 	case 0x4B:
 	case 0x4C:
 		/*
-		 * XFI does not need a PHY to work, but to avoid U-Boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
-		 * MAC, and should not use a real XAUI PHY address, since
-		 * MDIO can access it successfully, and then MDIO thinks
-		 * the XAUI card is used for the XFI MAC, which will cause
-		 * error.
+		 * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+		 * use default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to 10GBase-R
+		 * MAC, and should not use a real XAUI PHY address, since MDIO
+		 * can access it successfully, and then MDIO thinks the XAUI
+		 * card is used for the 10GBase-R MAC, which will cause error.
 		 */
 		wriop_set_phy_address(i, 0, i + 4);
 		ls2080a_qds_enable_SFP_TX(SFP_TX);
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 205c45cb2a..75a633ccb4 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview.
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0
       - SATA 3.0
-      - XFI
+      - 10GBase-R
  - DDR Controller
      - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
        chip-selects and two DIMM connectors. Support is up to 2133MT/s.
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index dde3f8ca37..84deb9562a 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features:
   - One QSGMII interface
   - Four SGMII interface supporting 1000 Mbps
   - Three SGMII interfaces supporting up to 2500 Mbps
-  - 10GbE XFI or 10Base-KR interface
+  - 10GBase-R or 10Base-KR interface
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 56e6109288..4f04d2ee06 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis)
 		/* set the on-board RGMII2  PHY */
 		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
 
-		/* set 10G XFI with Aquantia AQR105 PHY */
+		/* set 10GBase-R with Aquantia AQR105 PHY */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		break;
 #endif
@@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis)
 #endif
 			fm_info_set_mdio(i, dev);
 			break;
-		case PHY_INTERFACE_MODE_SGMII_2500:
+		case PHY_INTERFACE_MODE_2500BASEX:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
@@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			      enum fm_port port, int offset)
 {
 #if defined(CONFIG_TARGET_T1024RDB)
-	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
 	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
 			(port == FM1_DTSEC3)) {
 		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
 		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "sgmii-2500");
+				   "2500base-x");
 		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
 	}
 #endif
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index d690857f2e..b52d9610e9 100755
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -55,14 +55,14 @@ Memory:
  - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
 Ethernet interfaces:
  - Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
+ - Four 10GBase-R on-board cages
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
 Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
 SerDes:
  - 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI
 IFC:
  - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
 eSPI:
@@ -85,14 +85,14 @@ System Logic:
  - QIXIS-II FPGA system controll
 Debug Features:
  - Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+10GBase-R:
+ - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
  a on-board SFP+ cages, which to house optical module (fiber cable) or
  direct attach cable(copper), the copper cable is used to emulate
  10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
+ So, for 10GBase-R usage, there are two scenarios, one will use fiber cable,
  another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
+ introduced to indicate a 10GBase-R port will use copper cable, and U-Boot
  will fixup the dtb accordingly.
  It's used as: fsl_10gkr_copper:<10g_mac_name>
  The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
@@ -100,10 +100,10 @@ XFI:
  "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
  will be used by default.
  for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
+ hwconfig, then both four 10GBase-R ports will use copper cable.
  set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
+ 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use
+ fiber cable.
 1000BASE-KX(1G-KX):
  - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
  runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 705387af3c..2d7fc8bdda 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 		switch (srds_s1) {
-		case 0x66: /* XFI interface */
+		case 0x66: /* 10GBase-R interface */
 		case 0x6b:
 		case 0x6c:
 		case 0x6d:
 		case 0x71:
 			/*
-			* if the 10G is XFI, check hwconfig to see what is the
-			* media type, there are two types, fiber or copper,
-			* fix the dtb accordingly.
-			*/
+			 * Check hwconfig to see what is the media type, there
+			 * are two types, fiber or copper, fix the dtb
+			 * accordingly.
+			 */
 			switch (port) {
 			case FM1_10GEC1:
 			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
@@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 					printf("Interface %d in backplane KR mode\n",
 					       port);
 				} else {
-					/* fixed-link for XFI fiber cable */
+					/* fixed-link for 10GBase-R fiber cable */
 					f_link.phy_id = port;
 					f_link.duplex = 1;
 					f_link.link_speed = 10000;
@@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis)
 	case 0x66:
 	case 0x67:
 		/*
-		 * XFI does not need a PHY to work, but to avoid U-Boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+		 * use default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to 10GBase-R
 		 * MAC, and should not use a real XAUI PHY address, since
 		 * MDIO can access it successfully, and then MDIO thinks
-		 * the XAUI card is used for the XFI MAC, which will cause
+		 * the XAUI card is used for the 10GBase-R MAC, which will cause
 		 * error.
 		 */
 		fm_info_set_phy_address(FM1_10GEC1, 4);
@@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis)
 			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 			    (srds_s1 == 0x71)) {
-				/* As XFI is in cage intead of a slot, so
+				/* As 10GBase-R is in cage intead of a slot, so
 				 * ensure doesn't disable the corresponding port
 				 */
 				break;
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 715de106d6..e54672a80b 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void)
 		break;
 	case 0x66:
 	case 0x67:
-		/* SD1(A:D) => XFI cage
+		/* SD1(A:D) => 10GBase-R cage
 		 * SD1(E:H) => SLOT1 PCIe4
 		 */
 		QIXIS_WRITE(brdcfg[12], 0xfe);
 		break;
 	case 0x6a:
 	case 0x6b:
-		/* SD1(A:D) => XFI cage
+		/* SD1(A:D) => 10GBase-R cage
 		 * SD1(E)   => SLOT1 PCIe4
 		 * SD1(F:H) => SLOT2 SGMII
 		 */
@@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void)
 		break;
 	case 0x6c:
 	case 0x6d:
-		/* SD1(A:B) => XFI cage
+		/* SD1(A:B) => 10GBase-R cage
 		 * SD1(C:D) => SLOT3 SGMII
 		 * SD1(E:H) => SLOT1 PCIe4
 		 */
 		QIXIS_WRITE(brdcfg[12], 0xda);
 		break;
 	case 0x6e:
-		/* SD1(A:B) => SFP Module, XFI
+		/* SD1(A:B) => SFP Module, 10GBase-R
 		 * SD1(C:D) => SLOT3 SGMII
 		 * SD1(E:F) => SLOT1 PCIe4 x2
 		 * SD1(G:H) => SLOT2 SGMII
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index ec47c96f2b..c4bfd3b466 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -54,7 +54,7 @@ Differences between T2080 and T2081
 T2080PCIe-RDB board Overview
 ----------------------------
  - SERDES Configuration
-     - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+     - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10)
      - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
      - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
      - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
@@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview
      - SerDes-2 Lane G-H: to SATA1 & SATA2
  - Ethernet
      - Two on-board 10M/100M/1G RGMII ethernet ports
-     - Two on-board 10Gbps XFI fiber ports
+     - Two on-board 10GBase-R fiber ports
      - Two on-board 10Gbps Base-T copper ports
  - DDR Memory
      - Supports 72bit 4GB DDR3-LP SODIMM
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index c815a3a4fa..34ffaa6aeb 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis)
 
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
-		/* SGMII && XFI */
+		/* SGMII && 10GBase-R */
 		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
 		fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
 		fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
index c23d150921..e09c0006b7 100644
--- a/board/gdsys/a38x/ihs_phys.c
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -110,9 +110,7 @@ int register_miiphy_bus(uint k, struct mii_dev **bus)
 
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name,
-		name,
-		MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
 	mdiodev->read = bb_miiphy_read;
 	mdiodev->write = bb_miiphy_write;
 
diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt
index cfc376bc97..648a1aee69 100644
--- a/doc/device-tree-bindings/net/ethernet.txt
+++ b/doc/device-tree-bindings/net/ethernet.txt
@@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt.
   * "2500base-x",
   * "rxaui"
   * "xaui"
-  * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+  * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol
+    used with various different mediums. Please refer to the IEEE standard for
+    a definition of this. Note: 10GBASE-R is just one protocol that can be used
+    with XFI and SFI. XFI and SFI permit multiple protocols over a single
+    SERDES lane, and also defines the electrical characteristics of the signals
+    with a host compliance board plugged into the host XFP/SFP connector.
+    Therefore, XFI and SFI are not PHY interface types in their own right.)
+  * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with
+    Clause 73 autonegotiation. Please refer to the IEEE standard for further
+    information. Note: due to legacy usage, some 10GBASE-R usage incorrectly
+    makes use of this definition).
 - phy-connection-type: the same as "phy-mode" property but described in the
   Devicetree Specification;
 - phy-handle: phandle, specifies a reference to a node representing a PHY
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
index 018891e173..5d4b90c6ba 100644
--- a/drivers/net/armada100_fec.c
+++ b/drivers/net/armada100_fec.c
@@ -717,7 +717,7 @@ int armada100_fec_register(unsigned long base_addr)
 	struct mii_dev *mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = smi_reg_read;
 	mdiodev->write = smi_reg_write;
 
diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c
index c862c14146..88dc3ab384 100644
--- a/drivers/net/bcm-sf2-eth.c
+++ b/drivers/net/bcm-sf2-eth.c
@@ -250,7 +250,7 @@ int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num)
 
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = eth->miiphy_read;
 	mdiodev->write = eth->miiphy_write;
 
diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c
index 4b62670e5d..235f2f22d9 100644
--- a/drivers/net/dsa_sandbox.c
+++ b/drivers/net/dsa_sandbox.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 #include <asm/eth.h>
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 934b881219..935cd9c99c 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -493,7 +493,7 @@ static int eepro100_initialize_mii(struct eepro100_priv *priv)
 	if (!mdiodev)
 		return -ENOMEM;
 
-	strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
 	mdiodev->read = eepro100_miiphy_read;
 	mdiodev->write = eepro100_miiphy_write;
 	mdiodev->priv = priv;
diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c
index 0218349b04..9f8df7de06 100644
--- a/drivers/net/ep93xx_eth.c
+++ b/drivers/net/ep93xx_eth.c
@@ -427,7 +427,7 @@ int ep93xx_miiphy_initialize(struct bd_info * const bd)
 	struct mii_dev *mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
 	mdiodev->read = ep93xx_miiphy_read;
 	mdiodev->write = ep93xx_miiphy_write;
 
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 5be0ad2ab3..6e3d008199 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 			env_get_f("hwconfig", buffer, sizeof(buffer));
 			buf = buffer;
 
-			/* check if XFI interface enable in hwconfig for 10g */
+			/* check if 10GBase-R interface enable in hwconfig for 10g */
 			if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
 						  "sfp_amc", "sfp", buf)) {
 				if ((port == FM1_10GEC1 ||
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 7c23ccc1f0..5e0d0bca9b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -50,7 +50,7 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 	u32 value;
 	struct mii_dev bus;
 	bool sgmii_2500 = (priv->enet_if ==
-			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+			PHY_INTERFACE_MODE_2500BASEX) ? true : false;
 	int i = 0, j;
 
 #ifndef CONFIG_DM_ETH
@@ -133,7 +133,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth)
 
 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
 	    fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
-	    fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+	    fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
 		dtsec_configure_serdes(fm_eth);
 }
 
@@ -432,7 +432,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 
 	/* For some reason we need to set SPEED_100 */
 	if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
-	     (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
+	     (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) ||
 	     (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
 	      mac->set_if_mode)
 		mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
@@ -829,7 +829,7 @@ static int init_phy(struct fm_eth *fm_eth)
 
 	if (fm_eth->type == FM_ETH_10G_E)
 		supported = PHY_10G_FEATURES;
-	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+	if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
 		supported |= SUPPORTED_2500baseX_Full;
 #endif
 
@@ -1090,7 +1090,7 @@ static int fm_eth_probe(struct udevice *dev)
 		if (fm_eth->num != 0)
 			break;
 	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_SGMII_2500:
+	case PHY_INTERFACE_MODE_2500BASEX:
 		fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
 		break;
 	default:
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index ba4da69423..e1abf8f6bb 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls1043.c
@@ -79,7 +79,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	case FM1_DTSEC2:
 		if ((port == FM1_DTSEC2) &&
 		    is_serdes_configured(SGMII_2500_FM1_DTSEC2))
-			return PHY_INTERFACE_MODE_SGMII_2500;
+			return PHY_INTERFACE_MODE_2500BASEX;
 	case FM1_DTSEC5:
 	case FM1_DTSEC6:
 	case FM1_DTSEC9:
@@ -87,7 +87,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 			return PHY_INTERFACE_MODE_SGMII;
 		else if ((port == FM1_DTSEC9) &&
 			 is_serdes_configured(SGMII_2500_FM1_DTSEC9))
-			return PHY_INTERFACE_MODE_SGMII_2500;
+			return PHY_INTERFACE_MODE_2500BASEX;
 		break;
 	default:
 		break;
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
index 49b540bd30..09df0aa537 100644
--- a/drivers/net/fm/ls1046.c
+++ b/drivers/net/fm/ls1046.c
@@ -99,7 +99,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	case FM1_DTSEC10:
 		if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
 					 port - FM1_DTSEC5))
-			return PHY_INTERFACE_MODE_SGMII_2500;
+			return PHY_INTERFACE_MODE_2500BASEX;
 		break;
 	default:
 		break;
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 36f50d2782..eeb67a39a7 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -93,12 +93,12 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
 		if_mode |= (IF_MODE_GMII | IF_MODE_RM);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_SGMII_2500:
+	case PHY_INTERFACE_MODE_2500BASEX:
 	case PHY_INTERFACE_MODE_QSGMII:
 		if_mode &= ~IF_MODE_MASK;
 		if_mode |= (IF_MODE_GMII);
 		break;
-	case PHY_INTERFACE_MODE_XFI:
+	case PHY_INTERFACE_MODE_10GBASER:
 	case PHY_INTERFACE_MODE_XGMII:
 		if_mode &= ~IF_MODE_MASK;
 		if_mode |= IF_MODE_XGMII;
@@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
 		break;
 	}
 	/* Enable automatic speed selection for Non-XGMII */
-	if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI)
+	if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER)
 		if_mode |= IF_MODE_EN_AUTO;
 
 	if (type == PHY_INTERFACE_MODE_RGMII ||
diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
index 6fc3b90337..696e74c9e6 100644
--- a/drivers/net/fm/t1024.c
+++ b/drivers/net/fm/t1024.c
@@ -63,7 +63,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 			return PHY_INTERFACE_MODE_SGMII;
 		else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
 			 + port - FM1_DTSEC1))
-			return PHY_INTERFACE_MODE_SGMII_2500;
+			return PHY_INTERFACE_MODE_2500BASEX;
 		break;
 	default:
 		break;
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 566cdc7e54..915c7c8025 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -144,7 +144,7 @@ static int enetc_init_sgmii(struct udevice *dev)
 	if (!enetc_has_imdio(dev))
 		return 0;
 
-	if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
+	if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX)
 		is2500 = true;
 
 	/*
@@ -226,9 +226,8 @@ static void enetc_setup_mac_iface(struct udevice *dev,
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		enetc_init_rgmii(dev, phydev);
 		break;
-	case PHY_INTERFACE_MODE_XGMII:
 	case PHY_INTERFACE_MODE_USXGMII:
-	case PHY_INTERFACE_MODE_XFI:
+	case PHY_INTERFACE_MODE_10GBASER:
 		/* set ifmode to (US)XGMII */
 		if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
 		if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
@@ -270,7 +269,7 @@ static void enetc_start_pcs(struct udevice *dev)
 		priv->imdio.read = enetc_mdio_read;
 		priv->imdio.write = enetc_mdio_write;
 		priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
-		strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+		strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
 		if (!miiphy_get_dev_by_name(priv->imdio.name))
 			mdio_register(&priv->imdio);
 	}
@@ -291,12 +290,11 @@ static void enetc_start_pcs(struct udevice *dev)
 
 	switch (priv->if_type) {
 	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_SGMII_2500:
+	case PHY_INTERFACE_MODE_2500BASEX:
 		enetc_init_sgmii(dev);
 		break;
-	case PHY_INTERFACE_MODE_XGMII:
 	case PHY_INTERFACE_MODE_USXGMII:
-	case PHY_INTERFACE_MODE_XFI:
+	case PHY_INTERFACE_MODE_10GBASER:
 		enetc_init_sxgmii(dev);
 		break;
 	};
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index c20aef4ab2..e103f79305 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -541,7 +541,7 @@ static int mcdmafec_probe(struct udevice *dev)
 	info->bus = mdio_alloc();
 	if (!info->bus)
 		return -ENOMEM;
-	strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
 	info->bus->read = mcffec_miiphy_read;
 	info->bus->write = mcffec_miiphy_write;
 
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index 265d813c4f..7e54d4642d 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers/net/ftmac110.c
@@ -476,7 +476,7 @@ int ftmac110_initialize(struct bd_info *bis)
 	struct mii_dev *mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = ftmac110_mdio_read;
 	mdiodev->write = ftmac110_mdio_write;
 
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index 3f281a515c..1a57343439 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -638,7 +638,7 @@ int lpc32xx_eth_initialize(struct bd_info *bis)
 	struct mii_dev *mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = mii_reg_read;
 	mdiodev->write = mii_reg_write;
 
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 57ea45e2dc..8151104acf 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -1245,7 +1245,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 	struct mii_dev *mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
 	mdiodev->read = macb_miiphy_read;
 	mdiodev->write = macb_miiphy_write;
 
@@ -1403,7 +1403,7 @@ static int macb_eth_probe(struct udevice *dev)
 	macb->bus = mdio_alloc();
 	if (!macb->bus)
 		return -ENOMEM;
-	strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
 	macb->bus->read = macb_miiphy_read;
 	macb->bus->write = macb_miiphy_write;
 
diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c
index 282c2599d3..4eb8260281 100644
--- a/drivers/net/mpc8xx_fec.c
+++ b/drivers/net/mpc8xx_fec.c
@@ -160,7 +160,7 @@ int fec_initialize(struct bd_info *bis)
 		struct mii_dev *mdiodev = mdio_alloc();
 		if (!mdiodev)
 			return -ENOMEM;
-		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+		strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 		mdiodev->read = fec8xx_miiphy_read;
 		mdiodev->write = fec8xx_miiphy_write;
 
diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c
index f20e84e0f1..551fc2c9f9 100644
--- a/drivers/net/mscc_eswitch/felix_switch.c
+++ b/drivers/net/mscc_eswitch/felix_switch.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * Felix (VSC9959) Ethernet switch driver
- * Copyright 2018-2021 NXP Semiconductors
+ * Copyright 2018-2021 NXP
  */
 
 /*
@@ -213,17 +213,16 @@ static void felix_start_pcs(struct udevice *dev, int port,
 	bool autoneg = true;
 
 	if (phy->phy_id == PHY_FIXED_ID ||
-	    phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
+	    phy->interface == PHY_INTERFACE_MODE_2500BASEX)
 		autoneg = false;
 
 	switch (phy->interface) {
 	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_SGMII_2500:
+	case PHY_INTERFACE_MODE_2500BASEX:
 	case PHY_INTERFACE_MODE_QSGMII:
 		felix_init_sgmii(imdio, port, autoneg);
 		break;
-	case PHY_INTERFACE_MODE_XGMII:
-	case PHY_INTERFACE_MODE_XFI:
+	case PHY_INTERFACE_MODE_10GBASER:
 	case PHY_INTERFACE_MODE_USXGMII:
 		if (felix_init_sxgmii(imdio, port))
 			dev_err(dev, "PCS reset timeout on port %d\n", port);
@@ -233,7 +232,7 @@ static void felix_start_pcs(struct udevice *dev, int port,
 	}
 }
 
-void felix_init(struct udevice *dev)
+static void felix_init(struct udevice *dev)
 {
 	struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
 	struct felix_priv *priv = dev_get_priv(dev);
@@ -258,7 +257,7 @@ void felix_init(struct udevice *dev)
 	priv->imdio.read = felix_mdio_read;
 	priv->imdio.write = felix_mdio_write;
 	priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
-	strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+	strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
 
 	/* set up CPU port */
 	out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
@@ -276,6 +275,7 @@ void felix_init(struct udevice *dev)
 static int felix_probe(struct udevice *dev)
 {
 	struct felix_priv *priv = dev_get_priv(dev);
+	int err;
 
 	if (ofnode_valid(dev_ofnode(dev)) &&
 	    !ofnode_is_available(dev_ofnode(dev))) {
@@ -300,11 +300,18 @@ static int felix_probe(struct udevice *dev)
 		struct mii_dev *mii_bus;
 
 		mii_bus = mdio_alloc();
+		if (!mii_bus)
+			return -ENOMEM;
+
 		mii_bus->read = felix_mdio_read;
 		mii_bus->write = felix_mdio_write;
 		mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
-		strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
-		mdio_register(mii_bus);
+		strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
+		err = mdio_register(mii_bus);
+		if (err) {
+			mdio_free(mii_bus);
+			return err;
+		}
 	}
 
 	dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
@@ -317,10 +324,23 @@ static int felix_probe(struct udevice *dev)
 	return 0;
 }
 
+static int felix_port_probe(struct udevice *dev, int port,
+			    struct phy_device *phy)
+{
+	int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
+	struct felix_priv *priv = dev_get_priv(dev);
+
+	phy->supported &= supported;
+	phy->advertising &= supported;
+
+	felix_start_pcs(dev, port, phy, &priv->imdio);
+
+	return phy_config(phy);
+}
+
 static int felix_port_enable(struct udevice *dev, int port,
 			     struct phy_device *phy)
 {
-	int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
 	struct felix_priv *priv = dev_get_priv(dev);
 	void *base = priv->regs_base;
 
@@ -339,15 +359,7 @@ static int felix_port_enable(struct udevice *dev, int port,
 		 FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
 		 FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
 
-	felix_start_pcs(dev, port, phy, &priv->imdio);
-
-	phy->supported &= supported;
-	phy->advertising &= supported;
-	phy_config(phy);
-
-	phy_startup(phy);
-
-	return 0;
+	return phy_startup(phy);
 }
 
 static void felix_port_disable(struct udevice *dev, int pidx,
@@ -392,6 +404,7 @@ static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length)
 }
 
 static const struct dsa_ops felix_dsa_ops = {
+	.port_probe	= felix_port_probe,
 	.port_enable	= felix_port_enable,
 	.port_disable	= felix_port_disable,
 	.xmit		= felix_xmit,
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index ce5b8eed64..954bf86121 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -883,7 +883,7 @@ int mvgbe_initialize(struct bd_info *bis)
 		struct mii_dev *mdiodev = mdio_alloc();
 		if (!mdiodev)
 			return -ENOMEM;
-		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+		strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 		mdiodev->read = smi_reg_read;
 		mdiodev->write = smi_reg_write;
 
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
index 3228b8df49..ae5b6fc280 100644
--- a/drivers/net/pfe_eth/pfe_mdio.c
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -161,7 +161,7 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv)
 	int value, sgmii_2500 = 0;
 	struct gemac_s *gem = priv->gem;
 
-	if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+	if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
 		sgmii_2500 = 1;
 
 
@@ -220,7 +220,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
 
 	/* Configure SGMII  PCS */
 	if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
-	    gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+	    gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
 		out_be32(&scfg->mdioselcr, 0x00000000);
 		pfe_configure_serdes(priv);
 	}
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index d3d35a75d0..83075f78c9 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -308,9 +308,9 @@ struct {
 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
 	[PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 					   AQUANTIA_VND1_GSTART_RATE_1G},
-	[PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
+	[PHY_INTERFACE_MODE_2500BASEX]  = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 					   AQUANTIA_VND1_GSTART_RATE_2_5G},
-	[PHY_INTERFACE_MODE_XFI] =        {0x100, AQUANTIA_VND1_GSYSCFG_10G,
+	[PHY_INTERFACE_MODE_10GBASER] =   {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 					   AQUANTIA_VND1_GSTART_RATE_10G},
 	[PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 					   AQUANTIA_VND1_GSTART_RATE_10G},
@@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev)
 			return ret;
 	}
 	/*
-	 * for backward compatibility convert XGMII into either XFI or USX based
-	 * on FW config
+	 * for backward compatibility convert XGMII into either 10GBase-R or
+	 * USXGMII based on FW config
 	 */
 	if (interface == PHY_INTERFACE_MODE_XGMII) {
-		debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
+		debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
 
 		reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 				    AQUANTIA_SYSTEM_INTERFACE_SR);
 		if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 			interface = PHY_INTERFACE_MODE_USXGMII;
 		else
-			interface = PHY_INTERFACE_MODE_XFI;
+			interface = PHY_INTERFACE_MODE_10GBASER;
 	}
 
 	/*
@@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev)
 	case PHY_INTERFACE_MODE_USXGMII:
 		usx_an = 1;
 		/* FALLTHROUGH */
-	case PHY_INTERFACE_MODE_XFI:
+	case PHY_INTERFACE_MODE_10GBASER:
 		/* 10GBASE-T mode */
 		phydev->advertising = SUPPORTED_10000baseT_Full;
 		phydev->supported = phydev->advertising;
@@ -515,14 +515,14 @@ int aquantia_config(struct phy_device *phydev)
 			      phydev->dev->name);
 		} else {
 			reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
-			debug("%s: system interface XFI\n",
+			debug("%s: system interface 10GBase-R\n",
 			      phydev->dev->name);
 		}
 
 		phy_write(phydev, MDIO_MMD_PHYXS,
 			  AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 		break;
-	case PHY_INTERFACE_MODE_SGMII_2500:
+	case PHY_INTERFACE_MODE_2500BASEX:
 		/* 2.5GBASE-T mode */
 		phydev->advertising = SUPPORTED_1000baseT_Full;
 		phydev->supported = phydev->advertising;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 69acb69460..c9fc20855b 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -463,7 +463,7 @@ static struct phy_driver genphy_driver = {
 	.shutdown	= genphy_shutdown,
 };
 
-int genphy_init(void)
+static int genphy_init(void)
 {
 	return phy_register(&genphy_driver);
 }
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 3143a5813a..4055f07b2f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -657,7 +657,7 @@ int sh_eth_initialize(struct bd_info *bd)
 	mdiodev = mdio_alloc();
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = bb_miiphy_read;
 	mdiodev->write = bb_miiphy_write;
 
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 8f420261fa..5d9a73f23d 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -425,7 +425,7 @@ static int smc911x_initialize_mii(struct smc911x_priv *priv)
 	if (!mdiodev)
 		return -ENOMEM;
 
-	strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
 	mdiodev->read = smc911x_miiphy_read;
 	mdiodev->write = smc911x_miiphy_write;
 
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index bfe1b84cd5..2dfadbd82d 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -816,7 +816,7 @@ static int davinci_emac_probe(struct udevice *dev)
 		struct mii_dev *mdiodev = mdio_alloc();
 		if (!mdiodev)
 			return -ENOMEM;
-		strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
+		strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
 		mdiodev->read = davinci_mii_phy_read;
 		mdiodev->write = davinci_mii_phy_write;
 
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ee820aae15..0ce9765671 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -638,7 +638,7 @@ static int tsec_init(struct udevice *dev)
 	return priv->phydev->link ? 0 : -1;
 }
 
-static phy_interface_t tsec_get_interface(struct tsec_private *priv)
+static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
 {
 	struct tsec __iomem *regs = priv->regs;
 	u32 ecntrl;
@@ -701,8 +701,6 @@ static int init_phy(struct tsec_private *priv)
 	/* Assign a Physical address to the TBI */
 	out_be32(&regs->tbipa, priv->tbiaddr);
 
-	priv->interface = tsec_get_interface(priv);
-
 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 		tsec_configure_serdes(priv);
 
@@ -886,12 +884,13 @@ int tsec_probe(struct udevice *dev)
 	priv->tbiaddr = tbiaddr;
 
 	phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
+	if (!phy_mode)
+		phy_mode = dev_read_prop(dev, "phy-mode", NULL);
 	if (phy_mode)
 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
-	if (pdata->phy_interface == -1) {
-		printf("Invalid PHY interface '%s'\n", phy_mode);
-		return -EINVAL;
-	}
+	if (pdata->phy_interface == -1)
+		pdata->phy_interface = tsec_get_interface(priv);
+
 	priv->interface = pdata->phy_interface;
 
 	/* Check for speed limit, default is 1000Mbps */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 5da971ddc0..c4bd5c4a14 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1407,7 +1407,7 @@ int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info)
 
 	if (!mdiodev)
 		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 	mdiodev->read = uec_miiphy_read;
 	mdiodev->write = uec_miiphy_write;
 
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index afac6ec91c..f70b6e94c0 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0
- * Copyright 2016-2019 NXP Semiconductors
+ * Copyright 2016-2019 NXP
  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  */
 
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 0f31a908c9..a339a49730 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
  */
 
 #ifndef __DSA_H__
@@ -57,7 +57,8 @@
 /**
  * struct dsa_ops - DSA operations
  *
- * @port_enable:  Initialize a switch port for I/O.
+ * @port_probe:   Initialize a switch port.
+ * @port_enable:  Enable I/O for a port.
  * @port_disable: Disable I/O for a port.
  * @xmit:         Insert the DSA tag for transmission.
  *                DSA drivers receive a copy of the packet with headroom and
@@ -69,6 +70,8 @@
  *                master including any additional headers.
  */
 struct dsa_ops {
+	int (*port_probe)(struct udevice *dev, int port,
+			  struct phy_device *phy);
 	int (*port_enable)(struct udevice *dev, int port,
 			   struct phy_device *phy);
 	void (*port_disable)(struct udevice *dev, int port,
diff --git a/include/phy.h b/include/phy.h
index 6b928636b6..b9d8dc3a61 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface)
 {
 	return interface == PHY_INTERFACE_MODE_XGMII ||
 	       interface == PHY_INTERFACE_MODE_USXGMII ||
-	       interface == PHY_INTERFACE_MODE_XFI;
+	       interface == PHY_INTERFACE_MODE_10GBASER;
 }
 
 #endif
diff --git a/include/phy_interface.h b/include/phy_interface.h
index ebb18ecd40..f075abe9c9 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -37,7 +37,7 @@ typedef enum {
 	PHY_INTERFACE_MODE_CAUI2,
 	PHY_INTERFACE_MODE_CAUI4,
 	PHY_INTERFACE_MODE_NCSI,
-	PHY_INTERFACE_MODE_XFI,
+	PHY_INTERFACE_MODE_10GBASER,
 	PHY_INTERFACE_MODE_USXGMII,
 	PHY_INTERFACE_MODE_NONE,	/* Must be last */
 
@@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = {
 	[PHY_INTERFACE_MODE_CAUI2]		= "caui2",
 	[PHY_INTERFACE_MODE_CAUI4]		= "caui4",
 	[PHY_INTERFACE_MODE_NCSI]		= "NC-SI",
-	[PHY_INTERFACE_MODE_XFI]		= "xfi",
+	[PHY_INTERFACE_MODE_10GBASER]		= "10gbase-r",
 	[PHY_INTERFACE_MODE_USXGMII]		= "usxgmii",
 	[PHY_INTERFACE_MODE_NONE]		= "",
 };
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 694664d81b..bf762cd2a8 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -100,7 +100,7 @@ static void dsa_port_stop(struct udevice *pdev)
 
 		port_pdata = dev_get_parent_plat(pdev);
 		ops->port_disable(dev, port_pdata->index, port_pdata->phy);
-		ops->port_disable(dev, priv->cpu_port, NULL);
+		ops->port_disable(dev, priv->cpu_port, priv->cpu_port_fixed_phy);
 	}
 
 	eth_get_ops(master)->stop(master);
@@ -199,9 +199,7 @@ static int dsa_port_free_pkt(struct udevice *pdev, uchar *packet, int length)
 static int dsa_port_of_to_pdata(struct udevice *pdev)
 {
 	struct dsa_port_pdata *port_pdata;
-	struct dsa_pdata *dsa_pdata;
 	struct eth_pdata *eth_pdata;
-	struct udevice *dev;
 	const char *label;
 	u32 index;
 	int err;
@@ -213,15 +211,12 @@ static int dsa_port_of_to_pdata(struct udevice *pdev)
 	if (err)
 		return err;
 
-	dev = dev_get_parent(pdev);
-	dsa_pdata = dev_get_uclass_plat(dev);
-
 	port_pdata = dev_get_parent_plat(pdev);
 	port_pdata->index = index;
 
 	label = ofnode_read_string(dev_ofnode(pdev), "label");
 	if (label)
-		strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
+		strlcpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
 
 	eth_pdata = dev_get_plat(pdev);
 	eth_pdata->priv_pdata = port_pdata;
@@ -240,18 +235,42 @@ static const struct eth_ops dsa_port_ops = {
 	.free_pkt	= dsa_port_free_pkt,
 };
 
-static int dsa_port_probe(struct udevice *pdev)
+/*
+ * Inherit port's hwaddr from the DSA master, unless the port already has a
+ * unique MAC address specified in the environment.
+ */
+static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master)
 {
-	struct udevice *dev = dev_get_parent(pdev);
 	struct eth_pdata *eth_pdata, *master_pdata;
 	unsigned char env_enetaddr[ARP_HLEN];
+
+	eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
+	if (!is_zero_ethaddr(env_enetaddr)) {
+		/* individual port mac addrs require master to be promisc */
+		struct eth_ops *eth_ops = eth_get_ops(master);
+
+		if (eth_ops->set_promisc)
+			eth_ops->set_promisc(master, 1);
+
+		return;
+	}
+
+	master_pdata = dev_get_plat(master);
+	eth_pdata = dev_get_plat(pdev);
+	memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
+	eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
+				      master_pdata->enetaddr);
+}
+
+static int dsa_port_probe(struct udevice *pdev)
+{
+	struct udevice *dev = dev_get_parent(pdev);
+	struct dsa_ops *ops = dsa_get_ops(dev);
 	struct dsa_port_pdata *port_pdata;
-	struct dsa_priv *dsa_priv;
 	struct udevice *master;
-	int ret;
+	int err;
 
 	port_pdata = dev_get_parent_plat(pdev);
-	dsa_priv = dev_get_uclass_priv(dev);
 
 	port_pdata->phy = dm_eth_phy_connect(pdev);
 	if (!port_pdata->phy)
@@ -268,42 +287,25 @@ static int dsa_port_probe(struct udevice *pdev)
 	 * TODO: we assume the master device is always there and doesn't get
 	 * removed during runtime.
 	 */
-	ret = device_probe(master);
-	if (ret)
-		return ret;
-
-	/*
-	 * Inherit port's hwaddr from the DSA master, unless the port already
-	 * has a unique MAC address specified in the environment.
-	 */
-	eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
-	if (!is_zero_ethaddr(env_enetaddr)) {
-		/* individual port mac addrs require master to be promisc */
-		struct eth_ops *eth_ops = eth_get_ops(master);
+	err = device_probe(master);
+	if (err)
+		return err;
 
-		if (eth_ops->set_promisc)
-			eth_ops->set_promisc(master, 1);
+	dsa_port_set_hwaddr(pdev, master);
 
-		return 0;
+	if (ops->port_probe) {
+		err = ops->port_probe(dev, port_pdata->index,
+				      port_pdata->phy);
+		if (err)
+			return err;
 	}
 
-	master_pdata = dev_get_plat(master);
-	eth_pdata = dev_get_plat(pdev);
-	memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
-	eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
-				      master_pdata->enetaddr);
-
 	return 0;
 }
 
 static int dsa_port_remove(struct udevice *pdev)
 {
-	struct udevice *dev = dev_get_parent(pdev);
-	struct dsa_port_pdata *port_pdata;
-	struct dsa_priv *dsa_priv;
-
-	port_pdata = dev_get_parent_plat(pdev);
-	dsa_priv = dev_get_uclass_priv(dev);
+	struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev);
 
 	port_pdata->phy = NULL;
 
@@ -419,7 +421,7 @@ static int dsa_post_bind(struct udevice *dev)
 			struct dsa_port_pdata *port_pdata;
 
 			port_pdata = dev_get_parent_plat(pdev);
-			strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
+			strlcpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
 			pdev->name = port_pdata->name;
 		}
 
diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
index 1b687765b8..e74e34f78f 100644
--- a/net/mdio-uclass.c
+++ b/net/mdio-uclass.c
@@ -101,7 +101,7 @@ static int dm_mdio_post_probe(struct udevice *dev)
 	pdata->mii_bus->write = mdio_write;
 	pdata->mii_bus->reset = mdio_reset;
 	pdata->mii_bus->priv = dev;
-	strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1);
+	strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN);
 
 	return mdio_register(pdata->mii_bus);
 }
diff --git a/scripts/coccinelle/net/mdio_register.cocci b/scripts/coccinelle/net/mdio_register.cocci
index 100f102936..7d11281f46 100644
--- a/scripts/coccinelle/net/mdio_register.cocci
+++ b/scripts/coccinelle/net/mdio_register.cocci
@@ -16,12 +16,12 @@ identifier readfunc, writefunc;
 - miiphy_register(devname, readfunc, writefunc);
 + struct mii_dev *mdiodev = mdio_alloc();
 + if (!mdiodev) return -ENOMEM;
-+ strncpy(mdiodev->name, devname, MDIO_NAME_LEN);
++ strlcpy(mdiodev->name, devname, MDIO_NAME_LEN);
 + mdiodev->read = readfunc;
 + mdiodev->write = writefunc;
 + 
 + retval = mdio_register(mdiodev);
-+ if (retval < 0) return retval;
++ if (retval < 0) { mdio_free(mdiodev); return retval; }
 
 @ update_read_sig @
 identifier mii_reg.readfunc;
diff --git a/test/dm/dsa.c b/test/dm/dsa.c
index 18c1776460..c857106eaf 100644
--- a/test/dm/dsa.c
+++ b/test/dm/dsa.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020-2021 NXP Semiconductors
+ * Copyright 2020-2021 NXP
  */
 
 #include <net/dsa.h>