diff options
| author | Simon Glass <sjg@chromium.org> | 2019-01-21 14:53:30 -0700 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2019-02-01 16:59:13 +0100 |
| commit | 5328af17742d35d50f64666c63c2824113d6903a (patch) | |
| tree | 5c9869af2fcde7be74bb3c92020f62f908f18155 | |
| parent | cf5c8d188058dd87310bc8f5870795445029b071 (diff) | |
| download | u-boot-5328af17742d35d50f64666c63c2824113d6903a.tar.gz | |
rockchip: clk: Add mention of four new clocks
These clocks are needed to get MMC running. We don't actually support
setting them yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 198914b067..cab2bd9943 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -925,7 +925,13 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3399_saradc_get_clk(priv->cru); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + break; default: + log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; } @@ -993,7 +999,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3399_saradc_set_clk(priv->cru, rate); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + return 0; default: + log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; } |