diff options
| author | Marek Behún <marek.behun@nic.cz> | 2018-04-24 17:21:22 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-05-14 10:00:15 +0200 |
| commit | 3282a3e75fbea752f96df63baaad4c7f7d14d3b6 (patch) | |
| tree | f9b975d910200bb09c8548903d13fd92d59654ec | |
| parent | 7586ac2b49dd3046868354201ab6a208c3a5b82c (diff) | |
| download | u-boot-3282a3e75fbea752f96df63baaad4c7f7d14d3b6.tar.gz | |
phy: marvell: a3700: Fix SGMII cfg and stat register addresses
The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 7990aab1c6..0f0138dc97 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -24,7 +24,7 @@ #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC) #define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0)) -#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28) +#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28) #define rb_pin_pu_iveref BIT(1) #define rb_pin_reset_core BIT(11) #define rb_pin_reset_comphy BIT(12) @@ -38,7 +38,7 @@ #define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift) #define rb_phy_rx_init BIT(30) -#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28) +#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28) #define rb_rx_init_done BIT(0) #define rb_pll_ready_rx BIT(2) #define rb_pll_ready_tx BIT(3) |