diff options
| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2019-03-01 10:11:13 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2019-03-19 09:22:05 +0100 |
| commit | 08dcbc98236c4ea9eb4b9d4731a53022204c4809 (patch) | |
| tree | 150b647ed02a9b925602e732fc61fb656c4eb52c | |
| parent | 5860532264326d8eb387ccfd9037792cc6d57fd1 (diff) | |
| download | u-boot-08dcbc98236c4ea9eb4b9d4731a53022204c4809.tar.gz | |
mv_ddr: ddr3: fix tRAS timimg parameter
Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_db.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 111a8586c6..b2f11a8399 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd result = speed_bin_table_t_rcd_t_rp[index]; break; case SPEED_BIN_TRAS: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 37500; - else if (index < SPEED_BIN_DDR_1333J) + else if (index <= SPEED_BIN_DDR_1333J) result = 36000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 35000; - else if (index < SPEED_BIN_DDR_1866M) + else if (index <= SPEED_BIN_DDR_1866M) result = 34000; else result = 33000; |