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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> | 2018-11-14 17:20:18 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-02-15 15:04:01 +0100 |
| commit | 053d4bd4727185f292a0bb2ac080c8c6ae794cbe (patch) | |
| tree | aa02591f2283deb7f92543686905d534c8dd24ee | |
| parent | ccc8a11935214464a4a6a6f4055b4c05a28f735d (diff) | |
| download | u-boot-053d4bd4727185f292a0bb2ac080c8c6ae794cbe.tar.gz | |
arm64: zynqmp: Change the spi-rx-bus-width property to x1
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | arch/arm/dts/zynqmp-zc1275-revB.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts index e84b2da164..1a7975b551 100644 --- a/arch/arm/dts/zynqmp-zc1275-revB.dts +++ b/arch/arm/dts/zynqmp-zc1275-revB.dts @@ -47,7 +47,7 @@ #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; |