Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/24Sep2020-next

Xilinx changes for v2021.01

arm64:
- Support for bigger U-Boot images compiled with PIE

microblaze:
- Extend support for LE/BE systems

zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode

zynqmp-r5:
- Fix MPU mapping and defconfig setting.

xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot

cmd:
- pxe: Add fixing for platforms with manual relocation support

clk:
- fixed_rate: Add DM flag to support early boot on r5

fpga:
- zynqmppl: Use only firmware interface and enable SPL build

serial:
- uartlite: Enable for ARM systems and support endians

mmc:
- zynq: Fix indentation

net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64

kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values

bindings:
- Add binding doc for vsc8531

51 files changed, 499 insertions, 298 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 68d6d1afd6..6a0227819b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,8 +16,8 @@ config POSITION_INDEPENDENT
 	help
 	  U-Boot expects to be linked to a specific hard-coded address, and to
 	  be loaded to and run from that address. This option lifts that
-	  restriction, thus allowing the code to be loaded to and executed
-	  from almost any address. This logic relies on the relocation
+	  restriction, thus allowing the code to be loaded to and executed from
+	  almost any 4K aligned address. This logic relies on the relocation
 	  information that is embedded in the binary to support U-Boot
 	  relocating itself to the top-of-RAM later during execution.
 
@@ -1155,7 +1155,8 @@ config ARCH_ZYNQMP
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
-	select SPL_DM_SPI if SPI
+	select SPL_DM if SPL
+	select SPL_DM_SPI if SPI && SPL_DM
 	select SPL_DM_SPI_FLASH if SPL_DM_SPI
 	select SPL_DM_MAILBOX if SPL
 	select SPL_FIRMWARE if SPL
@@ -2000,10 +2001,6 @@ source "board/tcl/sl50/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
-source "board/xilinx/Kconfig"
-source "board/xilinx/zynq/Kconfig"
-source "board/xilinx/zynqmp/Kconfig"
-source "board/xilinx/versal/Kconfig"
 source "board/phytium/durian/Kconfig"
 source "board/xen/xenguest_arm64/Kconfig"
 
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 002698b501..e5c2856cf5 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -59,6 +59,23 @@ reset:
 save_boot_params_ret:
 
 #if CONFIG_POSITION_INDEPENDENT
+	/* Verify that we're 4K aligned.  */
+	adr	x0, _start
+	ands	x0, x0, #0xfff
+	b.eq	1f
+0:
+	/*
+	 * FATAL, can't continue.
+	 * U-Boot needs to be loaded at a 4K aligned address.
+	 *
+	 * We use ADRP and ADD to load some symbol addresses during startup.
+	 * The ADD uses an absolute (non pc-relative) lo12 relocation
+	 * thus requiring 4K alignment.
+	 */
+	wfi
+	b	0b
+1:
+
 	/*
 	 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
 	 * executed at a different address than it was linked at.
@@ -67,8 +84,10 @@ pie_fixup:
 	adr	x0, _start		/* x0 <- Runtime value of _start */
 	ldr	x1, _TEXT_BASE		/* x1 <- Linked value of _start */
 	sub	x9, x0, x1		/* x9 <- Run-vs-link offset */
-	adr	x2, __rel_dyn_start	/* x2 <- Runtime &__rel_dyn_start */
-	adr	x3, __rel_dyn_end	/* x3 <- Runtime &__rel_dyn_end */
+	adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
+	add     x2, x2, #:lo12:__rel_dyn_start
+	adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
+	add     x3, x3, #:lo12:__rel_dyn_end
 pie_fix_loop:
 	ldp	x0, x1, [x2], #16	/* (x0, x1) <- (Link location, fixup) */
 	ldr	x4, [x2], #8		/* x4 <- addend */
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index a8bbb14f6c..aae3c626f5 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -230,16 +230,16 @@
 				#io-channel-cells = <1>;
 				label = "ina226-vccint";
 				reg = <0x40>;
-				shunt-resistor = <5000>; /* R440 */
-				/* 0.78V @ 32A 1 of 6 Phases*/
+				shunt-resistor = <500>; /* R440 */
+				/* 0.80V @ 32A 1 of 6 Phases*/
 			};
 			vcc_soc: ina226@41 { /* u161 */
 				compatible = "ti,ina226";
 				#io-channel-cells = <1>;
 				label = "ina226-vcc-soc";
 				reg = <0x41>;
-				shunt-resistor = <2000>; /* R1186 */
-				/* 0.78V @ 18A */
+				shunt-resistor = <500>; /* R1702 */
+				/* 0.80V @ 18A */
 			};
 			vcc_pmc: ina226@42 { /* u163 */
 				compatible = "ti,ina226";
@@ -554,6 +554,31 @@
 			reg = <7>;
 		};
 	};
+	i2c-mux@75 { /* u214 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		i2c@0 { /* SFP0_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* SFP0 */
+		};
+		i2c@1 { /* SFP1_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* SFP1 */
+		};
+		i2c@2 { /* QSFP1_I2C */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* QSFP1 */
+		};
+		/* 3 - 7 unused */
+	};
 };
 
 &xilinx_ams {
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 04afa518ac..9d2319c0e8 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -73,7 +73,12 @@ ENTRY(_main)
 #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	x0, =(CONFIG_SPL_STACK)
 #elif defined(CONFIG_INIT_SP_RELATIVE)
+#if CONFIG_POSITION_INDEPENDENT
+	adrp	x0, __bss_start     /* x0 <- Runtime &__bss_start */
+	add	x0, x0, #:lo12:__bss_start
+#else
 	adr	x0, __bss_start
+#endif
 	add	x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
 #else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -102,7 +107,8 @@ ENTRY(_main)
 	adr	lr, relocation_return
 #if CONFIG_POSITION_INDEPENDENT
 	/* Add in link-vs-runtime offset */
-	adr	x0, _start		/* x0 <- Runtime value of _start */
+	adrp	x0, _start		/* x0 <- Runtime value of _start */
+	add	x0, x0, #:lo12:_start
 	ldr	x9, _TEXT_BASE		/* x9 <- Linked value of _start */
 	sub	x9, x9, x0		/* x9 <- Run-vs-link offset */
 	add	lr, lr, x9
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index e1d66e8d32..ebd2da3887 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -62,4 +62,7 @@ config VERSAL_NO_DDR
 	  This option configures MMU with no DDR to avoid speculative
 	  access to DDR memory where DDR is not present.
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/versal/Kconfig"
+
 endif
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 79f831e6df..e54310383b 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -70,4 +70,7 @@ config BOOT_INIT_FILE
 config ZYNQ_SDHCI_MAX_FREQ
 	default 52000000
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
+
 endif
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 77b7cb1307..3befc12028 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -17,8 +17,7 @@
 #define ZYNQ_SILICON_VER_MASK	0xF0000000
 #define ZYNQ_SILICON_VER_SHIFT	28
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
 xilinx_desc fpga = {
 	.family = xilinx_zynq,
 	.iface = devcfg,
@@ -111,8 +110,7 @@ static int __maybe_unused cpu_desc_id(void)
 #if defined(CONFIG_ARCH_EARLY_INIT_R)
 int arch_early_init_r(void)
 {
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
 	int cpu_id = cpu_desc_id();
 
 	if (cpu_id < 0)
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 239ce3436a..cb8cfd2f35 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -34,7 +34,7 @@ void board_init_f(ulong dummy)
 void spl_board_init(void)
 {
 	preloader_console_init();
-#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
+#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
 	arch_early_init_r();
 #endif
 	board_init();
diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c
index b3402d7189..87c1d75f9f 100644
--- a/arch/arm/mach-zynqmp-r5/cpu.c
+++ b/arch/arm/mach-zynqmp-r5/cpu.c
@@ -11,11 +11,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct mpu_region_config region_config[] = {
-	{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
-	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
-	{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
-	  O_I_WB_RD_WR_ALLOC, REGION_512MB },
-	{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
+	{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
+	  SHARED_WRITE_BUFFERED, REGION_4GB },
+	{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
 	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
 };
 
@@ -23,8 +21,7 @@ int arch_cpu_init(void)
 {
 	gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
 
-	setup_mpu_regions(region_config, sizeof(region_config) /
-			  sizeof(struct mpu_region_config));
+	setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
 
 	return 0;
 }
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index d82a737a69..f1301f6661 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -171,4 +171,7 @@ config SD1_LSHFT_MODE
 
 endchoice
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
+
 endif
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index 64e5320acc..7d7ab9da6e 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -65,7 +65,7 @@ struct xfsbl_atf_handoff_params {
 	struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
 };
 
-#ifdef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_ATF
 struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
 					     uintptr_t bl33_entry,
 					     uintptr_t fdt_addr)
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8e6be0ae26..632bb236fb 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -50,14 +50,24 @@
 #define outw(x, addr)	((void)writew(x, addr))
 #define outl(x, addr)	((void)writel(x, addr))
 
-/* Some #definitions to keep strange Xilinx code happy */
-#define in_8(addr)	readb(addr)
-#define in_be16(addr)	readw(addr)
-#define in_be32(addr)	readl(addr)
+#define out_arch(type, endian, addr, x)	\
+		 __raw_write##type(cpu_to_##endian(x), addr)
+#define in_arch(type, endian, addr)	\
+		endian##_to_cpu(__raw_read##type(addr))
+
+#define out_le16(addr, x)	out_arch(w, le16, addr, x)
+#define out_le32(addr, x)	out_arch(l, le32, addr, x)
+
+#define in_le16(addr)		in_arch(w, le16, addr)
+#define in_le32(addr)		in_arch(l, le32, addr)
+
+#define in_8(addr)		readb(addr)
+#define in_be16(addr)		in_arch(w, be16, addr)
+#define in_be32(addr)		in_arch(l, be32, addr)
 
 #define out_8(addr, x)		outb(x, addr)
-#define out_be16(addr, x)	outw(x, addr)
-#define out_be32(addr, x)	outl(x, addr)
+#define out_be16(addr, x)	out_arch(w, be16, addr, x)
+#define out_be32(addr, x)	out_arch(l, be32, addr, x)
 
 #define inb_p(port)		inb((port))
 #define outb_p(val, port)	outb((val), (port))
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 73fc1be014..c80d0a8812 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -41,7 +41,7 @@ config XILINX_PS_INIT_FILE
 endif
 
 config XILINX_OF_BOARD_DTB_ADDR
-	hex
+	hex "Default DTB pickup address"
 	default 0x1000 if ARCH_VERSAL
 	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
 	depends on OF_BOARD || OF_SEPARATE
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index eab389d049..b0f60c40a5 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -44,7 +44,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
 void *board_fdt_blob_setup(void)
 {
-	static void *fdt_blob;
+	void *fdt_blob;
 
 #if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
 	fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index bcfd56a912..28f067a251 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,6 +9,7 @@
 #include <cpu_func.h>
 #include <debug_uart.h>
 #include <env.h>
+#include <env_internal.h>
 #include <init.h>
 #include <log.h>
 #include <net.h>
@@ -38,181 +39,156 @@
 
 #include "pm_cfg_obj.h"
 
+#define ZYNQMP_VERSION_SIZE	7
+#define EFUSE_VCU_DIS_MASK     0x100
+#define EFUSE_VCU_DIS_SHIFT    8
+#define EFUSE_GPU_DIS_MASK     0x20
+#define EFUSE_GPU_DIS_SHIFT    5
+#define IDCODE2_PL_INIT_MASK   0x200
+#define IDCODE2_PL_INIT_SHIFT  9
+
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0U),
+	ZYNQMP_VARIANT_EV = BIT(1U),
+	ZYNQMP_VARIANT_CG = BIT(2U),
+	ZYNQMP_VARIANT_DR = BIT(3U),
+};
+
 static const struct {
 	u32 id;
-	u32 ver;
-	char *name;
-	bool evexists;
+	u8 device;
+	u8 variants;
 } zynqmp_devices[] = {
 	{
-		.id = 0x10,
-		.name = "3eg",
-	},
-	{
-		.id = 0x10,
-		.ver = 0x2c,
-		.name = "3cg",
-	},
-	{
-		.id = 0x11,
-		.name = "2eg",
-	},
-	{
-		.id = 0x11,
-		.ver = 0x2c,
-		.name = "2cg",
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.name = "5ev",
-		.evexists = 1,
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x100,
-		.name = "5eg",
-		.evexists = 1,
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x12c,
-		.name = "5cg",
-		.evexists = 1,
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.name = "4ev",
-		.evexists = 1,
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x100,
-		.name = "4eg",
-		.evexists = 1,
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x12c,
-		.name = "4cg",
-		.evexists = 1,
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.name = "7ev",
-		.evexists = 1,
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x100,
-		.name = "7eg",
-		.evexists = 1,
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x12c,
-		.name = "7cg",
-		.evexists = 1,
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.name = "9eg",
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.ver = 0x2c,
-		.name = "9cg",
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.name = "6eg",
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.ver = 0x2c,
-		.name = "6cg",
-	},
-	{
-		.id = 0x40,
-		.name = "11eg",
-	},
-	{ /* For testing purpose only */
-		.id = 0x50,
-		.ver = 0x2c,
-		.name = "15cg",
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x50,
-		.name = "15eg",
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x58,
-		.name = "19eg",
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x59,
-		.name = "17eg",
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x61,
-		.name = "21dr",
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x63,
-		.name = "23dr",
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x65,
-		.name = "25dr",
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x64,
-		.name = "27dr",
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x60,
-		.name = "28dr",
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x62,
-		.name = "29dr",
-	},
-	{
-		.id = 0x66,
-		.name = "39dr",
-	},
-	{
-		.id = 0x7b,
-		.name = "48dr",
-	},
-	{
-		.id = 0x7e,
-		.name = "49dr",
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 };
-#endif
 
-#define ZYNQMP_VERSION_SIZE		9
-#define ZYNQMP_PL_STATUS_BIT		9
-#define ZYNQMP_IPDIS_VCU_BIT		8
-#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
-#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
-#define ZYNQMP_CSU_VCUDIS_VER_MASK	ZYNQMP_CSU_VERSION_MASK & \
-					~BIT(ZYNQMP_IPDIS_VCU_BIT)
-#define MAX_VARIANTS_EV			3
-
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	u32 i, id, ver, j;
-	char *buf;
-	static char name[ZYNQMP_VERSION_SIZE];
+	u32 i;
+	u32 idcode, idcode2;
+	char name[ZYNQMP_VERSION_SIZE];
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
 	xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
@@ -226,61 +202,71 @@ static char *zynqmp_get_silicon_idcode_name(void)
 	 * payload[2][29] = PL_INIT
 	 */
 
-	/* Get IDCODE field */
-	id = ret_payload[1];
-	id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK;
-	id >>=	ZYNQMP_CSU_IDCODE_SVD_SHIFT;
-
-	/* Shift silicon version info */
-	ver = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
-
-	debug("%s, ID: 0x%0X, Ver: 0x%0X\r\n", __func__, id, ver);
+	idcode  = ret_payload[1];
+	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+	debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
+	      idcode2);
 
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id) {
-			if (zynqmp_devices[i].evexists &&
-			    !(ver & ZYNQMP_PL_STATUS_MASK))
-				break;
-			if (zynqmp_devices[i].ver == (ver &
-			    ZYNQMP_CSU_VERSION_MASK))
-				break;
-		}
+		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
+			break;
 	}
 
 	if (i >= ARRAY_SIZE(zynqmp_devices))
 		return "unknown";
 
-	strncat(name, "zu", 2);
-	if (!zynqmp_devices[i].evexists ||
-	    (ver & ZYNQMP_PL_STATUS_MASK)) {
-		strncat(name, zynqmp_devices[i].name,
-			ZYNQMP_VERSION_SIZE - 3);
-		return name;
-	}
-
-	/*
-	 * Here we are means, PL not powered up and ev variant
-	 * exists. So, we need to ignore VCU disable bit(8) in
-	 * version and findout if its CG or EG/EV variant.
-	 */
-	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
-		if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
-		    (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
-			strncat(name, zynqmp_devices[i].name,
-				ZYNQMP_VERSION_SIZE - 3);
-			break;
+	/* Add device prefix to the name */
+	strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
+	strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
+
+	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
+
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strncat(name, "ev", 2);
+				break;
+			case 0x10:
+				strncat(name, "eg", 2);
+				break;
+			case 0x11:
+				strncat(name, "cg", 2);
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
+				"e", 2);
 		}
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
+		strncat(name, "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
+		strncat(name, "dr", 2);
+	} else {
+		debug("Variant not identified\n");
 	}
 
-	if (j >= MAX_VARIANTS_EV)
-		return "unknown";
-
-	if (strstr(name, "eg") || strstr(name, "ev")) {
-		buf = strstr(name, "e");
-		*buf = '\0';
-	}
-
-	return name;
+	return strdup(name);
 }
 #endif
 
@@ -342,9 +328,7 @@ int board_init(void)
 	/* Bug in ROM sets wrong value in this register */
 	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
-    defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 	zynqmppl.name = zynqmp_get_silicon_idcode_name();
 	printf("Chip ID:\t%s\n", zynqmppl.name);
 	fpga_init();
@@ -444,6 +428,24 @@ void reset_cpu(ulong addr)
 {
 }
 
+static u8 __maybe_unused zynqmp_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
 #if defined(CONFIG_BOARD_LATE_INIT)
 static const struct {
 	u32 bit;
@@ -527,24 +529,6 @@ static int set_fdtfile(void)
 	return 0;
 }
 
-static u8 zynqmp_get_bootmode(void)
-{
-	u8 bootmode;
-	u32 reg = 0;
-	int ret;
-
-	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
-	if (ret)
-		return -EINVAL;
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
-
-	return bootmode;
-}
-
 int board_late_init(void)
 {
 	u8 bootmode;
@@ -689,3 +673,37 @@ int checkboard(void)
 	puts("Board: Xilinx ZynqMP\n");
 	return 0;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynqmp_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case NAND_MODE:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 6372fc9871..46ac08fa3a 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -212,10 +212,24 @@ static struct cmd_tbl cmd_pxe_sub[] = {
 	U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "")
 };
 
+static void __maybe_unused pxe_reloc(void)
+{
+	static int relocated_pxe;
+
+	if (!relocated_pxe) {
+		fixup_cmdtable(cmd_pxe_sub, ARRAY_SIZE(cmd_pxe_sub));
+		relocated_pxe = 1;
+	}
+}
+
 static int do_pxe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	struct cmd_tbl *cp;
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	pxe_reloc();
+#endif
+
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index af8255a8d6..807b1dc059 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -602,7 +602,7 @@ config SPL_FAT_WRITE
 	  Support for the underlying block device (e.g. MMC or USB) must be
 	  enabled separately.
 
-config SPL_FPGA_SUPPORT
+config SPL_FPGA
 	bool "Support FPGAs"
 	help
 	  Enable support for FPGAs in SPL. Field-programmable Gate Arrays
@@ -1271,7 +1271,7 @@ config SPL_YMODEM_SUPPORT
 
 config SPL_ATF
 	bool "Support ARM Trusted Firmware"
-	depends on ARM64
+	depends on ARM64 && SPL_FIT
 	help
 	  ATF(ARM Trusted Firmware) is a component for ARM AArch64 which
 	  is loaded by SPL (which is considered as BL2 in ATF terminology).
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a8bfd388b1..0e27ad1d6a 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -253,7 +253,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 	const void *data;
 	bool external_data = false;
 
-	if (IS_ENABLED(CONFIG_SPL_FPGA_SUPPORT) ||
+	if (IS_ENABLED(CONFIG_SPL_FPGA) ||
 	    (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
 		if (fit_image_get_type(fit, node, &type))
 			puts("Cannot get image type.\n");
@@ -546,7 +546,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 		return -1;
 	}
 
-#ifdef CONFIG_SPL_FPGA_SUPPORT
+#ifdef CONFIG_SPL_FPGA
 	node = spl_fit_get_image_node(fit, images, "fpga", 0);
 	if (node >= 0) {
 		/* Load the image and set up the spl_image structure */
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index dd44168f5a..25282ba428 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 8fdd21c0d3..5d6fe4f35a 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FPGA=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 4c463f48ee..5175571c66 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x100000
@@ -25,12 +26,15 @@ CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -64,6 +68,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
@@ -71,10 +76,11 @@ CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
 CONFIG_PHY_GIGE=y
-CONFIG_MII=y
+CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ARM_DCC=y
 CONFIG_PL01X_SERIAL=y
+CONFIG_XILINX_UARTLITE=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
@@ -93,4 +99,3 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 8acdab25b7..b127945297 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -20,7 +20,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 # CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 485bc558de..4d313e17ea 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -49,7 +49,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 43a857d516..ccd933f314 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -49,7 +49,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index a7cd93ebed..6ada8623ab 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -49,6 +49,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SYS_NAND_MAX_CHIPS=2
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index fb657bf1b2..04e17482fa 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -49,6 +49,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 706e7980f9..0fff0db364 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -8,8 +8,8 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
-# CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
+# CONFIG_PSCI_RESET is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
 # CONFIG_EXPERT is not set
 # CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -49,7 +49,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig
index 713418e611..f7433e994d 100644
--- a/configs/xilinx_zynqmp_r5_defconfig
+++ b/configs/xilinx_zynqmp_r5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQMP_R5=y
 CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DEBUG_UART_BASE=0xff010000
@@ -18,3 +19,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_TIMER=y
 CONFIG_CADENCE_TTC_TIMER=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index a0984c8045..264b662ece 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -58,10 +58,13 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
@@ -95,6 +98,7 @@ CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SYS_NAND_MAX_CHIPS=2
@@ -107,6 +111,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -116,11 +121,12 @@ CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
-CONFIG_MII=y
+CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_ARM_DCC=y
+CONFIG_XILINX_UARTLITE=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_SPI=y
 CONFIG_ZYNQ_SPI=y
@@ -146,4 +152,3 @@ CONFIG_WDT_CDNS=y
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/drivers/Makefile b/drivers/Makefile
index 33126b2da7..9eb51453e5 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
 obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
 obj-$(CONFIG_$(SPL_)BOARD) += board/
 obj-$(CONFIG_XEN) += xen/
+obj-$(CONFIG_$(SPL_)FPGA) += fpga/
 
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
@@ -60,7 +61,6 @@ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
 obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/
-obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 obj-$(CONFIG_SPL_THERMAL) += thermal/
 
 endif
@@ -85,7 +85,6 @@ obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
-obj-$(CONFIG_FPGA) += fpga/
 obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 2c20eddb0b..55e1f8caa5 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -53,4 +53,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
 	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
 	.ops = &clk_fixed_rate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 2313ac0bc0..7795119756 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -710,7 +710,7 @@ static const struct udevice_id zynqmp_clk_ids[] = {
 };
 
 U_BOOT_DRIVER(zynqmp_clk) = {
-	.name = "zynqmp-clk",
+	.name = "zynqmp_clk",
 	.id = UCLASS_CLK,
 	.of_match = zynqmp_clk_ids,
 	.probe = zynqmp_clk_probe,
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 903a8f5878..7583f24a20 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -202,6 +202,6 @@ static const struct udevice_id zynqmp_firmware_ids[] = {
 
 U_BOOT_DRIVER(zynqmp_firmware) = {
 	.id = UCLASS_FIRMWARE,
-	.name = "zynqmp-firmware",
+	.name = "zynqmp_firmware",
 	.of_match = zynqmp_firmware_ids,
 };
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 5b103cfeaf..8ce140a2e1 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -231,11 +231,11 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_hi = upper_32_bits(bin_buf);
 
 	if (xilfpga_old)
-		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 					buf_hi, (u32)(uintptr_t)bsizeptr,
 					bstype, ret_payload);
 	else
-		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 					buf_hi, (u32)bsize, 0, ret_payload);
 
 	if (ret)
@@ -277,7 +277,7 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_lo = lower_32_bits((ulong)buf);
 	buf_hi = upper_32_bits((ulong)buf);
 
-	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+	ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 				buf_hi,
 			 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 			 flag, ret_payload);
@@ -295,7 +295,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
 	int ret;
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+	ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
 				0, ret_payload);
 	if (!ret)
 		printf("PCAP status\t0x%x\n", ret_payload[1]);
@@ -305,7 +305,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
 
 struct xilinx_fpga_op zynqmp_op = {
 	.load = zynqmp_load,
-#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
 	.loads = zynqmp_loads,
 #endif
 	.info = zynqmp_pcap_info,
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 024c63c4ea..7144d39984 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -500,7 +500,7 @@ static const struct udevice_id cdns_i2c_of_match[] = {
 };
 
 U_BOOT_DRIVER(cdns_i2c) = {
-	.name = "i2c-cdns",
+	.name = "i2c_cdns",
 	.id = UCLASS_I2C,
 	.of_match = cdns_i2c_of_match,
 	.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 746377e557..9483ed9cef 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -133,7 +133,7 @@ struct mbox_ops zynqmp_ipi_mbox_ops = {
 };
 
 U_BOOT_DRIVER(zynqmp_ipi) = {
-	.name = "zynqmp-ipi",
+	.name = "zynqmp_ipi",
 	.id = UCLASS_MAILBOX,
 	.of_match = zynqmp_ipi_ids,
 	.probe = zynqmp_ipi_probe,
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e9381b9493..775c17baac 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -191,7 +191,7 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
 
 #if defined(CONFIG_ARCH_ZYNQMP)
 const struct sdhci_ops arasan_ops = {
-	.platform_execute_tuning	= &arasan_sdhci_execute_tuning,
+	.platform_execute_tuning = &arasan_sdhci_execute_tuning,
 	.set_delay = &arasan_sdhci_set_tapdelay,
 	.set_control_reg = &arasan_sdhci_set_control_reg,
 };
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 06b2ff972c..df4cbd52cf 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -233,7 +233,7 @@ endif
 config NAND_ARASAN
 	bool "Configure Arasan Nand"
 	select SYS_NAND_SELF_INIT
-	select DM_MTD
+	depends on DM_MTD
 	imply CMD_NAND
 	help
 	  This enables Nand driver support for Arasan nand flash
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 6c1d64054c..0615e50378 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -1306,7 +1306,7 @@ static const struct udevice_id arasan_nand_dt_ids[] = {
 };
 
 U_BOOT_DRIVER(arasan_nand) = {
-	.name = "arasan-nand",
+	.name = "arasan_nand",
 	.id = UCLASS_MTD,
 	.of_match = arasan_nand_dt_ids,
 	.probe = arasan_probe,
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index fa59455210..92db2aa19c 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -1282,7 +1282,7 @@ static const struct udevice_id zynq_nand_dt_ids[] = {
 };
 
 U_BOOT_DRIVER(zynq_nand) = {
-	.name = "zynq-nand",
+	.name = "zynq_nand",
 	.id = UCLASS_MTD,
 	.of_match = zynq_nand_dt_ids,
 	.probe = zynq_nand_probe,
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 99d4d85c52..8af3711204 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -101,10 +101,10 @@ struct axidma_priv {
 
 /* BD descriptors */
 struct axidma_bd {
-	u32 next;	/* Next descriptor pointer */
-	u32 reserved1;
-	u32 phys;	/* Buffer address */
-	u32 reserved2;
+	u32 next_desc;	/* Next descriptor pointer */
+	u32 next_desc_msb;
+	u32 buf_addr;	/* Buffer address */
+	u32 buf_addr_msb;
 	u32 reserved3;
 	u32 reserved4;
 	u32 cntrl;	/* Control */
@@ -182,7 +182,7 @@ static inline int mdio_wait(struct axi_regs *regs)
 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
 {
 #if defined(CONFIG_PHYS_64BIT)
-	writeq(bd, desc);
+	writeq((unsigned long)bd, desc);
 #else
 	writel((u32)bd, desc);
 #endif
@@ -492,15 +492,19 @@ static int axiemac_start(struct udevice *dev)
 
 	/* Setup the BD. */
 	memset(&rx_bd, 0, sizeof(rx_bd));
-	rx_bd.next = (u32)&rx_bd;
-	rx_bd.phys = (u32)&rxframe;
+	rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+	rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
 	rx_bd.cntrl = sizeof(rxframe);
 	/* Flush the last BD so DMA core could see the updates */
-	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+	flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
 
 	/* It is necessary to flush rxframe because if you don't do it
 	 * then cache can contain uninitialized data */
-	flush_cache((u32)&rxframe, sizeof(rxframe));
+	flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
 
 	/* Start the hardware */
 	temp = readl(&priv->dmarx->control);
@@ -534,19 +538,23 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 		len = PKTSIZE_ALIGN;
 
 	/* Flush packet to main memory to be trasfered by DMA */
-	flush_cache((u32)ptr, len);
+	flush_cache((phys_addr_t)ptr, len);
 
 	/* Setup Tx BD */
 	memset(&tx_bd, 0, sizeof(tx_bd));
 	/* At the end of the ring, link the last BD back to the top */
-	tx_bd.next = (u32)&tx_bd;
-	tx_bd.phys = (u32)ptr;
+	tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
+	tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
+#if defined(CONFIG_PHYS_64BIT)
+	tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
+	tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
+#endif
 	/* Save len */
 	tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 						XAXIDMA_BD_CTRL_TXEOF_MASK;
 
 	/* Flush the last BD so DMA core could see the updates */
-	flush_cache((u32)&tx_bd, sizeof(tx_bd));
+	flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
 
 	if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 		u32 temp;
@@ -637,16 +645,20 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 	/* Setup RxBD */
 	/* Clear the whole buffer and setup it again - all flags are cleared */
 	memset(&rx_bd, 0, sizeof(rx_bd));
-	rx_bd.next = (u32)&rx_bd;
-	rx_bd.phys = (u32)&rxframe;
+	rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+	rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
 	rx_bd.cntrl = sizeof(rxframe);
 
 	/* Write bd to HW */
-	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+	flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
 
 	/* It is necessary to flush rxframe because if you don't do it
 	 * then cache will contain previous packet */
-	flush_cache((u32)&rxframe, sizeof(rxframe));
+	flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
 
 	/* Rx BD is ready - start again */
 	axienet_dma_write(&rx_bd, &priv->dmarx->tail);
@@ -738,7 +750,7 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 	/* RX channel offset is 0x30 */
-	priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
+	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
 
 	priv->phyaddr = -1;
 
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index da4b6fba9f..8afec8bbfc 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -758,6 +758,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 
 	if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
 					&phandle_args)) {
+		fdt_addr_t addr;
+		ofnode parent;
+
 		debug("phy-handle does exist %s\n", dev->name);
 		priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
 							"reg", -1);
@@ -765,6 +768,13 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 		priv->max_speed = ofnode_read_u32_default(phandle_args.node,
 							  "max-speed",
 							  SPEED_1000);
+
+		parent = ofnode_get_parent(phandle_args.node);
+		addr = ofnode_get_addr(parent);
+		if (addr != FDT_ADDR_T_NONE) {
+			debug("MDIO bus not found %s\n", dev->name);
+			priv->mdiobase = (struct zynq_gem_regs *)addr;
+		}
 	}
 
 	phy_mode = dev_read_prop(dev, "phy-mode", NULL);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e344677f91..b4805a2e4e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -734,7 +734,7 @@ config UNIPHIER_SERIAL
 
 config XILINX_UARTLITE
 	bool "Xilinx Uarlite support"
-	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
+	depends on DM_SERIAL
 	help
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
@@ -802,7 +802,7 @@ config STM32_SERIAL
 
 config ZYNQ_SERIAL
 	bool "Cadence (Xilinx Zynq) UART support"
-	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5)
+	depends on DM_SERIAL
 	help
 	  This driver supports the Cadence UART. It is found e.g. in Xilinx
 	  Zynq/ZynqMP.
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 5116d13751..236ab860ad 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -23,6 +23,8 @@
 #define ULITE_CONTROL_RST_TX	0x01
 #define ULITE_CONTROL_RST_RX	0x02
 
+static bool little_endian;
+
 struct uartlite {
 	unsigned int rx_fifo;
 	unsigned int tx_fifo;
@@ -34,15 +36,31 @@ struct uartlite_platdata {
 	struct uartlite *regs;
 };
 
+static u32 uart_in32(void __iomem *addr)
+{
+	if (little_endian)
+		return in_le32(addr);
+	else
+		return in_be32(addr);
+}
+
+static void uart_out32(void __iomem *addr, u32 val)
+{
+	if (little_endian)
+		out_le32(addr, val);
+	else
+		out_be32(addr, val);
+}
+
 static int uartlite_serial_putc(struct udevice *dev, const char ch)
 {
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
 
-	if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+	if (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
 		return -EAGAIN;
 
-	out_be32(&regs->tx_fifo, ch & 0xff);
+	uart_out32(&regs->tx_fifo, ch & 0xff);
 
 	return 0;
 }
@@ -52,10 +70,10 @@ static int uartlite_serial_getc(struct udevice *dev)
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
 
-	if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
+	if (!(uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA))
 		return -EAGAIN;
 
-	return in_be32(&regs->rx_fifo) & 0xff;
+	return uart_in32(&regs->rx_fifo) & 0xff;
 }
 
 static int uartlite_serial_pending(struct udevice *dev, bool input)
@@ -64,19 +82,26 @@ static int uartlite_serial_pending(struct udevice *dev, bool input)
 	struct uartlite *regs = plat->regs;
 
 	if (input)
-		return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
+		return uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA;
 
-	return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
+	return !(uart_in32(&regs->status) & SR_TX_FIFO_EMPTY);
 }
 
 static int uartlite_serial_probe(struct udevice *dev)
 {
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
-
-	out_be32(&regs->control, 0);
-	out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
-	in_be32(&regs->control);
+	int ret;
+
+	uart_out32(&regs->control, 0);
+	uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	ret = uart_in32(&regs->status);
+	/* Endianness detection */
+	if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+		little_endian = true;
+		uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+			   ULITE_CONTROL_RST_TX);
+	}
 
 	return 0;
 }
@@ -119,20 +144,27 @@ U_BOOT_DRIVER(serial_uartlite) = {
 static inline void _debug_uart_init(void)
 {
 	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
-
-	out_be32(&regs->control, 0);
-	out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
-	in_be32(&regs->control);
+	int ret;
+
+	uart_out32(&regs->control, 0);
+	uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	uart_in32(&regs->status);
+	/* Endianness detection */
+	if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+		little_endian = true;
+		uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+			   ULITE_CONTROL_RST_TX);
+	}
 }
 
 static inline void _debug_uart_putc(int ch)
 {
 	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
 
-	while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+	while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
 		;
 
-	out_be32(&regs->tx_fifo, ch & 0xff);
+	uart_out32(&regs->tx_fifo, ch & 0xff);
 }
 
 DEBUG_UART_FUNCS
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3fc2d0674a..5df97c80fa 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -407,7 +407,6 @@ config XILINX_SPI
 
 config ZYNQ_SPI
 	bool "Zynq SPI driver"
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  Enable the Zynq SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Zynq
@@ -415,7 +414,6 @@ config ZYNQ_SPI
 
 config ZYNQ_QSPI
 	bool "Zynq QSPI driver"
-	depends on ARCH_ZYNQ
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
@@ -425,7 +423,6 @@ config ZYNQ_QSPI
 
 config ZYNQMP_GQSPI
 	bool "Configure ZynqMP Generic QSPI"
-	depends on ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  This option is used to enable ZynqMP QSPI controller driver which
 	  is used to communicate with qspi flash devices.
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..4eb7b34e24 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -200,8 +200,7 @@ config USB_EHCI_TEGRA
 
 config USB_EHCI_ZYNQ
 	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
-	depends on ARCH_ZYNQ
-	default y
+	default y if ARCH_ZYNQ
 	---help---
 	  Enable support for Zynq on-chip EHCI USB controller
 
diff --git a/env/Kconfig b/env/Kconfig
index b59ba310ec..f3a9925f58 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -422,7 +422,7 @@ config ENV_FAT_DEVICE_AND_PART
 	string "Device and partition for where to store the environemt in FAT"
 	depends on ENV_IS_IN_FAT
 	default "0:1" if TI_COMMON_CMD_OPTIONS
-	default "0:auto" if ARCH_ZYNQMP
+	default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP
 	default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
 	default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
 	default "0" if ARCH_AT91
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 6e3953835d..010d28ac86 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -24,7 +24,6 @@
 
 /* No falcon support */
 #undef CONFIG_SPL_OS_BOOT
-#undef CONFIG_SPL_FPGA_SUPPORT
 
 /* FPGA commands that we don't use */
 
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index d7255a05df..8b416327b5 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -94,6 +94,18 @@
 # define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_PXE(func)	func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func)	func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
 #if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
 # define BOOT_TARGET_DEVICES_XSPI(func)	func(XSPI, xspi, 0)
 #else
@@ -135,8 +147,8 @@
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_XSPI(func) \
 	BOOT_TARGET_DEVICES_DFU_USB(func) \
-	func(PXE, pxe, na) \
-	func(DHCP, dhcp, na)
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
 
 #include <config_distro_bootcmd.h>
 
diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h
new file mode 100644
index 0000000000..61f5287d75
--- /dev/null
+++ b/include/dt-bindings/net/mscc-phy-vsc8531.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Device Tree constants for Microsemi VSC8531 PHY
+ *
+ * Author: Nagaraju Lakkaraju
+ *
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#ifndef _DT_BINDINGS_MSCC_VSC8531_H
+#define _DT_BINDINGS_MSCC_VSC8531_H
+
+/* PHY LED Modes */
+#define VSC8531_LINK_ACTIVITY			0
+#define VSC8531_LINK_1000_ACTIVITY		1
+#define VSC8531_LINK_100_ACTIVITY		2
+#define VSC8531_LINK_10_ACTIVITY		3
+#define VSC8531_LINK_100_1000_ACTIVITY		4
+#define VSC8531_LINK_10_1000_ACTIVITY		5
+#define VSC8531_LINK_10_100_ACTIVITY		6
+#define VSC8584_LINK_100FX_1000X_ACTIVITY	7
+#define VSC8531_DUPLEX_COLLISION		8
+#define VSC8531_COLLISION			9
+#define VSC8531_ACTIVITY			10
+#define VSC8584_100FX_1000X_ACTIVITY		11
+#define VSC8531_AUTONEG_FAULT			12
+#define VSC8531_SERIAL_MODE			13
+#define VSC8531_FORCE_LED_OFF			14
+#define VSC8531_FORCE_LED_ON			15
+
+#define VSC8531_RGMII_CLK_DELAY_0_2_NS	0
+#define VSC8531_RGMII_CLK_DELAY_0_8_NS	1
+#define VSC8531_RGMII_CLK_DELAY_1_1_NS	2
+#define VSC8531_RGMII_CLK_DELAY_1_7_NS	3
+#define VSC8531_RGMII_CLK_DELAY_2_0_NS	4
+#define VSC8531_RGMII_CLK_DELAY_2_3_NS	5
+#define VSC8531_RGMII_CLK_DELAY_2_6_NS	6
+#define VSC8531_RGMII_CLK_DELAY_3_4_NS	7
+
+#endif
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index a0a52ec4c1..35cfe17d44 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -10,9 +10,6 @@
 #include <xilinx.h>
 #include <linux/bitops.h>
 
-#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
-#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
-#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS		0xC2000017
 #define ZYNQMP_FPGA_OP_INIT			(1 << 0)
 #define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE			(1 << 2)