Merge tag 'xilinx-for-v2021.01-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblazeWIP/20Nov2020

Xilinx changes for v2021.01-rc3

Microblaze:
- Enable GC
- Get rid of xparameters.h and switch to DT for CFI
- Fix config file

tpm:
- Fix TPM code

zynqmp:
- Enable TPM by default
- Remove unused macros

fru:
- Several fixes especially use limit for recording

11 files changed, 35 insertions, 110 deletions

diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index c5ba42124b..b328837c69 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -134,7 +134,8 @@ struct apu_regs {
 struct csu_regs {
 	u32 reserved0[4];
 	u32 multi_boot;
-	u32 reserved1[12];
+	u32 reserved1[11];
+	u32 idcode;
 	u32 version;
 };
 
@@ -149,7 +150,4 @@ struct pmu_regs {
 
 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
 
-#define ZYNQMP_CSU_IDCODE_ADDR	0xFFCA0040
-#define ZYNQMP_CSU_VER_ADDR	0xFFCA0044
-
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index 96c39b1278..de5b97e719 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -9,6 +9,9 @@
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
 
 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
+PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections
+
+LDFLAGS_FINAL += --gc-sections
 
 ifeq ($(CONFIG_SPL_BUILD),)
 PLATFORM_CPPFLAGS += -fPIC
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index 9282643349..5dc09dbad2 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -14,7 +14,7 @@ SECTIONS
 	{
 		__text_start = .;
 		arch/microblaze/cpu/start.o (.text)
-		*(.text)
+		*(.text*)
 		__text_end = .;
 	}
 
@@ -28,7 +28,7 @@ SECTIONS
 	.data ALIGN(0x4):
 	{
 		__data_start = .;
-		*(.data)
+		*(.data*)
 		__data_end = .;
 	}
 
@@ -51,7 +51,7 @@ SECTIONS
 		__bss_start = .;
 		*(.sbss)
 		*(.scommon)
-		*(.bss)
+		*(.bss*)
 		*(COMMON)
 		. = ALIGN(4);
 		__bss_end = .;
diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h
index a3e6520257..e7284709dd 100644
--- a/board/xilinx/common/fru.h
+++ b/board/xilinx/common/fru.h
@@ -50,12 +50,16 @@ struct fru_board_data {
 	/* Xilinx custom fields */
 	u8 rev_type_len;
 	u8 rev[FRU_BOARD_MAX_LEN];
+	u8 pcie_type_len;
+	u8 pcie[FRU_BOARD_MAX_LEN];
+	u8 uuid_type_len;
+	u8 uuid[FRU_BOARD_MAX_LEN];
 };
 
 struct fru_table {
-	bool captured;
 	struct fru_common_hdr hdr;
 	struct fru_board_data brd;
+	bool captured;
 };
 
 #define FRU_TYPELEN_CODE_MASK	0xC0
diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c
index fc3add7d93..b4cd3d4998 100644
--- a/board/xilinx/common/fru_ops.c
+++ b/board/xilinx/common/fru_ops.c
@@ -163,12 +163,15 @@ static int fru_parse_board(unsigned long addr)
 {
 	u8 i, type;
 	int len;
-	u8 *data, *term;
+	u8 *data, *term, *limit;
 
 	memcpy(&fru_data.brd.ver, (void *)addr, 6);
 	addr += 6;
 	data = (u8 *)&fru_data.brd.manufacturer_type_len;
 
+	/* Record max structure limit not to write data over allocated space */
+	limit = data + sizeof(struct fru_board_data);
+
 	for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) {
 		len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code,
 					 &type);
@@ -178,6 +181,9 @@ static int fru_parse_board(unsigned long addr)
 		if (len == -EINVAL)
 			break;
 
+		/* Stop when amount of chars is more then fields to record */
+		if (data + len > limit)
+			break;
 		/* This record type/len field */
 		*data++ = *(u8 *)addr;
 
@@ -217,7 +223,7 @@ int fru_capture(unsigned long addr)
 
 	hdr = (struct fru_common_hdr *)addr;
 
-	memcpy((void *)&fru_data.hdr, (void *)hdr,
+	memcpy((void *)&fru_data, (void *)hdr,
 	       sizeof(struct fru_common_hdr));
 
 	fru_data.captured = true;
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
deleted file mode 100644
index 5e0911faf6..0000000000
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * CAUTION: This file is a faked configuration !!!
- *          There is no real target for the microblaze-generic
- *          configuration. You have to replace this file with
- *          the generated file from your Xilinx design flow.
- */
-
-/* Microblaze is microblaze_0 */
-#define XILINX_FSL_NUMBER	3
-
-/* Flash Memory is FLASH_2Mx32 */
-#define XILINX_FLASH_START	0x2c000000
-#define XILINX_FLASH_SIZE	0x00800000
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 08c88856dc..761cc65cbf 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -48,8 +48,10 @@ CONFIG_DM_I2C=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 0c816de707..bac8117c51 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -57,6 +57,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_TPM=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_MTDPARTS_SPREAD=y
@@ -137,6 +138,7 @@ CONFIG_ZYNQ_SERIAL=y
 CONFIG_SPI=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_TPM2_TIS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
@@ -156,5 +158,6 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_WDT=y
 CONFIG_WDT_CDNS=y
 CONFIG_PANIC_HANG=y
+CONFIG_TPM=y
 CONFIG_SPL_GZIP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 9a8145e6ba..0045bedf0c 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -30,8 +30,6 @@
 #include "tpm_tis.h"
 #include "tpm_internal.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define TPM_ACCESS(l)			(0x0000 | ((l) << 12))
 #define TPM_INT_ENABLE(l)               (0x0008 | ((l) << 12))
 #define TPM_STS(l)			(0x0018 | ((l) << 12))
@@ -520,7 +518,6 @@ static int tpm_tis_spi_cleanup(struct udevice *dev)
 static int tpm_tis_spi_open(struct udevice *dev)
 {
 	struct tpm_chip *chip = dev_get_priv(dev);
-	struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
 
 	if (chip->is_open)
 		return -EBUSY;
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 2b41242350..bc0bf04973 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -8,24 +8,14 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include "../board/xilinx/microblaze-generic/xparameters.h"
+/* Microblaze is microblaze_0 */
+#define XILINX_FSL_NUMBER	3
 
 /* MicroBlaze CPU */
 #define	MICROBLAZE_V5		1
 
 #define CONFIG_SYS_BOOTM_LEN	(64 * 1024 * 1024)
 
-/* linear and spi flash memory */
-#ifdef XILINX_FLASH_START
-#define	FLASH
-#undef	SPIFLASH
-#undef	RAMENV	/* hold environment in flash */
-#else
-#undef	FLASH
-#undef	SPIFLASH
-#define	RAMENV	/* hold environment in RAM */
-#endif
-
 /* uart */
 /* The following table includes the supported baudrates */
 # define CONFIG_SYS_BAUDRATE_TABLE \
@@ -40,67 +30,17 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
 					 CONFIG_SYS_MALLOC_F_LEN)
 
-/*
- * CFI flash memory layout - Example
- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
- *
- * SECT_SIZE = 0x20000;			128kB is one sector
- * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
- *
- * 0x2200_0000	CONFIG_SYS_FLASH_BASE
- *					FREE		256kB
- * 0x2204_0000	CONFIG_ENV_ADDR
- *					ENV_AREA	128kB
- * 0x2206_0000
- *					FREE
- * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
- *
- */
-
-#ifdef FLASH
-# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
-# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
+#ifdef CONFIG_CFI_FLASH
 /* ?empty sector */
 # define CONFIG_SYS_FLASH_EMPTY_INFO	1
 /* max number of memory banks */
 # define CONFIG_SYS_MAX_FLASH_BANKS	1
 /* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT	512
-/* hardware flash protection */
-/* use buffered writes (20x faster) */
-# ifdef	RAMENV
-# else	/* FLASH && !RAMENV */
-/* 128K(one sector) for env */
-# endif /* FLASH && !RAMBOOT */
-#else /* !FLASH */
-
-#ifdef SPIFLASH
-# ifdef	RAMENV
-# else	/* SPIFLASH && !RAMENV */
-/* 128K(two sectors) for env */
-/* Warning: adjust the offset in respect of other flash content and size */
-# endif /* SPIFLASH && !RAMBOOT */
-#else /* !SPIFLASH */
-
-/* ENV in RAM */
-#endif /* !SPIFLASH */
-#endif /* !FLASH */
-
-#define XILINX_USE_ICACHE 1
-#define XILINX_USE_DCACHE 1
-
-#if defined(XILINX_USE_ICACHE)
-# define CONFIG_ICACHE
-#else
-# undef CONFIG_ICACHE
+# define CONFIG_SYS_MAX_FLASH_SECT	2048
 #endif
 
-#if defined(XILINX_USE_DCACHE)
-# define CONFIG_DCACHE
-#else
-# undef CONFIG_DCACHE
-#endif
+#define CONFIG_ICACHE
+#define CONFIG_DCACHE
 
 #ifndef XILINX_DCACHE_BYTE_SIZE
 #define XILINX_DCACHE_BYTE_SIZE	32768
@@ -111,12 +51,6 @@
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-#if defined(CONFIG_MTD_PARTITIONS)
-/* MTD partitions */
-
-/* default mtd partition table */
-#endif
-
 /* size of console buffer */
 #define	CONFIG_SYS_CBSIZE	512
 /* max number of command args */
@@ -194,15 +128,12 @@
 
 /* SPL part */
 
-#ifdef CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
-#endif
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
 
 /* for booting directly linux */
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_TEXT_BASE + \
+					0x40000)
 
-#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
-					 0x40000)
-#define CONFIG_SYS_FDT_SIZE		(16 << 10)
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
 					 0x1000000)
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0aabe7a451..8b4fcba395 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2170,7 +2170,6 @@ CONFIG_SYS_FCC_PSMR
 CONFIG_SYS_FDT_BASE
 CONFIG_SYS_FDT_LOAD_ADDR
 CONFIG_SYS_FDT_PAD
-CONFIG_SYS_FDT_SIZE
 CONFIG_SYS_FEC0_IOBASE
 CONFIG_SYS_FEC1_IOBASE
 CONFIG_SYS_FECI2C