ppc: Remove MPC8569MDS boardWIP/2021-02-25-remove-platforms

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is the last ARCH_MPC8569 board, remove that support
as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

21 files changed, 4 insertions, 1738 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 870ab800e8..6f90518927 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -64,10 +64,6 @@ config TARGET_MPC8568MDS
 	bool "Support MPC8568MDS"
 	select ARCH_MPC8568
 
-config TARGET_MPC8569MDS
-	bool "Support MPC8569MDS"
-	select ARCH_MPC8569
-
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
 	select ARCH_P1010
@@ -473,19 +469,6 @@ config ARCH_MPC8568
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 
-config ARCH_MPC8569
-	bool
-	select FSL_LAW
-	select SYS_FSL_ERRATUM_A004508
-	select SYS_FSL_ERRATUM_A005125
-	select FSL_PCIE_RESET
-	select SYS_FSL_HAS_DDR3
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_BE
-	select SYS_FSL_SEC_COMPAT_2
-	select FSL_ELBC
-	imply CMD_NAND
-
 config ARCH_MPC8572
 	bool
 	select FSL_LAW
@@ -1102,7 +1085,6 @@ config SYS_CCSRBAR_DEFAULT
 				ARCH_MPC8555	|| \
 				ARCH_MPC8560	|| \
 				ARCH_MPC8568	|| \
-				ARCH_MPC8569	|| \
 				ARCH_MPC8572	|| \
 				ARCH_P1010	|| \
 				ARCH_P1011	|| \
@@ -1335,8 +1317,7 @@ config SYS_FSL_NUM_LAWS
 			ARCH_P2020
 	default 10 if	ARCH_MPC8544	|| \
 			ARCH_MPC8548	|| \
-			ARCH_MPC8568	|| \
-			ARCH_MPC8569
+			ARCH_MPC8568
 	default 8 if	ARCH_MPC8540	|| \
 			ARCH_MPC8541	|| \
 			ARCH_MPC8555	|| \
@@ -1433,7 +1414,6 @@ source "board/freescale/mpc8541cds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
-source "board/freescale/mpc8569mds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 019fce6314..14e46626f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -65,7 +65,6 @@ obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
 obj-$(CONFIG_ARCH_P1010)	+= p1010_serdes.o
 obj-$(CONFIG_ARCH_P1011)	+= p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
deleted file mode 100644
index eb54b8252b..0000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES		4
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
-	[0x0] = {PCIE1, NONE, NONE, NONE},
-	[0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
-	[0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
-	[0x3] = {SRIO1, SRIO2, NONE, NONE},
-	[0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
-	[0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
-	[0x6] = {PCIE1, NONE, SRIO1, SRIO2},
-	[0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
-	[0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
-	[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
-	[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
-	if (!(serdes1_prtcl_map & (1 << NONE)))
-		fsl_serdes_init();
-
-	return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-	int lane;
-
-	if (serdes1_prtcl_map & (1 << NONE))
-		return;
-
-	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
-	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
-		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
-		return;
-	}
-
-	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
-		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
-		serdes1_prtcl_map |= (1 << lane_prtcl);
-	}
-
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 09653c7012..9c89ce5d70 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -630,7 +630,7 @@ int get_clocks(void)
 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
+#if defined(CONFIG_ARCH_P1010)
 	gd->arch.sdhc_clk = gd->bus_clk;
 #else
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index dd784e7e30..f41e82ad18 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -344,39 +344,6 @@ l2_disabled:
 	mtspr	DBCR0,r0
 #endif
 
-#ifdef CONFIG_ARCH_MPC8569
-#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
-#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
-
-	/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
-	 * use address space which is more than 12bits, and it must be done in
-	 * the 4K boot page. So we set this bit here.
-	 */
-
-	/* create a temp mapping TLB0[0] for LBCR  */
-	create_tlb0_entry 0, \
-		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
-		CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
-		0, r6
-
-	/* Set LBCR register */
-	lis     r4,CONFIG_SYS_LBCR_ADDR@h
-	ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
-
-	lis     r5,CONFIG_SYS_LBC_LBCR@h
-	ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
-	stw     r5,0(r4)
-	isync
-
-	/* invalidate this temp TLB */
-	lis	r4,CONFIG_SYS_LBC_ADDR@h
-	ori	r4,r4,CONFIG_SYS_LBC_ADDR@l
-	tlbivax	0,r4
-	isync
-
-#endif /* CONFIG_ARCH_MPC8569 */
-
 /*
  * Search for the TLB that covers the code we're executing, and shrink it
  * so that it covers only this 4K page.  That will ensure that any other
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f25ba1af09..4d70259f09 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -38,16 +38,6 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
-#elif defined(CONFIG_ARCH_MPC8569)
-#define QE_MURAM_SIZE			0x20000UL
-#define MAX_QE_RISC			4
-#define QE_NUM_OF_SNUM			46
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_RMU
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
-
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index bfa601e91b..c6c009261d 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2204,15 +2204,8 @@ typedef struct ccsr_gur {
 	u32	gpiocr;		/* GPIO control */
 #endif
 	u8	res3[12];
-#if defined(CONFIG_ARCH_MPC8569)
-	u32	plppar1;	/* Platform port pin assignment 1 */
-	u32	plppar2;	/* Platform port pin assignment 2 */
-	u32	plpdir1;	/* Platform port pin direction 1 */
-	u32	plpdir2;	/* Platform port pin direction 2 */
-#else
 	u32	gpoutdr;	/* General-purpose output data */
 	u8	res4[12];
-#endif
 	u32	gpindr;		/* General-purpose input data */
 	u8	res5[12];
 	u32	pmuxcr;		/* Alt. function signal multiplex control */
@@ -2478,7 +2471,7 @@ typedef struct ccsr_gur {
 	u32	svr;		/* System version */
 	u8	res10[8];
 	u32	rstcr;		/* Reset control */
-#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568)
 	u8	res11a[76];
 	par_io_t qe_par_io[7];
 	u8	res11b[1600];
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index ae66039857..596cd0018c 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,20 +63,7 @@ int pib_init(void)
 #endif
 
 #if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_TARGET_MPC8569MDS)
-	val8 = 0;
-	i2c_write(0x20, 0x6, 1, &val8, 1);
-	i2c_write(0x20, 0x7, 1, &val8, 1);
-
-	val8 = 0xdf;
-	i2c_write(0x20, 0x2, 1, &val8, 1);
-	val8 = 0xf7;
-	i2c_write(0x20, 0x3, 1, &val8, 1);
-
-	eieio();
-
-	printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_TARGET_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
 	val8 = 0;
 	i2c_write(0x26, 0x7, 1, &val8, 1);
 	val8 = 0xf7;
diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig
deleted file mode 100644
index 48718575ff..0000000000
--- a/board/freescale/mpc8569mds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8569MDS
-
-config SYS_BOARD
-	default "mpc8569mds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8569MDS"
-
-endif
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
deleted file mode 100644
index 9df3f3cca8..0000000000
--- a/board/freescale/mpc8569mds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8569MDS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8569mds/
-F:	include/configs/MPC8569MDS.h
-F:	configs/MPC8569MDS_defconfig
-F:	configs/MPC8569MDS_ATM_defconfig
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
deleted file mode 100644
index 45718dfdae..0000000000
--- a/board/freescale/mpc8569mds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004-2009 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8569mds.o
-obj-y	+= bcsr.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README
deleted file mode 100644
index 86c3ccde79..0000000000
--- a/board/freescale/mpc8569mds/README
+++ /dev/null
@@ -1,77 +0,0 @@
-Overview
---------
-MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
-I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
-
-Building U-Boot
------------
-	make MPC8569MDS_config
-	make
-
-Memory Map
-----------
-0x0000_0000   0x7fff_ffff     DDR                     2G
-0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
-0xe000_0000   0xe00f_ffff     CCSRBAR                 1M
-0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
-0xc000_0000   0xdfff_ffff     SRIO                    512MB
-0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
-0xf800_0000   0xf800_7fff     BCSR                    32KB
-0xf800_8000   0xf800_ffff     PIB (CS4)               32KB
-0xf801_0000   0xf801_7fff     PIB (CS5)               32KB
-0xfe00_0000   0xffff_ffff     Flash                   32MB
-
-
-Flashing U-Boot Images
----------------
-
-Use the following commands to program U-Boot image into flash:
-
-	=> tftp 1000000 u-boot.bin
-	=> protect off all
-	=> erase fff80000 ffffffff
-	=> cp.b 1000000 fff80000 80000
-
-
-Setting the correct MAC addresses
------------------------
-The command - "mac", is introduced to set on-board system EEPROM in the format
-defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
-addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
-we first get the board. The commands are as follows:
-	=> mac i NXID	/* Set NXID to this EEPROM */
-	=> mac e 01	/* Set Errata, this value is not defined by hardware
-			   designer, we can set whatever we want */
-	=> mac n a0	/* Set Serial Number. This is not defined by hardware
-			   designer, we can set whatever we want */
-	=> mac date 090512080000  /* Set the date in YYMMDDhhmmss format */
-
-	=> mac p 8	/* Set the number of mac ports, it should be 8 */
-	=> mac 0 xx:xx:xx:xx:xx:xx  /* xx:xx:xx:xx:xx:xx should be the real mac
-				       address, you can refer to the value on
-				       the sticker of the rear side of the board
-				     */
-	.....
-	=> mac 7 xx:xx:xx:xx:xx:xx
-	=> mac read
-	=> mac save
-
-After resetting the board, the ethxaddrs will be filled with the mac addresses
-if such environment variables are blank(never been set before). If the ethxaddr
-has been set but we want to update it, we can use the following commands:
-	=> setenv ethxaddr	/* x = "none",1,2,3,4,5,6,7 */
-	=> save
-	=> reset
-
-
-Programming the ucode to flash
----------------------------------
-MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
-IRAM so that the QE can work. The ucode binary can be downloaded from
-http://opensource.freescale.com/firmware/, and it must be programmed to
-the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
-hangs at "Net:"
-
-
-Please note the above two steps(setting mac addresses and programming ucode) are
-very important to get the board booting up and working properly.
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
deleted file mode 100644
index 9ed00f6e5b..0000000000
--- a/board/freescale/mpc8569mds/bcsr.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-#include "bcsr.h"
-
-void enable_8569mds_flash_write(void)
-{
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
-}
-
-void disable_8569mds_flash_write(void)
-{
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
-}
-
-void enable_8569mds_qe_uec(void)
-{
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
-			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
-			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
-			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
-			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-	/* Set UCC1-4 working at RMII mode */
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
-			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
-			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
-			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
-			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
-	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
-#endif
-}
-
-void disable_8569mds_brd_eeprom_write_protect(void)
-{
-	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
-}
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
deleted file mode 100644
index fee0fe7dbc..0000000000
--- a/board/freescale/mpc8569mds/bcsr.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __BCSR_H_
-#define __BCSR_H_
-
-#include <common.h>
-
-/* BCSR Bit definitions*/
-/****************************************/
-/* BCSR defines                         */
-/****************************************/
-#define BCSR6_UPC1_EN		0x80
-#define BCSR6_UPC1_POS_EN	0x40
-#define BCSR6_UPC1_ADDR_EN	0x20
-#define BCSR6_UPC1_DEV2		0x10
-#define BCSR6_SD_CARD_1BIT	0x08
-#define BCSR6_SD_CARD_4BITS	0x04
-#define BCSR6_TDM2G_EN		0x02
-#define BCSR6_UCC7_RMII_EN	0x01
-
-#define BCSR7_UCC1_GETH_EN	0x80
-#define BCSR7_UCC1_RGMII_EN	0x40
-#define BCSR7_UCC1_RTBI_EN	0x20
-#define BCSR7_GETHRST_MRVL	0x04
-#define BCSR7_BRD_WRT_PROTECT	0x02
-
-#define BCSR8_UCC2_GETH_EN	0x80
-#define BCSR8_UCC2_RGMII_EN	0x40
-#define BCSR8_UCC2_RTBI_EN	0x20
-#define BCSR8_UEM_MARVEL_RESET	0x02
-
-#define BCSR9_UCC3_GETH_EN	0x80
-#define BCSR9_UCC3_RGMII_EN	0x40
-#define BCSR9_UCC3_RTBI_EN	0x20
-#define BCSR9_UCC3_RMII_EN	0x10
-#define BCSR9_UCC3_UEM_MICREL	0x01
-
-#define BCSR10_UCC4_GETH_EN	0x80
-#define BCSR10_UCC4_RGMII_EN	0x40
-#define BCSR10_UCC4_RTBI_EN	0x20
-
-#define BCSR11_LED0		0x40
-#define BCSR11_LED1		0x20
-#define BCSR11_LED2		0x10
-
-#define BCSR12_UCC6_RMII_EN	0x20
-#define BCSR12_UCC8_RMII_EN	0x20
-
-#define BCSR15_SMII6_DIS	0x08
-#define BCSR15_SMII8_DIS	0x04
-#define BCSR15_QEUART_EN	0x01
-
-#define BCSR16_UPC1_DEV2	0x02
-
-#define BCSR17_nUSBEN		0x80
-#define BCSR17_nUSBLOWSPD	0x40
-#define BCSR17_USBVCC		0x20
-#define BCSR17_USBMODE		0x10
-#define BCSR17_FLASH_nWP	0x01
-
-/*BCSR Utils functions*/
-
-void enable_8569mds_flash_write(void);
-void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_uec(void);
-void disable_8569mds_brd_eeprom_write_protect(void);
-
-#endif	/* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
deleted file mode 100644
index d049611e64..0000000000
--- a/board/freescale/mpc8569mds/ddr.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 4;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0xff;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 2;
-
-	/*
-	 * Enable half drive strength
-	 */
-	popts->half_strength_driver_enable = 1;
-
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xa;
-	popts->wrlvl_start = 0x4;
-
-	/* Rtt and Rtt_W override */
-	popts->rtt_override = 1;
-	popts->rtt_override_value = DDR3_RTT_60_OHM;
-	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
-}
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
deleted file mode 100644
index 35cdd75d6e..0000000000
--- a/board/freescale/mpc8569mds/law.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
- *1)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
- *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
- *2)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
- *3)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
- *4.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
- *4.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
- *4.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
- *4.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
- *4.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
- *
- *Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
deleted file mode 100644
index 1d2cffbacd..0000000000
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ /dev/null
@@ -1,590 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2010 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <console.h>
-#include <flash.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <ioports.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <phy.h>
-
-#include "bcsr.h"
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* QE_MUX_MDC */
-	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
-
-	/* QE_MUX_MDIO */
-	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
-
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-	/* UCC_1_RGMII */
-	{2, 11, 2, 0, 1}, /* CLK12 */
-	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
-	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
-	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
-	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
-	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
-	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
-	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
-	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
-	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
-	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
-	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
-	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
-
-	/* UCC_2_RGMII */
-	{2, 16, 2, 0, 3}, /* CLK17 */
-	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
-	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
-	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
-	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
-	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
-	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
-	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
-	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
-	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
-	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
-	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
-	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
-
-	/* UCC_3_RGMII */
-	{2, 11, 2, 0, 1}, /* CLK12 */
-	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
-	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
-	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
-	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
-	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
-	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
-	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
-	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
-	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
-	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
-	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
-	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
-
-	/* UCC_4_RGMII */
-	{2, 16, 2, 0, 3}, /* CLK17 */
-	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
-	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
-	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
-	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
-	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
-	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
-	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
-	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
-	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
-	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
-	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
-	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
-
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-	/* UCC_1_RMII */
-	{2, 15, 2, 0, 1}, /* CLK16 */
-	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
-	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
-	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
-	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
-	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
-	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
-
-	/* UCC_2_RMII */
-	{2, 15, 2, 0, 1}, /* CLK16 */
-	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
-	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
-	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
-	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
-	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
-	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
-
-	/* UCC_3_RMII */
-	{2, 15, 2, 0, 1}, /* CLK16 */
-	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
-	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
-	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
-	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
-	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
-	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
-
-	/* UCC_4_RMII */
-	{2, 15, 2, 0, 1}, /* CLK16 */
-	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
-	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
-	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
-	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
-	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
-	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
-#endif
-
-	/* UART1 is muxed with QE PortF bit [9-12].*/
-	{5, 12, 2, 0, 3}, /* UART1_SIN */
-	{5, 9,  1, 0, 3}, /* UART1_SOUT */
-	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
-	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
-
-	/* QE UART                                     */
-	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
-	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
-	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
-	{1, 23, 2, 0, 1}, /* QEUART_CTS                */
-
-	/* QE USB                                      */
-	{5,  3, 1, 0, 1}, /* USB_OE                    */
-	{5,  4, 1, 0, 2}, /* USB_TP                    */
-	{5,  5, 1, 0, 2}, /* USB_TN                    */
-	{5,  6, 2, 0, 2}, /* USB_RP                    */
-	{5,  7, 2, 0, 1}, /* USB_RX                    */
-	{5,  8, 2, 0, 1}, /* USB_RN                    */
-	{2,  4, 2, 0, 2}, /* CLK5                      */
-
-	/* SPI Flash, M25P40                           */
-	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
-	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
-	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
-	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	enable_8569mds_flash_write();
-
-#ifdef CONFIG_QE
-	enable_8569mds_qe_uec();
-#endif
-
-#if CONFIG_SYS_I2C2_OFFSET
-	/* Enable I2C2 signals instead of SD signals */
-	volatile struct ccsr_gur *gur;
-	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
-	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
-	gur->plppar1 |= PLPPAR1_I2C2_VAL;
-	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
-	gur->plpdir1 |= PLPDIR1_I2C2_VAL;
-
-	disable_8569mds_brd_eeprom_write_protect();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
-	const u8 flash_esel = 0;
-
-	/*
-	 * Remap Boot flash to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* invalidate existing TLB entry for flash */
-	disable_tlb(flash_esel);
-
-	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
-		0, flash_esel,				/* ts, esel */
-		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	printf ("Board: 8569 MDS\n");
-
-	return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-phys_size_t fixed_sdram(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-	uint d_init;
-
-	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
-	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
-	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
-	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
-	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
-	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
-	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
-	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
-	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
-	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
-	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
-	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
-#if defined (CONFIG_DDR_ECC)
-	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
-	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
-	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
-#endif
-	udelay(500);
-
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
-		udelay(1000);
-	}
-	debug("DDR: memory initialized\n\n");
-	udelay(500);
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	sys_info_t sysinfo;
-
-	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
-	out_be32(&gur->lbiuiplldcr1, 0x00078080);
-	if (clkdiv == 16)
-		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
-	else if (clkdiv == 8)
-		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
-	else if (clkdiv == 4)
-		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
-
-	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
-}
-
-static void fdt_board_disable_serial(void *blob, struct bd_info *bd,
-				     const char *alias)
-{
-	const char *status = "disabled";
-	int off;
-	int err;
-
-	off = fdt_path_offset(blob, alias);
-	if (off < 0) {
-		printf("WARNING: could not find %s alias: %s.\n", alias,
-			fdt_strerror(off));
-		return;
-	}
-
-	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
-	if (err) {
-		printf("WARNING: could not set status for serial0: %s.\n",
-			fdt_strerror(err));
-		return;
-	}
-}
-
-/*
- * Because of an erratum in prototype boards it is impossible to use eSDHC
- * without disabling UART0 (which makes it quite easy to 'brick' the board
- * by simply issung 'setenv hwconfig esdhc', and not able to interact with
- * U-Boot anylonger).
- *
- * So, but default we assume that the board is a prototype, which is a most
- * safe assumption. There is no way to determine board revision from a
- * register, so we use hwconfig.
- */
-
-static int prototype_board(void)
-{
-	if (hwconfig_subarg("board", "rev", NULL))
-		return hwconfig_subarg_cmp("board", "rev", "prototype");
-	return 1;
-}
-
-static int esdhc_disables_uart0(void)
-{
-	return prototype_board() ||
-	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
-}
-
-static void fdt_board_fixup_qe_uart(void *blob, struct bd_info *bd)
-{
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
-	const char *devtype = "serial";
-	const char *compat = "ucc_uart";
-	const char *clk = "brg9";
-	u32 portnum = 0;
-	int off = -1;
-
-	if (!hwconfig("qe_uart"))
-		return;
-
-	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
-		printf("QE UART: won't enable with esdhc.\n");
-		return;
-	}
-
-	fdt_board_disable_serial(blob, bd, "serial1");
-
-	while (1) {
-		const u32 *idx;
-		int len;
-
-		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
-		if (off < 0) {
-			printf("WARNING: unable to fixup device tree for "
-				"QE UART\n");
-			return;
-		}
-
-		idx = fdt_getprop(blob, off, "cell-index", &len);
-		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
-			continue;
-		break;
-	}
-
-	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
-	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
-	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
-	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
-	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
-
-	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-
-int board_mmc_init(struct bd_info *bd)
-{
-	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
-	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
-
-	if (!hwconfig("esdhc"))
-		return 0;
-
-	printf("Enabling eSDHC...\n"
-	       "  For eSDHC to function, I2C2 ");
-	if (esdhc_disables_uart0()) {
-		printf("and UART0 should be disabled.\n");
-		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
-		console_assign(stderr, "eserial1");
-		console_assign(stdout, "eserial1");
-		console_assign(stdin, "eserial1");
-		printf("Switched to UART1 (initial log has been printed to "
-		       "UART0).\n");
-
-		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
-					       PLPPAR1_ESDHC_4BITS_VAL);
-		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
-					       PLPDIR1_ESDHC_4BITS_VAL);
-		bcsr6 |= BCSR6_SD_CARD_4BITS;
-	} else {
-		printf("should be disabled.\n");
-	}
-
-	/* Assign I2C2 signals to eSDHC. */
-	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
-				       PLPPAR1_ESDHC_VAL);
-	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
-				       PLPDIR1_ESDHC_VAL);
-
-	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
-	setbits_8(&bcsr[6], bcsr6);
-
-	return fsl_esdhc_mmc_init(bd);
-}
-
-static void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd)
-{
-	const char *status = "disabled";
-	int off = -1;
-
-	if (!hwconfig("esdhc"))
-		return;
-
-	if (esdhc_disables_uart0())
-		fdt_board_disable_serial(blob, bd, "serial0");
-
-	while (1) {
-		const u32 *idx;
-		int len;
-
-		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
-		if (off < 0)
-			break;
-
-		idx = fdt_getprop(blob, off, "cell-index", &len);
-		if (!idx || len != sizeof(*idx))
-			continue;
-
-		if (*idx == 1) {
-			fdt_setprop(blob, off, "status", status,
-				    strlen(status) + 1);
-			break;
-		}
-	}
-
-	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
-		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
-		if (off < 0) {
-			printf("WARNING: could not find esdhc node\n");
-			return;
-		}
-		fdt_delprop(blob, off, "sdhci,1-bit-only");
-	}
-}
-#else
-static inline void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) {}
-#endif
-
-static void fdt_board_fixup_qe_usb(void *blob, struct bd_info *bd)
-{
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
-
-	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
-		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
-	else
-		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
-
-	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
-		clrbits_8(&bcsr[17], BCSR17_USBVCC);
-		clrbits_8(&bcsr[17], BCSR17_USBMODE);
-		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
-				   "peripheral", sizeof("peripheral"), 1);
-	} else {
-		setbits_8(&bcsr[17], BCSR17_USBVCC);
-		setbits_8(&bcsr[17], BCSR17_USBMODE);
-	}
-
-	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-#if defined(CONFIG_PQ_MDS_PIB)
-	pib_init();
-#endif
-
-	fsl_pcie_init_board(0);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#if defined(CONFIG_SYS_UCC_RMII_MODE)
-	int nodeoff, off, err;
-	unsigned int val;
-	const u32 *ph;
-	const u32 *index;
-
-	/* fixup device tree for supporting rmii mode */
-	nodeoff = -1;
-	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
-				"ucc_geth")) >= 0) {
-		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
-						"clk16");
-		if (err < 0) {
-			printf("WARNING: could not set tx-clock-name %s.\n",
-				fdt_strerror(err));
-			break;
-		}
-
-		err = fdt_fixup_phy_connection(blob, nodeoff,
-				PHY_INTERFACE_MODE_RMII);
-
-		if (err < 0) {
-			printf("WARNING: could not set phy-connection-type "
-				"%s.\n", fdt_strerror(err));
-			break;
-		}
-
-		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
-		if (index == NULL) {
-			printf("WARNING: could not get cell-index of ucc\n");
-			break;
-		}
-
-		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
-		if (ph == NULL) {
-			printf("WARNING: could not get phy-handle of ucc\n");
-			break;
-		}
-
-		off = fdt_node_offset_by_phandle(blob, *ph);
-		if (off < 0) {
-			printf("WARNING: could not get phy node	%s.\n",
-				fdt_strerror(err));
-			break;
-		}
-
-		val = 0x7 + *index; /* RMII phy address starts from 0x8 */
-
-		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
-		if (err < 0) {
-			printf("WARNING: could not set reg for phy-handle "
-				"%s.\n", fdt_strerror(err));
-			break;
-		}
-	}
-#endif
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	fdt_board_fixup_esdhc(blob, bd);
-	fdt_board_fixup_qe_uart(blob, bd);
-	fdt_board_fixup_qe_usb(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
deleted file mode 100644
index fdbac54984..0000000000
--- a/board/freescale/mpc8569mds/tlb.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 Initializations */
-	/*
-	 * TLBe 0:	64M	write-through, guarded
-	 * Out of reset this entry is only 4K.
-	 * 0xfc000000	32MB	NAND FLASH (CS3)
-	 * 0xfe000000	32MB	NOR FLASH (CS0)
-	 */
-#ifdef CONFIG_NAND_SPL
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
-#endif
-	/*
-	 * TLBe 1:	256KB	Non-cacheable, guarded
-	 * 0xf8000000	32K	BCSR
-	 * 0xf8008000	32K	PIB (CS4)
-	 * 0xf8010000	32K	PIB (CS5)
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256K, 1),
-
-	/*
-	 * TLBe 2:	256M	Non-cacheable, guarded
-	 * 0xa00000000	256M	PCIe MEM (lower half)
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLBe 3:	256M	Non-cacheable, guarded
-	 * 0xb00000000	256M	PCIe MEM (higher half)
-	 */
-	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
-		      (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLBe 4:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe280_0000	8M	PCIe IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
deleted file mode 100644
index b1f4789a92..0000000000
--- a/configs/MPC8569MDS_ATM_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8569MDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="ATM"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_E1000=y
-CONFIG_QE=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
deleted file mode 100644
index 1f0f3dcceb..0000000000
--- a/configs/MPC8569MDS_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8569MDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_E1000=y
-CONFIG_QE=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
deleted file mode 100644
index f50f53ec3f..0000000000
--- a/include/configs/MPC8569MDS.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8569mds board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
-#define CONFIG_PCIE1		1	/* PCIE controller */
-#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-/* Replace a call to get_clock_freq (after it is implemented)*/
-#define CONFIG_SYS_CLK_FREQ	66666666
-#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
-
-#ifdef CONFIG_ATM
-#define CONFIG_PQ_MDS_PIB
-#define CONFIG_PQ_MDS_PIB_ATM
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
-#define CONFIG_BTB				/* toggle branch predition */
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-#define CONFIG_HWCONFIG
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE		(512 << 10)
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-					/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
-#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
-#define CONFIG_SYS_DDR_TIMING_3         0x00020000
-#define CONFIG_SYS_DDR_TIMING_0         0x00330004
-#define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
-#define CONFIG_SYS_DDR_TIMING_2         0x002888D0
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
-#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
-#define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
-#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
-#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
-#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
-#define CONFIG_SYS_DDR_TIMING_4         0x00220001
-#define CONFIG_SYS_DDR_TIMING_5         0x03402400
-#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
-#define CONFIG_SYS_DDR_CDR_1		0x80040000
-#define CONFIG_SYS_DDR_CDR_2		0x00000000
-#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
-#define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL2         0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
-#define CONFIG_SYS_DDR_SBE              0x00010000
-
-/*
- * Local Bus Definitions
- */
-
-#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_BCSR_BASE		0xf8000000
-#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
-
-/*Chip select 0 - Flash*/
-#define CONFIG_FLASH_BR_PRELIM		0xfe000801
-#define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
-
-/*Chip select 1 - BCSR*/
-#define CONFIG_SYS_BR1_PRELIM		0xf8000801
-#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
-
-/*Chip select 4 - PIB*/
-#define CONFIG_SYS_BR4_PRELIM		0xf8008801
-#define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
-
-/*Chip select 5 - PIB*/
-#define CONFIG_SYS_BR5_PRELIM		0xf8010801
-#define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Chip select 3 - NAND */
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE		0xFC000000
-#else
-#define CONFIG_SYS_NAND_BASE		0xFFF00000
-#endif
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
-	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_NAND_FSL_ELBC		1
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
-				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
-				| BR_PS_8	     /* Port Size = 8 bit */ \
-				| BR_MS_FCM	     /* MSEL = FCM */ \
-				| BR_V)		     /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
-				| OR_FCM_CSCT \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
-#define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#define CONFIG_SYS_EEPROM_BUS_NUM       1
-
-#define PLPPAR1_I2C_BIT_MASK		0x0000000F
-#define PLPPAR1_I2C2_VAL		0x00000000
-#define PLPPAR1_ESDHC_VAL		0x0000000A
-#define PLPDIR1_I2C_BIT_MASK		0x0000000F
-#define PLPDIR1_I2C2_VAL		0x0000000F
-#define PLPDIR1_ESDHC_VAL		0x00000006
-#define PLPPAR1_UART0_BIT_MASK		0x00000fc0
-#define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
-#define PLPDIR1_UART0_BIT_MASK		0x00000fc0
-#define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
-
-/*
- * General PCI
- * Memory Addresses are mapped 1-1. I/O is mapped from 0
- */
-#define CONFIG_SYS_PCIE1_NAME		"Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
-
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
-
-#ifdef CONFIG_QE
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
-#undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
-
-#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME         "UEC0"
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1         /* GETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
-#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
-#define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH2         /* GETH2 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
-#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
-#define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH2 */
-
-#define CONFIG_UEC_ETH3         /* GETH3 */
-#define CONFIG_HAS_ETH2
-
-#ifdef CONFIG_UEC_ETH3
-#define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
-#define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
-#define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR       2
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
-#define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH3 */
-
-#define CONFIG_UEC_ETH4         /* GETH4 */
-#define CONFIG_HAS_ETH3
-
-#ifdef CONFIG_UEC_ETH4
-#define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
-#define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
-#define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR       3
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
-#define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH4 */
-
-#undef CONFIG_UEC_ETH6         /* GETH6 */
-#define CONFIG_HAS_ETH5
-
-#ifdef CONFIG_UEC_ETH6
-#define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
-#define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
-#define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
-#define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC6_PHY_ADDR       4
-#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH6 */
-
-#undef CONFIG_UEC_ETH8         /* GETH8 */
-#define CONFIG_HAS_ETH7
-
-#ifdef CONFIG_UEC_ETH8
-#define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
-#define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
-#define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
-#define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
-#define CONFIG_SYS_UEC8_PHY_ADDR       6
-#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH8 */
-
-#endif /* CONFIG_QE */
-
-#if defined(CONFIG_PCI)
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif	/* CONFIG_PCI */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-						/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "mpc8569mds"
-#define CONFIG_ROOTPATH  "/nfsroot"
-#define CONFIG_BOOTFILE  "your.uImage"
-
-#define CONFIG_SERVERIP  192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK   255.255.255.0
-
-#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=600000\0"						\
-	"ramdiskfile=your.ramdisk.u-boot\0"				\
-	"fdtaddr=400000\0"						\
-	"fdtfile=your.fdt.dtb\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-	"nfsroot=$serverip:$rootpath "					\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw "			\
-	"console=$consoledev,$baudrate $othbootargs\0"			\
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"run nfsargs;"							\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"run ramargs;"							\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */