diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2021-01-12 13:44:11 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-18 15:23:06 -0500 |
| commit | ac7a51c0e48f2aa81ae20caf8d6b9fad976675cd (patch) | |
| tree | 912603265aac7ae1fb843c02986dbbb0835b7060 | |
| parent | 63779b240711cb1a0761bbceb323f5e9558394cc (diff) | |
| download | u-boot-WIP/2021-01-18-assorted-platform-updates.tar.gz | |
dts: mt7622: use accurate clock source fot mtk_timerWIP/2021-01-18-assorted-platform-updates
The input system clock for mt7622 timer is 10MHz and can be retrieved
through the clk driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| -rw-r--r-- | arch/arm/dts/mt7622.dtsi | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index d888545809..5c2e0251de 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -71,16 +71,10 @@ compatible = "mediatek,timer"; reg = <0x10004000 0x80>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_APXGPT_PD>; clock-names = "system-clk"; }; - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - infracfg: infracfg@10000000 { compatible = "mediatek,mt7622-infracfg", "syscon"; |