diff options
| author | Tom Rini <trini@konsulko.com> | 2021-04-11 14:11:05 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-04-11 14:11:05 -0400 |
| commit | 3b676a1662ac6b54d1e97ea40a0c41ee0925ffe3 (patch) | |
| tree | d793c47b6ee68f30fb1426d526ac66f15b7cb636 | |
| parent | c6a4ee2aaee541c12d290dd25561e771396817cc (diff) | |
| parent | d3cfc474b764fc9d8fca6dc1dfe56f42e564f0f5 (diff) | |
| download | u-boot-WIP/11Apr2021.tar.gz | |
Merge branch '2021-04-11-remove-non-migrated-boards'WIP/11Apr2021
- Remove a large number of boards that have not migrated to DM_MMC, for
which the migration deadline with 2 years ago at v2019.04.
428 files changed, 21 insertions, 39732 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 79a0562182..d176e045e1 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -195,12 +195,6 @@ jobs: evb_ast2500: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" - vexpress_ca15_tc2: - TEST_PY_BD: "vexpress_ca15_tc2" - TEST_PY_ID: "--id qemu" - vexpress_ca9x4: - TEST_PY_BD: "vexpress_ca9x4" - TEST_PY_ID: "--id qemu" integratorcp_cm926ejs: TEST_PY_BD: "integratorcp_cm926ejs" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 28f72ab639..51bd64308a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -206,18 +206,6 @@ sandbox_flattree test.py: TEST_PY_BD: "sandbox_flattree" <<: *buildman_and_testpy_dfn -vexpress_ca15_tc2 test.py: - variables: - TEST_PY_BD: "vexpress_ca15_tc2" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -vexpress_ca9x4 test.py: - variables: - TEST_PY_BD: "vexpress_ca9x4" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - integratorcp_cm926ejs test.py: variables: TEST_PY_BD: "integratorcp_cm926ejs" @@ -1084,8 +1084,6 @@ endif $(call deprecated,CONFIG_DM_MMC CONFIG_BLK,MMC,v2019.04,$(CONFIG_MMC)) $(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\ USB,v2019.07,$(CONFIG_USB)) - $(call deprecated,CONFIG_AHCI,AHCI instead of CONFIG_MVSATA_IDE,v2019.07, \ - $(CONFIG_MVSATA_IDE)) $(call deprecated,CONFIG_AHCI,AHCI,v2019.07, $(CONFIG_LIBATA)) $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI)) $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 76adf7fdb2..01b5ba58de 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -346,7 +346,7 @@ config SYS_CACHELINE_SIZE choice prompt "Select the ARM data write cache policy" default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ - TARGET_BCMNSP || CPU_PXA || RZA1 + CPU_PXA || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -561,11 +561,6 @@ config ARCH_MVEBU select SPI imply CMD_DM -config TARGET_APF27 - bool "Support apf27" - select CPU_ARM926EJS - select SUPPORT_SPL - config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS @@ -650,13 +645,6 @@ config ARCH_BCM6858 select OF_CONTROL imply CMD_DM -config TARGET_VEXPRESS_CA15_TC2 - bool "Support vexpress_ca15_tc2" - select CPU_V7A - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select PL011_SERIAL - config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A @@ -668,28 +656,6 @@ config ARCH_BCMSTB This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips. -config TARGET_VEXPRESS_CA5X2 - bool "Support vexpress_ca5x2" - select CPU_V7A - select PL011_SERIAL - -config TARGET_VEXPRESS_CA9X4 - bool "Support vexpress_ca9x4" - select CPU_V7A - select PL011_SERIAL - -config TARGET_BCM23550_W1D - bool "Support bcm23550_w1d" - select CPU_V7A - imply CRC32_VERIFY - imply FAT_WRITE - -config TARGET_BCM28155_AP - bool "Support bcm28155_ap" - select CPU_V7A - imply CRC32_VERIFY - imply FAT_WRITE - config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A @@ -701,10 +667,6 @@ config TARGET_BCMCYGNUS imply HASH_VERIFY imply NETDEVICES -config TARGET_BCMNSP - bool "Support bcmnsp" - select CPU_V7A - config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 @@ -954,11 +916,6 @@ config ARCH_RMOBILE imply SYS_THUMB_BUILD imply ARCH_MISC_INIT if DISPLAY_CPUINFO -config TARGET_S32V234EVB - bool "Support s32v234evb" - select ARM64 - select SYS_FSL_ERRATUM_ESDHC111 - config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" select ARM64 @@ -1969,18 +1926,11 @@ source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" -source "board/armadeus/apf27/Kconfig" -source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" -source "board/broadcom/bcm23550_w1d/Kconfig" -source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" source "board/broadcom/bcm968360bg/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" -source "board/broadcom/bcmcygnus/Kconfig" -source "board/broadcom/bcmnsp/Kconfig" -source "board/broadcom/bcmns2/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" @@ -2003,7 +1953,6 @@ source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/lx2160a/Kconfig" -source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9cd6a8d642..b7a10a8e34 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -116,7 +116,7 @@ config PSCI_RESET !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ - !ARCH_UNIPHIER && !TARGET_S32V234EVB + !ARCH_UNIPHIER help Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile deleted file mode 100644 index 3bdb98d995..0000000000 --- a/arch/arm/cpu/armv8/s32v234/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - -obj-y += generic.o -obj-y += cpu.o diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c deleted file mode 100644 index 8ee3adc805..0000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/system.h> -#include <asm/armv8/mmu.h> -#include <asm/io.h> -#include <asm/arch/mc_me_regs.h> -#include <linux/bitops.h> -#include "cpu.h" - -u32 cpu_mask(void) -{ - return readl(MC_ME_CS); -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - -#define S32V234_IRAM_BASE 0x3e800000UL -#define S32V234_IRAM_SIZE 0x800000UL -#define S32V234_DRAM_BASE1 0x80000000UL -#define S32V234_DRAM_SIZE1 0x40000000UL -#define S32V234_DRAM_BASE2 0xC0000000UL -#define S32V234_DRAM_SIZE2 0x20000000UL -#define S32V234_PERIPH_BASE 0x40000000UL -#define S32V234_PERIPH_SIZE 0x40000000UL - -static struct mm_region s32v234_mem_map[] = { - { - .virt = S32V234_IRAM_BASE, - .phys = S32V234_IRAM_BASE, - .size = S32V234_IRAM_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_DRAM_BASE1, - .phys = S32V234_DRAM_BASE1, - .size = S32V234_DRAM_SIZE1, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_PERIPH_BASE, - .phys = S32V234_PERIPH_BASE, - .size = S32V234_PERIPH_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - /* TODO: Do we need these? */ - /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */ - }, { - .virt = S32V234_DRAM_BASE2, - .phys = S32V234_DRAM_BASE2, - .size = S32V234_DRAM_SIZE2, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_OUTER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = s32v234_mem_map; - -#endif - -/* - * Return the number of cores on this SOC. - */ -int cpu_numcores(void) -{ - int numcores; - u32 mask; - - mask = cpu_mask(); - numcores = hweight32(cpu_mask()); - - /* Verify if M4 is deactivated */ - if (mask & 0x1) - numcores--; - - return numcores; -} - -#if defined(CONFIG_ARCH_EARLY_INIT_R) -int arch_early_init_r(void) -{ - int rv; - asm volatile ("dsb sy"); - rv = fsl_s32v234_wake_seconday_cores(); - - if (rv) - printf("Did not wake secondary cores\n"); - - asm volatile ("sev"); - return 0; -} -#endif /* CONFIG_ARCH_EARLY_INIT_R */ diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h deleted file mode 100644 index 11c3a6b435..0000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -u32 cpu_mask(void); -int cpu_numcores(void); diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c deleted file mode 100644 index d1ae10b1a7..0000000000 --- a/arch/arm/cpu/armv8/s32v234/generic.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <clock_legacy.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/mc_rgm_regs.h> -#include <netdev.h> -#include <div64.h> -#include <errno.h> - -u32 get_cpu_rev(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - u32 cpu = readl(&mscmir->cpxtype); - - return cpu; -} - -DECLARE_GLOBAL_DATA_PTR; - -static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, - u32 pllfd, u32 selected_output) -{ - u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; - u32 plldv_rfdphi_div = 0, fout = 0; - u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0; - - if (selected_output > DFS_MAXNUMBER) { - return -1; - } - - plldv_prediv = - (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET; - plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); - - pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); - - plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv; - - /* The formula for VCO is from TR manual, rev. D */ - vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); - - if (selected_output != 0) { - /* Determine the RFDPHI for PHI1 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >> - PLLDIG_PLLDV_RFDPHI1_OFFSET; - plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div; - if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) { - dfs_portn = - readl(DFS_DVPORTn(pll, selected_output - 1)); - dfs_mfi = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - dfs_mfn = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - fout = vco / (dfs_mfi + (dfs_mfn / 256)); - } else { - fout = vco / plldv_rfdphi_div; - } - - } else { - /* Determine the RFDPHI for PHI0 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >> - PLLDIG_PLLDV_RFDPHI_OFFSET; - fout = vco / plldv_rfdphi_div; - } - - return fout; - -} - -/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */ -static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, - u32 selected_output) -{ - u32 plldv, pllfd; - - plldv = readl(PLLDIG_PLLDV(pll)); - pllfd = readl(PLLDIG_PLLFD(pll)); - - return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output); -} - -static u32 get_mcu_main_clk(void) -{ - u32 coreclk_div; - u32 sysclk_sel; - u32 freq = 0; - - sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - coreclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK; - coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - coreclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / coreclk_div; -} - -static u32 get_sys_clk(u32 number) -{ - u32 sysclk_div, sysclk_div_number; - u32 sysclk_sel; - u32 freq = 0; - - switch (number) { - case 3: - sysclk_div_number = 0; - break; - case 6: - sysclk_div_number = 1; - break; - default: - printf("unsupported system clock \n"); - return -1; - } - sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - sysclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) & - MC_CGM_SC_DCn_PREDIV_MASK; - sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - sysclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / sysclk_div; -} - -static u32 get_peripherals_clk(void) -{ - u32 aux5clk_div; - u32 freq = 0; - - aux5clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux5clk_div += 1; - - freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux5clk_div; - -} - -static u32 get_uart_clk(void) -{ - u32 auxclk3_div, auxclk3_sel, freq = 0; - - auxclk3_sel = - readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK; - auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET; - - auxclk3_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - auxclk3_div += 1; - - switch (auxclk3_sel) { - case MC_CGM_ACn_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_PERPLLDIVX: - freq = get_peripherals_clk() / 3; - break; - case MC_CGM_ACn_SEL_SYSCLK: - freq = get_sys_clk(6); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / auxclk3_div; -} - -static u32 get_fec_clk(void) -{ - u32 aux2clk_div; - u32 freq = 0; - - aux2clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux2clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux2clk_div; -} - -static u32 get_usdhc_clk(void) -{ - u32 aux15clk_div; - u32 freq = 0; - - aux15clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux15clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4); - - return freq / aux15clk_div; -} - -static u32 get_i2c_clk(void) -{ - return get_peripherals_clk(); -} - -/* return clocks in Hz */ -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return get_mcu_main_clk(); - case MXC_PERIPHERALS_CLK: - return get_peripherals_clk(); - case MXC_UART_CLK: - return get_uart_clk(); - case MXC_FEC_CLK: - return get_fec_clk(); - case MXC_I2C_CLK: - return get_i2c_clk(); - case MXC_USDHC_CLK: - return get_usdhc_clk(); - default: - break; - } - printf("Error: Unsupported function to read the frequency! \ - Please define it correctly!"); - return -1; -} - -/* Not yet implemented - int soc_clk_dump(); */ - -#if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_reset_cause(void) -{ - u32 cause = readl(MC_RGM_BASE_ADDR + 0x300); - - switch (cause) { - case F_SWT4: - return "WDOG"; - case F_JTAG: - return "JTAG"; - case F_FCCU_SOFT: - return "FCCU soft reaction"; - case F_FCCU_HARD: - return "FCCU hard reaction"; - case F_SOFT_FUNC: - return "Software Functional reset"; - case F_ST_DONE: - return "Self Test done reset"; - case F_EXT_RST: - return "External reset"; - default: - return "unknown reset"; - } - -} - -#define SRC_SCR_SW_RST (1<<12) - -void reset_cpu(void) -{ - printf("Feature not supported.\n"); -}; - -int print_cpuinfo(void) -{ - printf("CPU: Freescale Treerunner S32V234 at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - - return 0; -} -#endif - -int cpu_eth_init(struct bd_info * bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC_IMX - gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); -#endif - return 0; -} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c09ce8f888..d290c44257 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1071,10 +1071,6 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \ dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb -dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb -dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb -dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb - dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb diff --git a/arch/arm/dts/vexpress-v2m-rs1.dtsi b/arch/arm/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index d3963e9eaf..0000000000 --- a/arch/arm/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - smb@8000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/vexpress-v2m.dtsi b/arch/arm/dts/vexpress-v2m.dtsi deleted file mode 100644 index 798c97aff7..0000000000 --- a/arch/arm/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - -/ { - smb@4000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - v2m_sysreg: sysreg@0 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@1000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@2000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@4000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Both the core tile and the motherboard routes their output - * pads to this transmitter. The motherboard system controller - * can select one of them as input using a mux register in - * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is - * the only platform with this specific set-up. - */ - port@0 { - reg = <0>; - dvi_bridge_in_ct: endpoint { - remote-endpoint = <&clcd_pads_ct>; - }; - }; - port@1 { - reg = <1>; - dvi_bridge_in_mb: endpoint { - remote-endpoint = <&clcd_pads_mb>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads_mb: endpoint { - remote-endpoint = <&dvi_bridge_in_mb>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -};
\ No newline at end of file diff --git a/arch/arm/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/dts/vexpress-v2p-ca15_a7.dts deleted file mode 100644 index 00cd9f5bef..0000000000 --- a/arch/arm/dts/vexpress-v2p-ca15_a7.dts +++ /dev/null @@ -1,682 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 A7x3 - * Cortex-A15_A7 MPCore (V2P-CA15_A7) - * - * HBI-0249A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15_CA7"; - arm,hbi = <0x249>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - idle-states { - CLUSTER_SLEEP_BIG: cluster-sleep-big { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_LITTLE: cluster-sleep-little { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <500>; - min-residency-us = <2500>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - wdt@2a490000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0 0x2a490000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r0"; - reg = <0x9000 0x5000>; - interrupts = <0 105 4>, - <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>; - }; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ff00000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu-a15 { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>; - }; - - pmu-a7 { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 128 4>, - <0 129 4>, - <0 130 4>; - interrupt-affinity = <&cpu2>, - <&cpu3>, - <&cpu4>; - }; - - oscclk6a: oscclk6a { - /* Reference 24MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "oscclk6a"; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* A15 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk1 { - /* A15 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* A7 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - oscclk3 { - /* A7 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* External AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* Static memory controller clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-a15 { - /* A15 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "A15 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A15 Vcore"; - }; - - volt-a7 { - /* A7 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "A7 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A7 Vcore"; - }; - - amp-a15 { - /* Total current for the two A15 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "A15 Icore"; - }; - - amp-a7 { - /* Total current for the three A7 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "A7 Icore"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-a15 { - /* Total power for the two A15 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "A15 Pcore"; - }; - - power-a7 { - /* Total power for the three A7 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "A7 Pcore"; - }; - - energy-a15 { - /* Total energy for the two A15 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - label = "A15 Jcore"; - }; - - energy-a7 { - /* Total energy for the three A7 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>, <13 3>; - label = "A7 Jcore"; - }; - }; - - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* Input port #3 is for ITM, not supported here */ - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@5 { - reg = <5>; - funnel_in_port5: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - }; - }; - - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@2203c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203c000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@2203d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203d000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - etm@2203e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203e000 0 0x1000>; - - cpu = <&cpu4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; - }; - }; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/dts/vexpress-v2p-ca5s.dts b/arch/arm/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index d5b47d526f..0000000000 --- a/arch/arm/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,280 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x18000000 0x00800000>; - no-map; - }; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0x304>; - }; - - timer@2c000200 { - compatible = "arm,cortex-a5-global-timer", - "arm,cortex-a9-global-timer"; - reg = <0x2c000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&cpu_clk>; - }; - - watchdog@2c000620 { - compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - cpu_clk: oscclk0 { - /* CPU and internal AXI reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 100000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - axi_clk: oscclk1 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <5000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* DDR2 */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <80000000 120000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - hdlcd_clk: oscclk3 { - /* HDLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* Test chip gate configuration */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <80000000 80000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - smbclk: oscclk5 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - temp-dcc { - /* DCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index d796efaadb..0000000000 --- a/arch/arm/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; -#include "vexpress-v2m.dtsi" - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 3 is physically at 0x4c000000 */ - vram: vram@4c000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x4c000000 0x00800000>; - no-map; - }; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads_ct: endpoint { - remote-endpoint = <&dvi_bridge_in_ct>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1e000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e000620 0x20>; - interrupts = <1 14 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; - - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: extsaxiclk { - /* ACLK clock to the AXI master port on the test chip */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <30000000 50000000>; - #clock-cells = <0>; - clock-output-names = "extsaxiclk"; - }; - - oscclk1: clcdclk { - /* Reference clock for the CLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <10000000 80000000>; - #clock-cells = <0>; - clock-output-names = "clcdclk"; - }; - - smbclk: oscclk2: tcrefclk { - /* Reference clock for the test chip internal PLLs */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <33000000 100000000>; - #clock-cells = <0>; - clock-output-names = "tcrefclk"; - }; - - volt-vd10 { - /* Test Chip internal logic voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VD10"; - regulator-always-on; - label = "VD10"; - }; - - volt-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "VD10_S2"; - regulator-always-on; - label = "VD10_S2"; - }; - - volt-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 2>; - regulator-name = "VD10_S3"; - regulator-always-on; - label = "VD10_S3"; - }; - - volt-vcc1v8 { - /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 3>; - regulator-name = "VCC1V8"; - regulator-always-on; - label = "VCC1V8"; - }; - - volt-ddr2vtt { - /* DDR2 SDRAM VTT termination voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 4>; - regulator-name = "DDR2VTT"; - regulator-always-on; - label = "DDR2VTT"; - }; - - volt-vcc3v3 { - /* Local board supply for miscellaneous logic external to the Test Chip */ - arm,vexpress-sysreg,func = <2 5>; - compatible = "arm,vexpress-volt"; - regulator-name = "VCC3V3"; - regulator-always-on; - label = "VCC3V3"; - }; - - amp-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "VD10_S2"; - }; - - amp-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "VD10_S3"; - }; - - power-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "PVD10_S2"; - }; - - power-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "PVD10_S3"; - }; - }; - - smb: smb@4000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@e0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x20000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h deleted file mode 100644 index 70846094e8..0000000000 --- a/arch/arm/include/asm/arch-s32v234/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_PERIPHERALS_CLK, - MXC_UART_CLK, - MXC_USDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; -enum pll_type { - ARM_PLL = 0, - PERIPH_PLL, - ENET_PLL, - DDR_PLL, - VIDEO_PLL, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -void clock_init(void); - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h deleted file mode 100644 index 8c709af80d..0000000000 --- a/arch/arm/include/asm/arch-s32v234/ddr.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ -#define __ARCH_ARM_MACH_S32V234_DDR_H__ - -#define DDR0 0 -#define DDR1 1 - -/* DDR offset in MSCR register */ -#define _DDR0_RESET 168 -#define _DDR0_CLK0 169 -#define _DDR0_CAS 170 -#define _DDR0_RAS 171 -#define _DDR0_WE_B 172 -#define _DDR0_CKE0 173 -#define _DDR0_CKE1 174 -#define _DDR0_CS_B0 175 -#define _DDR0_CS_B1 176 -#define _DDR0_BA0 177 -#define _DDR0_BA1 178 -#define _DDR0_BA2 179 -#define _DDR0_A0 180 -#define _DDR0_A1 181 -#define _DDR0_A2 182 -#define _DDR0_A3 183 -#define _DDR0_A4 184 -#define _DDR0_A5 185 -#define _DDR0_A6 186 -#define _DDR0_A7 187 -#define _DDR0_A8 188 -#define _DDR0_A9 189 -#define _DDR0_A10 190 -#define _DDR0_A11 191 -#define _DDR0_A12 192 -#define _DDR0_A13 193 -#define _DDR0_A14 194 -#define _DDR0_A15 195 -#define _DDR0_DM0 196 -#define _DDR0_DM1 197 -#define _DDR0_DM2 198 -#define _DDR0_DM3 199 -#define _DDR0_DQS0 200 -#define _DDR0_DQS1 201 -#define _DDR0_DQS2 202 -#define _DDR0_DQS3 203 -#define _DDR0_D0 204 -#define _DDR0_D1 205 -#define _DDR0_D2 206 -#define _DDR0_D3 207 -#define _DDR0_D4 208 -#define _DDR0_D5 209 -#define _DDR0_D6 210 -#define _DDR0_D7 211 -#define _DDR0_D8 212 -#define _DDR0_D9 213 -#define _DDR0_D10 214 -#define _DDR0_D11 215 -#define _DDR0_D12 216 -#define _DDR0_D13 217 -#define _DDR0_D14 218 -#define _DDR0_D15 219 -#define _DDR0_D16 220 -#define _DDR0_D17 221 -#define _DDR0_D18 222 -#define _DDR0_D19 223 -#define _DDR0_D20 224 -#define _DDR0_D21 225 -#define _DDR0_D22 226 -#define _DDR0_D23 227 -#define _DDR0_D24 228 -#define _DDR0_D25 229 -#define _DDR0_D26 230 -#define _DDR0_D27 231 -#define _DDR0_D28 232 -#define _DDR0_D29 233 -#define _DDR0_D30 234 -#define _DDR0_D31 235 -#define _DDR0_ODT0 236 -#define _DDR0_ODT1 237 -#define _DDR0_ZQ 238 -#define _DDR1_RESET 239 -#define _DDR1_CLK0 240 -#define _DDR1_CAS 241 -#define _DDR1_RAS 242 -#define _DDR1_WE_B 243 -#define _DDR1_CKE0 244 -#define _DDR1_CKE1 245 -#define _DDR1_CS_B0 246 -#define _DDR1_CS_B1 247 -#define _DDR1_BA0 248 -#define _DDR1_BA1 249 -#define _DDR1_BA2 250 -#define _DDR1_A0 251 -#define _DDR1_A1 252 -#define _DDR1_A2 253 -#define _DDR1_A3 254 -#define _DDR1_A4 255 -#define _DDR1_A5 256 -#define _DDR1_A6 257 -#define _DDR1_A7 258 -#define _DDR1_A8 259 -#define _DDR1_A9 260 -#define _DDR1_A10 261 -#define _DDR1_A11 262 -#define _DDR1_A12 263 -#define _DDR1_A13 264 -#define _DDR1_A14 265 -#define _DDR1_A15 266 -#define _DDR1_DM0 267 -#define _DDR1_DM1 268 -#define _DDR1_DM2 269 -#define _DDR1_DM3 270 -#define _DDR1_DQS0 271 -#define _DDR1_DQS1 272 -#define _DDR1_DQS2 273 -#define _DDR1_DQS3 274 -#define _DDR1_D0 275 -#define _DDR1_D1 276 -#define _DDR1_D2 277 -#define _DDR1_D3 278 -#define _DDR1_D4 279 -#define _DDR1_D5 280 -#define _DDR1_D6 281 -#define _DDR1_D7 282 -#define _DDR1_D8 283 -#define _DDR1_D9 284 -#define _DDR1_D10 285 -#define _DDR1_D11 286 -#define _DDR1_D12 287 -#define _DDR1_D13 288 -#define _DDR1_D14 289 -#define _DDR1_D15 290 -#define _DDR1_D16 291 -#define _DDR1_D17 292 -#define _DDR1_D18 293 -#define _DDR1_D19 294 -#define _DDR1_D20 295 -#define _DDR1_D21 296 -#define _DDR1_D22 297 -#define _DDR1_D23 298 -#define _DDR1_D24 299 -#define _DDR1_D25 300 -#define _DDR1_D26 301 -#define _DDR1_D27 302 -#define _DDR1_D28 303 -#define _DDR1_D29 304 -#define _DDR1_D30 305 -#define _DDR1_D31 306 -#define _DDR1_ODT0 307 -#define _DDR1_ODT1 308 -#define _DDR1_ZQ 309 - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h deleted file mode 100644 index 1472a43f1b..0000000000 --- a/arch/arm/include/asm/arch-s32v234/imx-regs.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */ -#define IRAM_SIZE 0x00400000 /* 4MB */ - -#define AIPS0_BASE_ADDR (0x40000000UL) -#define AIPS1_BASE_ADDR (0x40080000UL) - -/* AIPS 0 */ -#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000) -#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000) -#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000) -#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000) -#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000) -#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000) -#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) -#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000) -#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000) -#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000) -#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000) -#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000) -#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000) -#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000) -#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000) -#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000) -#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000) -#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000) -#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000) -#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000) -#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000) -#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000) -#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000) -#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000) -#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000) -#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000) -#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000) - -/* AIPS 1 */ -#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000) -#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000) -#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000) -#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000) -#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000) -#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000) -#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000) -#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000) -#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000) -#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000) -#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000) -#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000) -#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000) -#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000) -#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000) -#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000) -#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000) -#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000) -#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000) -#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000) -#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000) -#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000) -#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000) -#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000) -#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000) -#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000) -#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000) -#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000) -#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000) -#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000) -#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000) -#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000) -#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000) -#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000) -#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000) -#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000) -#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000) -#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000) -#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000) -#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000) -#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000) -#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000) -#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000) - -/* TODO Remove this after the IOMUX framework is implemented */ -#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt router */ -#define MSCM_IRSPRC_CPn_EN 3 -#define MSCM_IRSPRC_NUM 176 -#define MSCM_CPXTYPE_RYPZ_MASK 0xFF -#define MSCM_CPXTYPE_RYPZ_OFFSET 0 -#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00 -#define MSCM_CPXTYPE_PERS_OFFSET 8 -#define MSCM_CPXTYPE_PERS_A53 0x413533 -#define MSCM_CPXTYPE_PERS_CM4 0x434d34 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 bmr1; - u32 bmr2; - u32 gpr1_boot; - u32 reserved_0x00C[61]; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 reserved_0x11C[1]; - u32 gpr9; - u32 gpr10; - u32 gpr11; - u32 gpr12; - u32 gpr13; - u32 gpr14; - u32 gpr15; - u32 gpr16; - u32 reserved_0x140[1]; - u32 gpr17; - u32 gpr18; - u32 gpr19; - u32 gpr20; - u32 gpr21; - u32 gpr22; - u32 gpr23; - u32 gpr24; - u32 gpr25; - u32 gpr26; - u32 gpr27; - u32 reserved_0x16C[5]; - u32 pcie_config1; - u32 ddr_self_ref_ctrl; - u32 pcie_config0; - u32 reserved_0x18C[4]; - u32 soc_misc_config2; -}; - -/* SRC registers definitions */ - -/* SRC_GPR1 */ -#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \ - (SRC_GPR1_PLL_OFFSET + (pll)) ) -#define SRC_GPR1_PLL_SOURCE_MASK (0x1) - -#define SRC_GPR1_PLL_OFFSET (27) -#define SRC_GPR1_FIRC_CLK_SOURCE (0x0) -#define SRC_GPR1_XOSC_CLK_SOURCE (0x1) - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u32 cr; - u32 ir; - u32 to; - u32 wn; - u32 sr; - u32 co; - u32 sk; -}; - -/* UART */ -struct linflex_fsl { - u32 lincr1; - u32 linier; - u32 linsr; - u32 linesr; - u32 uartcr; - u32 uartsr; - u32 lintcsr; - u32 linocr; - u32 lintocr; - u32 linfbrr; - u32 linibrr; - u32 lincfr; - u32 lincr2; - u32 bidr; - u32 bdrl; - u32 bdrm; - u32 ifer; - u32 ifmi; - u32 ifmr; - u32 ifcr0; - u32 ifcr1; - u32 ifcr2; - u32 ifcr3; - u32 ifcr4; - u32 ifcr5; - u32 ifcr6; - u32 ifcr7; - u32 ifcr8; - u32 ifcr9; - u32 ifcr10; - u32 ifcr11; - u32 ifcr12; - u32 ifcr13; - u32 ifcr14; - u32 ifcr15; - u32 gcr; - u32 uartpto; - u32 uartcto; - u32 dmatxe; - u32 dmarxe; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 cpxtype; /* Processor x Type Register */ - u32 cpxnum; /* Processor x Number Register */ - u32 cpxmaster; /* Processor x Master Number Register */ - u32 cpxcount; /* Processor x Count Register */ - u32 cpxcfg0; /* Processor x Configuration 0 Register */ - u32 cpxcfg1; /* Processor x Configuration 1 Register */ - u32 cpxcfg2; /* Processor x Configuration 2 Register */ - u32 cpxcfg3; /* Processor x Configuration 3 Register */ - u32 cp0type; /* Processor 0 Type Register */ - u32 cp0num; /* Processor 0 Number Register */ - u32 cp0master; /* Processor 0 Master Number Register */ - u32 cp0count; /* Processor 0 Count Register */ - u32 cp0cfg0; /* Processor 0 Configuration 0 Register */ - u32 cp0cfg1; /* Processor 0 Configuration 1 Register */ - u32 cp0cfg2; /* Processor 0 Configuration 2 Register */ - u32 cp0cfg3; /* Processor 0 Configuration 3 Register */ - u32 cp1type; /* Processor 1 Type Register */ - u32 cp1num; /* Processor 1 Number Register */ - u32 cp1master; /* Processor 1 Master Number Register */ - u32 cp1count; /* Processor 1 Count Register */ - u32 cp1cfg0; /* Processor 1 Configuration 0 Register */ - u32 cp1cfg1; /* Processor 1 Configuration 1 Register */ - u32 cp1cfg2; /* Processor 1 Configuration 2 Register */ - u32 cp1cfg3; /* Processor 1 Configuration 3 Register */ - u32 reserved_0x060[232]; - u32 ocmdr0; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x404[2]; - u32 ocmdr3; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x410[28]; - u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */ - u32 reserved_0x490[28]; - u32 cpce0; /* Core Parity Checking Enable Register 0 */ - u32 reserved_0x504[191]; - u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */ - u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */ - u32 reserved_0x808[6]; - u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */ - u32 reserved_0x824[23]; - u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */ - u32 reserved_0x9e0[136]; - u32 iahbbe0; /* Gasket Burst Enable Register */ - u32 reserved_0xc04[63]; - u32 ipcge; /* Interconnect Parity Checking Global Enable Register */ - u32 reserved_0xd04[3]; - u32 ipce[4]; /* Interconnect Parity Checking Enable Register */ - u32 reserved_0xd20[8]; - u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */ - u32 reserved_0xd44[3]; - u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */ -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h deleted file mode 100644 index c5efee5b75..0000000000 --- a/arch/arm/include/asm/arch-s32v234/lpddr2.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__ -#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__ - -/* definitions for LPDDR2 PAD values */ -#define LPDDR2_CLK0_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \ - SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_CKEn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_CS_Bn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DMn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DQSn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \ - SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_An_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) -#define LPDDR2_Dn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) - -#define _MDCTL 0x03010000 - -#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */ -#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */ -#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */ -#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */ -#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */ -#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */ -#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */ -#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */ -#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */ -#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */ -#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */ -#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */ -#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */ -#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */ -#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */ -#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */ -#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */ -#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */ -#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */ -#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */ -#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */ -#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */ -#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */ - -/* set I/O pads for DDR */ -void lpddr2_config_iomux(uint8_t module); -void config_mmdc(uint8_t module); - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h deleted file mode 100644 index 957d48f9c0..0000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_CGM registers definitions */ -/* MC_CGM_SC_SS */ -#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) ) -#define MC_CGM_SC_SEL_FIRC (0x0) -#define MC_CGM_SC_SEL_XOSC (0x1) -#define MC_CGM_SC_SEL_ARMPLL (0x2) -#define MC_CGM_SC_SEL_CLKDISABLE (0xF) - -/* MC_CGM_SC_DCn */ -#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) -#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET)) -#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000) -#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) -#define MC_CGM_SC_DCn_DE (1 << 31) -#define MC_CGM_SC_SEL_MASK (0x0F000000) -#define MC_CGM_SC_SEL_OFFSET (24) - -/* MC_CGM_ACn_DCm */ -#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) -#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET)) - -/* - * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown - * that the 5th bit is always ignored during writes if the current - * MC_CGM_ACn_DCm_PREDIV field has only 4 bits - * - * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits - * - * This should be changed if any problems occur. - */ -#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) -#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) -#define MC_CGM_ACn_DCm_DE (1 << 31) - -/* - * MC_CGM_ACn_SC/MC_CGM_ACn_SS - */ -#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20)) -#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20)) -#define MC_CGM_ACn_SEL_MASK (0x07000000) -#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET)) -#define MC_CGM_ACn_SEL_OFFSET (24) - -#define MC_CGM_ACn_SEL_FIRC (0x0) -#define MC_CGM_ACn_SEL_XOSC (0x1) -#define MC_CGM_ACn_SEL_ARMPLL (0x2) -/* - * According to the manual some PLL can be divided by X (X={1,3,5}): - * PERPLLDIVX, VIDEOPLLDIVX. - */ -#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3) -#define MC_CGM_ACn_SEL_ENETPLL (0x4) -#define MC_CGM_ACn_SEL_DDRPLL (0x5) -#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7) -#define MC_CGM_ACn_SEL_SYSCLK (0x8) -#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9) -#define MC_CGM_ACn_SEL_PERCLK (0xA) - -/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ -#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) -#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div)) -#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) - -/* - * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to - * the reference manual. This other value respect the formula 2^[RFDPHIBY+1] - */ -#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) -#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) - -#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) -#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) - -#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET)) -#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) -#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) -#define PLLDIG_PLLDV_PREDIV_OFFSET (12) - -/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ -#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) -#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) -#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) -#define PLLDIG_PLLFD_SMDEN (1 << 30) - -/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ -#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) -#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET)) -#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) -#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) - -/* Digital Frequency Synthesizer (DFS) */ -/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */ -#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040) - -/* DFS DLL Program Register 1 */ -#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) - -#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) -#define DFS_DLLPRG1_V2IGC_OFFSET (0) -#define DFS_DLLPRG1_V2IGC_MASK (0x00000007) - -#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) -#define DFS_DLLPRG1_LCKWT_OFFSET (4) -#define DFS_DLLPRG1_LCKWT_MASK (0x00000030) - -#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) -#define DFS_DLLPRG1_DACIN_OFFSET (6) -#define DFS_DLLPRG1_DACIN_MASK (0x000001C0) - -#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET)) -#define DFS_DLLPRG1_CALBYPEN_OFFSET (9) -#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200) - -#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET)) -#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10) -#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00) - -#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET)) -#define DFS_DLLPRG1_CPICTRL_OFFSET (12) -#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000) - -/* DFS Control Register (DFS_CTRL) */ -#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) -#define DFS_CTRL_DLL_LOLIE (1 << 0) -#define DFS_CTRL_DLL_RESET (1 << 1) - -/* DFS Port Status Register (DFS_PORTSR) */ -#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) -/* DFS Port Reset Register (DFS_PORTRESET) */ -#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) -#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET)) -#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) -#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) -#define DFS_PORTRESET_PORTRESET_OFFSET (0) - -/* DFS Divide Register Portn (DFS_DVPORTn) */ -#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) - -/* - * The mathematical formula for fdfs_clockout is the following: - * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) ) - */ -#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) ) -#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) ) -#define DFS_DVPORTn_MFI_MASK (0x0000FF00) -#define DFS_DVPORTn_MFN_MASK (0x000000FF) -#define DFS_DVPORTn_MFI_MAXVAL (0xFF) -#define DFS_DVPORTn_MFN_MAXVAL (0xFF) -#define DFS_DVPORTn_MFI_OFFSET (8) -#define DFS_DVPORTn_MFN_OFFSET (0) -#define DFS_MAXNUMBER (4) - -#define DFS_PARAMS_Nr (3) - -/* Frequencies are in Hz */ -#define FIRC_CLK_FREQ (48000000) -#define XOSC_CLK_FREQ (40000000) - -#define PLL_MIN_FREQ (650000000) -#define PLL_MAX_FREQ (1300000000) - -#define ARM_PLL_PHI0_FREQ (1000000000) -#define ARM_PLL_PHI1_FREQ (1000000000) -/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */ -#define ARM_PLL_PHI1_DFS1_EN (1) -#define ARM_PLL_PHI1_DFS1_MFI (3) -#define ARM_PLL_PHI1_DFS1_MFN (194) -/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS2_EN (1) -#define ARM_PLL_PHI1_DFS2_MFI (1) -#define ARM_PLL_PHI1_DFS2_MFN (170) -/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS3_EN (1) -#define ARM_PLL_PHI1_DFS3_MFI (1) -#define ARM_PLL_PHI1_DFS3_MFN (170) -#define ARM_PLL_PHI1_DFS_Nr (3) -#define ARM_PLL_PLLDV_PREDIV (2) -#define ARM_PLL_PLLDV_MFD (50) -#define ARM_PLL_PLLDV_MFN (0) - -#define PERIPH_PLL_PHI0_FREQ (400000000) -#define PERIPH_PLL_PHI1_FREQ (100000000) -#define PERIPH_PLL_PHI1_DFS_Nr (0) -#define PERIPH_PLL_PLLDV_PREDIV (1) -#define PERIPH_PLL_PLLDV_MFD (30) -#define PERIPH_PLL_PLLDV_MFN (0) - -#define ENET_PLL_PHI0_FREQ (500000000) -#define ENET_PLL_PHI1_FREQ (1000000000) -/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS1_EN (1) -#define ENET_PLL_PHI1_DFS1_MFI (2) -#define ENET_PLL_PHI1_DFS1_MFN (219) -/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS2_EN (1) -#define ENET_PLL_PHI1_DFS2_MFI (2) -#define ENET_PLL_PHI1_DFS2_MFN (219) -/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/ -#define ENET_PLL_PHI1_DFS3_EN (1) -#define ENET_PLL_PHI1_DFS3_MFI (3) -#define ENET_PLL_PHI1_DFS3_MFN (32) -/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/ -#define ENET_PLL_PHI1_DFS4_EN (1) -#define ENET_PLL_PHI1_DFS4_MFI (2) -#define ENET_PLL_PHI1_DFS4_MFN (0) -#define ENET_PLL_PHI1_DFS_Nr (4) -#define ENET_PLL_PLLDV_PREDIV (2) -#define ENET_PLL_PLLDV_MFD (50) -#define ENET_PLL_PLLDV_MFN (0) - -#define DDR_PLL_PHI0_FREQ (533000000) -#define DDR_PLL_PHI1_FREQ (1066000000) -/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS1_EN (1) -#define DDR_PLL_PHI1_DFS1_MFI (2) -#define DDR_PLL_PHI1_DFS1_MFN (33) -/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS2_EN (1) -#define DDR_PLL_PHI1_DFS2_MFI (2) -#define DDR_PLL_PHI1_DFS2_MFN (33) -/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */ -#define DDR_PLL_PHI1_DFS3_EN (1) -#define DDR_PLL_PHI1_DFS3_MFI (3) -#define DDR_PLL_PHI1_DFS3_MFN (11) -#define DDR_PLL_PHI1_DFS_Nr (3) -#define DDR_PLL_PLLDV_PREDIV (2) -#define DDR_PLL_PLLDV_MFD (53) -#define DDR_PLL_PLLDV_MFN (6144) - -#define VIDEO_PLL_PHI0_FREQ (600000000) -#define VIDEO_PLL_PHI1_FREQ (0) -#define VIDEO_PLL_PHI1_DFS_Nr (0) -#define VIDEO_PLL_PLLDV_PREDIV (1) -#define VIDEO_PLL_PLLDV_MFD (30) -#define VIDEO_PLL_PLLDV_MFN (0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h deleted file mode 100644 index 1671af4adb..0000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_ME registers definitions */ - -/* MC_ME_GS */ -#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000) - -#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0) -#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0) -#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0) -#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0) -#define MC_ME_GS_S_FIRC (1 << 4) -#define MC_ME_GS_S_XOSC (1 << 5) -#define MC_ME_GS_S_ARMPLL (1 << 6) -#define MC_ME_GS_S_PERPLL (1 << 7) -#define MC_ME_GS_S_ENETPLL (1 << 8) -#define MC_ME_GS_S_DDRPLL (1 << 9) -#define MC_ME_GS_S_VIDEOPLL (1 << 10) -#define MC_ME_GS_S_MVR (1 << 20) -#define MC_ME_GS_S_PDO (1 << 23) -#define MC_ME_GS_S_MTRANS (1 << 27) -#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28) -#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28) -#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28) - -/* MC_ME_MCTL */ -#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004) - -#define MC_ME_MCTL_KEY (0x00005AF0) -#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) -#define MC_ME_MCTL_RESET (0x0 << 28) -#define MC_ME_MCTL_TEST (0x1 << 28) -#define MC_ME_MCTL_DRUN (0x3 << 28) -#define MC_ME_MCTL_RUN0 (0x4 << 28) -#define MC_ME_MCTL_RUN1 (0x5 << 28) -#define MC_ME_MCTL_RUN2 (0x6 << 28) -#define MC_ME_MCTL_RUN3 (0x7 << 28) - -/* MC_ME_ME */ -#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008) - -#define MC_ME_ME_RESET_FUNC (1 << 0) -#define MC_ME_ME_TEST (1 << 1) -#define MC_ME_ME_DRUN (1 << 3) -#define MC_ME_ME_RUN0 (1 << 4) -#define MC_ME_ME_RUN1 (1 << 5) -#define MC_ME_ME_RUN2 (1 << 6) -#define MC_ME_ME_RUN3 (1 << 7) - -/* MC_ME_RUN_PCn */ -#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n)) - -#define MC_ME_RUN_PCn_RESET (1 << 0) -#define MC_ME_RUN_PCn_TEST (1 << 1) -#define MC_ME_RUN_PCn_DRUN (1 << 3) -#define MC_ME_RUN_PCn_RUN0 (1 << 4) -#define MC_ME_RUN_PCn_RUN1 (1 << 5) -#define MC_ME_RUN_PCn_RUN2 (1 << 6) -#define MC_ME_RUN_PCn_RUN3 (1 << 7) - -/* - * MC_ME_RESET_MC/MC_ME_TEST_MC - * MC_ME_DRUN_MC - * MC_ME_RUNn_MC - */ -#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020) -#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024) -#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C) -#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n)) - -#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val)) -#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F) -#define MC_ME_RUNMODE_MC_FIRCON (1 << 4) -#define MC_ME_RUNMODE_MC_XOSCON (1 << 5) -#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll))) -#define MC_ME_RUNMODE_MC_MVRON (1 << 20) -#define MC_ME_RUNMODE_MC_PDO (1 << 23) -#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28) -#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29) -#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30) - -/* MC_ME_DRUN_SEC_CC_I */ -#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260) -/* MC_ME_RUNn_SEC_CC_I */ -#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3) - -/* - * ME_PCTLn - * Please note that these registers are 8 bits width, so - * the operations over them should be done using 8 bits operations. - */ -#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK ) -#define MC_ME_PCTLn_RUNPCm_MASK (0x7) - -/* DEC200 Peripheral Control Register */ -#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4) -/* 2D-ACE Peripheral Control Register */ -#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB) -/* ENET Peripheral Control Register */ -#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1) -/* DMACHMUX0 Peripheral Control Register */ -#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2) -/* CSI0 Peripheral Control Register */ -#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3) -/* MMDC0 Peripheral Control Register */ -#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5) -/* FRAY Peripheral Control Register */ -#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7) -/* PIT0 Peripheral Control Register */ -#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9) -/* FlexTIMER0 Peripheral Control Register */ -#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C) -/* SARADC0 Peripheral Control Register */ -#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E) -/* LINFLEX0 Peripheral Control Register */ -#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110) -/* IIC0 Peripheral Control Register */ -#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112) -/* DSPI0 Peripheral Control Register */ -#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114) -/* CANFD0 Peripheral Control Register */ -#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116) -/* CRC0 Peripheral Control Register */ -#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118) -/* DSPI2 Peripheral Control Register */ -#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A) -/* SDHC Peripheral Control Register */ -#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E) -/* VIU0 Peripheral Control Register */ -#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127) -/* HPSMI Peripheral Control Register */ -#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B) -/* SIPI Peripheral Control Register */ -#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137) -/* LFAST Peripheral Control Register */ -#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B) -/* MMDC1 Peripheral Control Register */ -#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161) -/* DMACHMUX1 Peripheral Control Register */ -#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162) -/* CSI1 Peripheral Control Register */ -#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163) -/* QUADSPI0 Peripheral Control Register */ -#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165) -/* PIT1 Peripheral Control Register */ -#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169) -/* FlexTIMER1 Peripheral Control Register */ -#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175) -/* IIC2 Peripheral Control Register */ -#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179) -/* IIC1 Peripheral Control Register */ -#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B) -/* CANFD1 Peripheral Control Register */ -#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D) -/* LINFLEX1 Peripheral Control Register */ -#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F) -/* DSPI3 Peripheral Control Register */ -#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181) -/* DSPI1 Peripheral Control Register */ -#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183) -/* TSENS Peripheral Control Register */ -#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D) -/* CRC1 Peripheral Control Register */ -#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F) -/* VIU1 Peripheral Control Register */ -#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193) -/* JPEG Peripheral Control Register */ -#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197) -/* H264_DEC Peripheral Control Register */ -#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B) -/* H264_ENC Peripheral Control Register */ -#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F) -/* MBIST Peripheral Control Register */ -#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9) - -/* Core status register */ -#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h deleted file mode 100644 index 34501b2189..0000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ - -#define MC_RGM_DES (MC_RGM_BASE_ADDR) -#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300) -#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310) -#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330) -#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340) -#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350) -#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354) -#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358) -#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600) -#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607) -#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B) - -/* function reset sources mask */ -#define F_SWT4 0x8000 -#define F_JTAG 0x400 -#define F_FCCU_SOFT 0x40 -#define F_FCCU_HARD 0x20 -#define F_SOFT_FUNC 0x8 -#define F_ST_DONE 0x4 -#define F_EXT_RST 0x1 - -#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h deleted file mode 100644 index 8d74ae0266..0000000000 --- a/arch/arm/include/asm/arch-s32v234/mmdc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__ -#define __ARCH_ARM_MACH_S32V234_MMDC_H__ - -#define MMDC0 0 -#define MMDC1 1 - -#define MMDC_MDCTL 0x0 -#define MMDC_MDPDC 0x4 -#define MMDC_MDOTC 0x8 -#define MMDC_MDCFG0 0xC -#define MMDC_MDCFG1 0x10 -#define MMDC_MDCFG2 0x14 -#define MMDC_MDMISC 0x18 -#define MMDC_MDSCR 0x1C -#define MMDC_MDREF 0x20 -#define MMDC_MDRWD 0x2C -#define MMDC_MDOR 0x30 -#define MMDC_MDMRR 0x34 -#define MMDC_MDCFG3LP 0x38 -#define MMDC_MDMR4 0x3C -#define MMDC_MDASP 0x40 -#define MMDC_MAARCR 0x400 -#define MMDC_MAPSR 0x404 -#define MMDC_MAEXIDR0 0x408 -#define MMDC_MAEXIDR1 0x40C -#define MMDC_MADPCR0 0x410 -#define MMDC_MADPCR1 0x414 -#define MMDC_MADPSR0 0x418 -#define MMDC_MADPSR1 0x41C -#define MMDC_MADPSR2 0x420 -#define MMDC_MADPSR3 0x424 -#define MMDC_MADPSR4 0x428 -#define MMDC_MADPSR5 0x42C -#define MMDC_MASBS0 0x430 -#define MMDC_MASBS1 0x434 -#define MMDC_MAGENP 0x440 -#define MMDC_MPZQHWCTRL 0x800 -#define MMDC_MPWLGCR 0x808 -#define MMDC_MPWLDECTRL0 0x80C -#define MMDC_MPWLDECTRL1 0x810 -#define MMDC_MPWLDLST 0x814 -#define MMDC_MPODTCTRL 0x818 -#define MMDC_MPRDDQBY0DL 0x81C -#define MMDC_MPRDDQBY1DL 0x820 -#define MMDC_MPRDDQBY2DL 0x824 -#define MMDC_MPRDDQBY3DL 0x828 -#define MMDC_MPDGCTRL0 0x83C -#define MMDC_MPDGCTRL1 0x840 -#define MMDC_MPDGDLST0 0x844 -#define MMDC_MPRDDLCTL 0x848 -#define MMDC_MPRDDLST 0x84C -#define MMDC_MPWRDLCTL 0x850 -#define MMDC_MPWRDLST 0x854 -#define MMDC_MPZQLP2CTL 0x85C -#define MMDC_MPRDDLHWCTL 0x860 -#define MMDC_MPWRDLHWCTL 0x864 -#define MMDC_MPRDDLHWST0 0x868 -#define MMDC_MPRDDLHWST1 0x86C -#define MMDC_MPWRDLHWST1 0x870 -#define MMDC_MPWRDLHWST2 0x874 -#define MMDC_MPWLHWERR 0x878 -#define MMDC_MPDGHWST0 0x87C -#define MMDC_MPDGHWST1 0x880 -#define MMDC_MPDGHWST2 0x884 -#define MMDC_MPDGHWST3 0x888 -#define MMDC_MPPDCMPR1 0x88C -#define MMDC_MPPDCMPR2 0x890 -#define MMDC_MPSWDAR0 0x894 -#define MMDC_MPSWDRDR0 0x898 -#define MMDC_MPSWDRDR1 0x89C -#define MMDC_MPSWDRDR2 0x8A0 -#define MMDC_MPSWDRDR3 0x8A4 -#define MMDC_MPSWDRDR4 0x8A8 -#define MMDC_MPSWDRDR5 0x8AC -#define MMDC_MPSWDRDR6 0x8B0 -#define MMDC_MPSWDRDR7 0x8B4 -#define MMDC_MPMUR0 0x8B8 -#define MMDC_MPDCCR 0x8C0 - -#define MMDC_MPMUR0_FRC_MSR (1 << 11) -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16) - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h deleted file mode 100644 index 7572581054..0000000000 --- a/arch/arm/include/asm/arch-s32v234/siul.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__ -#define __ARCH_ARM_MACH_S32V234_SIUL_H__ - -#include "ddr.h" - -#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004) -#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008) -#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010) -#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018) -#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020) -#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028) -#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030) -#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038) - -#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040) -#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i)) - -#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0) - -/* SIUL2_MSCR specifications as stated in Reference Manual: - * 0 - 359 Output Multiplexed Signal Configuration Registers - * 512- 1023 Input Multiplexed Signal Configuration Registers */ -#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240) -#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i)) - -#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40) -#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i)) - -#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300) -#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i)) - -#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500) -#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i)) - -#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700) -#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i)) - -#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740) -#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i)) - -#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780) -#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i)) - -/* SIUL2_MSCR masks */ -#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000) -#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30) - -#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000) -#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29) -#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29) - -#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000) -#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27) -#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27) - -#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000) -#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24) -#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24) -#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24) -#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24) -#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24) -#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24) -#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24) - -#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000) -#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22) - -#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) -#define SIUL2_MSCR_OBE_EN (1 << 21) - -#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000) -#define SIUL2_MSCR_ODE_EN (1 << 20) - -#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_IBE_EN (1 << 19) - -#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000) -#define SIUL2_MSCR_HYS_EN (1 << 18) - -#define SIUL2_MSCR_INV(v) ((v) & 0x00020000) -#define SIUL2_MSCR_INV_EN (1 << 17) - -#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_PKE_EN (1 << 16) - -#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000) -#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14) -#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14) - -#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000) -#define SIUL2_MSCR_PUE_EN (1 << 13) - -#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800) -#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11) -#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11) -#define SIUL2_MSCR_PUS_100K_UP (2 << 11) -#define SIUL2_MSCR_PUS_33K_UP (3 << 11) - -#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700) -#define SIUL2_MSCR_DSE_240ohm (1 << 8) -#define SIUL2_MSCR_DSE_120ohm (2 << 8) -#define SIUL2_MSCR_DSE_80ohm (3 << 8) -#define SIUL2_MSCR_DSE_60ohm (4 << 8) -#define SIUL2_MSCR_DSE_48ohm (5 << 8) -#define SIUL2_MSCR_DSE_40ohm (6 << 8) -#define SIUL2_MSCR_DSE_34ohm (7 << 8) - -#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0) -#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6) - -#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020) -#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f) -#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1) -#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2) -#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3) - -/* UART settings */ -#define SIUL2_UART0_TXD_PAD 12 -#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \ - SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1) - -#define SIUL2_UART0_MSCR_RXD_PAD 11 -#define SIUL2_UART0_IMCR_RXD_PAD 200 - -#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT) -#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2) - -/* uSDHC settings */ -#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \ - SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN ) -#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1) -#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3) - -#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c78a308f48..1adf09b9a1 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -134,11 +134,6 @@ config TARGET_PM9G45 bool "Ronetix pm9g45 board" select AT91SAM9G45 -config TARGET_PICOSAM9G45 - bool "Mini-box picosam9g45 board" - select AT91SAM9M10G45 - select SUPPORT_SPL - config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select AT91SAM9N12 @@ -303,19 +298,6 @@ config TARGET_VINCO select SUPPORT_SPL imply CMD_DM -config TARGET_WB45N - bool "Support Laird WB45N" - select CPU_ARM926EJS - select SUPPORT_SPL - -config TARGET_WB50N - bool "Support Laird WB50N" - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select CPU_V7A - select SUPPORT_SPL - select ATMEL_SFR - endchoice config ATMEL_SFR @@ -351,15 +333,12 @@ source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" source "board/gardena/smart-gateway-at91sam/Kconfig" source "board/l+g/vinco/Kconfig" -source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -source "board/laird/wb45n/Kconfig" -source "board/laird/wb50n/Kconfig" config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 4ee7f6b2d4..580b45818f 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -52,11 +52,6 @@ config TARGET_MX53CX9020 select MX53 imply CMD_DM -config TARGET_MX53EVK - bool "Support mx53evk" - select BOARD_LATE_INIT - select MX53 - config TARGET_MX53LOCO bool "Support mx53loco" select BOARD_LATE_INIT @@ -68,10 +63,6 @@ config TARGET_MX53PPD help Enable support for the GE Healthcare PPD. -config TARGET_TS4800 - bool "Support TS4800" - select MX51 - config TARGET_USBARMORY bool "Support USB armory" select MX53 @@ -83,12 +74,10 @@ config SYS_SOC source "board/beckhoff/mx53cx9020/Kconfig" source "board/freescale/mx51evk/Kconfig" -source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/ge/mx53ppd/Kconfig" source "board/inversepath/usbarmory/Kconfig" source "board/k+p/kp_imx53/Kconfig" source "board/menlo/m53menlo/Kconfig" -source "board/technologic/ts4800/Kconfig" endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 92fb4c4f23..9450e6a683 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -111,12 +111,6 @@ choice prompt "MX6 board select" optional -config TARGET_ADVANTECH_DMS_BA16 - bool "Advantech dms-ba16" - depends on MX6Q - select BOARD_LATE_INIT - imply CMD_SATA - config TARGET_APALIS_IMX6 bool "Toradex Apalis iMX6 board" depends on MX6Q @@ -150,15 +144,6 @@ config TARGET_ARISTAINETOS2CCSLB imply CMD_SATA imply CMD_DM -config TARGET_CGTQMX6EVAL - bool "cgtqmx6eval" - depends on MX6QDL - select BOARD_LATE_INIT - select DM - select DM_THERMAL - select SUPPORT_SPL - imply CMD_DM - config TARGET_CM_FX6 bool "CM-FX6" depends on MX6QDL @@ -302,9 +287,6 @@ config TARGET_MX6MEMCAL and characterize the memory layout of a new design during the initial development and pre-production stages. -config TARGET_MX6QARM2 - bool "mx6qarm2" - config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" depends on MX6QDL @@ -476,11 +458,6 @@ config TARGET_OPOS6ULDEV depends on MX6UL select MX6UL_OPOS6UL -config TARGET_OT1200 - bool "Bachmann OT1200" - select SUPPORT_SPL - imply CMD_SATA - config TARGET_PICO_IMX6 bool "PICO-IMX6" depends on MX6QDL @@ -504,14 +481,6 @@ config TARGET_LITEBOARD select BOARD_LATE_INIT select MX6UL_LITESOM -config TARGET_PLATINUM_PICON - bool "platinum-picon" - select SUPPORT_SPL - -config TARGET_PLATINUM_TITANIUM - bool "platinum-titanium" - select SUPPORT_SPL - config TARGET_PCM058 bool "Phytec PCM058 i.MX6 Quad" depends on MX6Q @@ -521,12 +490,6 @@ config TARGET_PCM058 select OF_CONTROL imply CMD_DM -config TARGET_PFLA02 - bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad" - depends on MX6QDL - select BOARD_LATE_INIT - select SUPPORT_SPL - config TARGET_PCL063 bool "PHYTEC PCL063 (phyCORE-i.MX6UL)" depends on MX6UL @@ -551,9 +514,6 @@ config TARGET_PCL063_ULL select DM_THERMAL select SUPPORT_SPL -config TARGET_SECOMX6 - bool "secomx6 boards" - config TARGET_SOMLABS_VISIONSOM_6ULL bool "visionsom-6ull" depends on MX6ULL @@ -570,10 +530,6 @@ config TARGET_TBS2910 bool "TBS2910 Matrix ARM mini PC" depends on MX6Q -config TARGET_TITANIUM - bool "titanium" - depends on MX6Q - config TARGET_KP_IMX6Q_TPC bool "K+P KP_IMX6Q_TPC i.MX6 Quad" depends on MX6QDL @@ -645,31 +601,6 @@ config TARGET_WARP depends on MX6SL select BOARD_LATE_INIT -config TARGET_XPRESS - bool "CCV xPress" - depends on MX6UL - select BOARD_LATE_INIT - select DM - select DM_THERMAL - select SUPPORT_SPL - imply CMD_DM - -config TARGET_ZC5202 - bool "zc5202" - select BOARD_LATE_INIT - select DM - select DM_THERMAL - select SUPPORT_SPL - imply CMD_DM - -config TARGET_ZC5601 - bool "zc5601" - select BOARD_LATE_INIT - select DM - select DM_THERMAL - select SUPPORT_SPL - imply CMD_DM - config TARGET_BRPPT2 bool "brppt2" depends on MX6QDL @@ -695,23 +626,15 @@ config SYS_SOC source "board/ge/bx50v3/Kconfig" source "board/ge/b1x5v2/Kconfig" -source "board/advantech/dms-ba16/Kconfig" source "board/aristainetos/Kconfig" source "board/armadeus/opos6uldev/Kconfig" -source "board/bachmann/ot1200/Kconfig" -source "board/barco/platinum/Kconfig" -source "board/barco/titanium/Kconfig" source "board/boundary/nitrogen6x/Kconfig" source "board/bticino/mamoj/Kconfig" -source "board/ccv/xpress/Kconfig" source "board/compulab/cm_fx6/Kconfig" -source "board/congatec/cgtqmx6eval/Kconfig" source "board/dhelectronics/dh_imx6/Kconfig" -source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/engicam/imx6q/Kconfig" source "board/engicam/imx6ul/Kconfig" -source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6memcal/Kconfig" source "board/freescale/mx6sabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" @@ -723,7 +646,6 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" -source "board/phytec/pfla02/Kconfig" source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" @@ -731,7 +653,6 @@ source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" source "board/liebherr/mccmon6/Kconfig" source "board/logicpd/imx6/Kconfig" -source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index bcd8400af9..9f48ffda41 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -16,9 +16,6 @@ config TARGET_MX23EVK bool "Support mx23evk" select BOARD_EARLY_INIT_F -config TARGET_SANSA_FUZE_PLUS - bool "Support sansa_fuze_plus" - config TARGET_XFI3 bool "Support xfi3" @@ -29,8 +26,6 @@ config SYS_SOC source "board/olimex/mx23_olinuxino/Kconfig" source "board/freescale/mx23evk/Kconfig" -source "board/sandisk/sansa_fuze_plus/Kconfig" -source "board/creative/xfi3/Kconfig" endif @@ -51,12 +46,6 @@ config TARGET_MX28EVK bool "Support mx28evk" select BOARD_EARLY_INIT_F -config TARGET_SC_SPS_1 - bool "Support sc_sps_1" - -config TARGET_TS4600 - bool "Support TS4600" - config TARGET_XEA bool "Support XEA" @@ -68,7 +57,5 @@ config SYS_SOC source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" -source "board/schulercontrol/sc_sps_1/Kconfig" -source "board/technologic/ts4600/Kconfig" endif diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 4794f7aa9d..f5538f4a90 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -74,8 +74,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 /* Needs byte-swapping for ATA data register */ #define CONFIG_IDE_SWAP_IO /* Data, registers and alternate blocks are at the same offset */ diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 0a6eb4cb26..81c898b66e 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -89,18 +89,11 @@ config TARGET_OMAP3_OVERO select OMAP3_GPIO_6 imply CMD_DM -config TARGET_AM3517_CRANE - bool "am3517_crane" - config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" select OMAP3_GPIO_4 select OMAP3_GPIO_6 -config TARGET_TRICORDER - bool "Tricorder" - select OMAP3_GPIO_2 - config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" select BOARD_LATE_INIT @@ -166,11 +159,8 @@ source "board/ti/beagle/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" -source "board/ti/am3517crane/Kconfig" -source "board/corscience/tricorder/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" -source "board/technexion/tao3530/Kconfig" source "board/lg/sniper/Kconfig" endif diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig index 899289b645..cdac11c6b6 100644 --- a/arch/arm/mach-omap2/omap4/Kconfig +++ b/arch/arm/mach-omap2/omap4/Kconfig @@ -10,9 +10,6 @@ config TARGET_OMAP4_PANDA config TARGET_OMAP4_SDP4430 bool "TI OMAP4 SDP4430" -config TARGET_KC1 - bool "Amazon Kindle Fire (first generation)" - endchoice config SYS_SOC @@ -20,6 +17,5 @@ config SYS_SOC source "board/ti/panda/Kconfig" source "board/ti/sdp4430/Kconfig" -source "board/amazon/kc1/Kconfig" endif diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 2bae08e278..ff85834c46 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -28,11 +28,6 @@ config TARGET_CADDY2 bool "Support caddy2" select ARCH_MPC8349 -config TARGET_MPC8308RDB - bool "Support MPC8308RDB" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - config TARGET_MPC8313ERDB_NOR bool "Support MPC8313ERDB_NOR" select ARCH_MPC8313 @@ -75,18 +70,6 @@ config TARGET_MPC8349EMDS_SDRAM select SYS_FSL_DDR_BE select SYS_FSL_HAS_DDR2 -config TARGET_MPC8349ITX - bool "Support MPC8349ITX" - select ARCH_MPC8349 - imply CMD_IRQ - -config TARGET_MPC837XEMDS - bool "Support MPC837XEMDS" - select ARCH_MPC837X - select BOARD_EARLY_INIT_F - imply CMD_SATA - imply FSL_SATA - config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -142,16 +125,6 @@ config TARGET_TQM834X bool "Support TQM834x" select ARCH_MPC8349 -config TARGET_HRCON - bool "Support hrcon" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - -config TARGET_STRIDER - bool "Support strider" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - imply CMD_PCA953X config TARGET_GAZERBEAM bool "Support gazerbeam" @@ -330,14 +303,11 @@ config FSL_ELBC bool source "board/esd/vme8349/Kconfig" -source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" source "board/freescale/mpc8315erdb/Kconfig" source "board/freescale/mpc8323erdb/Kconfig" source "board/freescale/mpc832xemds/Kconfig" source "board/freescale/mpc8349emds/Kconfig" -source "board/freescale/mpc8349itx/Kconfig" -source "board/freescale/mpc837xemds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 124c22f58a..06a20c881d 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -210,14 +210,6 @@ config TARGET_T2080RDB imply CMD_SATA imply PANIC_HANG -config TARGET_T2081QDS - bool "Support T2081QDS" - select ARCH_T2081 - select SUPPORT_SPL - select PHYS_64BIT - select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - select FSL_DDR_INTERACTIVE - config TARGET_T4160RDB bool "Support T4160RDB" select ARCH_T4160 @@ -234,10 +226,6 @@ config TARGET_T4240RDB imply CMD_SATA imply PANIC_HANG -config TARGET_CONTROLCENTERD - bool "Support controlcenterd" - select ARCH_P1022 - config TARGET_KMP204X bool "Support kmp204x" select VENDOR_KM @@ -266,18 +254,6 @@ config TARGET_UCP1020 imply CMD_SATA imply PANIC_HANG -config TARGET_CYRUS_P5020 - bool "Support Varisys Cyrus P5020" - select ARCH_P5020 - select PHYS_64BIT - imply PANIC_HANG - -config TARGET_CYRUS_P5040 - bool "Support Varisys Cyrus P5040" - select ARCH_P5040 - select PHYS_64BIT - imply PANIC_HANG - endchoice config ARCH_B4420 @@ -576,23 +552,6 @@ config ARCH_P1021 imply CMD_REGINFO imply SATA_SIL -config ARCH_P1022 - bool - select FSL_LAW - select SYS_FSL_ERRATUM_A004477 - select SYS_FSL_ERRATUM_A004508 - select SYS_FSL_ERRATUM_A005125 - select SYS_FSL_ERRATUM_ELBC_A001 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_SATA_A001 - select FSL_PCIE_RESET - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_2 - select SYS_PPC_E500_USE_DEBUG_TLB - select FSL_ELBC - config ARCH_P1023 bool select FSL_LAW @@ -756,31 +715,6 @@ config ARCH_P4080 imply CMD_REGINFO imply SATA_SIL -config ARCH_P5020 - bool - select E500MC - select FSL_LAW - select SYS_FSL_DDR_VER_44 - select SYS_FSL_ERRATUM_A004510 - select SYS_FSL_ERRATUM_A005275 - select SYS_FSL_ERRATUM_A006261 - select SYS_FSL_ERRATUM_DDR_A003 - select SYS_FSL_ERRATUM_DDR_A003474 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_I2C_A004447 - select SYS_FSL_ERRATUM_SRIO_A004034 - select SYS_FSL_ERRATUM_USB14 - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_QORIQ_CHASSIS1 - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_4 - select SYS_PPC64 - select FSL_ELBC - imply CMD_SATA - imply CMD_REGINFO - imply FSL_SATA - config ARCH_P5040 bool select E500MC @@ -928,29 +862,6 @@ config ARCH_T2080 imply CMD_REGINFO imply FSL_SATA -config ARCH_T2081 - bool - select E500MC - select E6500 - select FSL_LAW - select SYS_FSL_DDR_VER_47 - select SYS_FSL_ERRATUM_A006379 - select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 - select SYS_FSL_ERRATUM_A007212 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_ESDHC111 - select FSL_PCIE_RESET - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_QORIQ_CHASSIS2 - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_4 - select SYS_PPC64 - select FSL_IFC - imply CMD_NAND - imply CMD_REGINFO - config ARCH_T4160 bool select E500MC @@ -1052,19 +963,16 @@ config MAX_CPUS ARCH_P5040 || \ ARCH_T1040 || \ ARCH_T1042 || \ - ARCH_T2080 || \ - ARCH_T2081 + ARCH_T2080 default 2 if ARCH_B4420 || \ ARCH_BSC9132 || \ ARCH_MPC8572 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1023 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 || \ - ARCH_P5020 || \ ARCH_T1023 || \ ARCH_T1024 default 1 @@ -1093,7 +1001,6 @@ config SYS_CCSRBAR_DEFAULT ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 @@ -1103,14 +1010,12 @@ config SYS_CCSRBAR_DEFAULT ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 || \ ARCH_T1023 || \ ARCH_T1024 || \ ARCH_T1040 || \ ARCH_T1042 || \ ARCH_T2080 || \ - ARCH_T2081 || \ ARCH_T4160 || \ ARCH_T4240 default 0xe0000000 if ARCH_QEMU_E500 @@ -1224,7 +1129,7 @@ config SYS_FSL_A004447_SVR_REV default 0x00 if ARCH_MPC8548 default 0x10 if ARCH_P1010 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 - default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 + default 0x20 if ARCH_P3041 || ARCH_P4080 config SYS_FSL_ERRATUM_IFC_A002769 bool @@ -1294,10 +1199,8 @@ config SYS_FSL_NUM_LAWS ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 || \ ARCH_T2080 || \ - ARCH_T2081 || \ ARCH_T4160 || \ ARCH_T4240 default 16 if ARCH_T1023 || \ @@ -1313,7 +1216,6 @@ config SYS_FSL_NUM_LAWS ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1023 || \ ARCH_P1024 || \ ARCH_P1025 || \ @@ -1363,7 +1265,6 @@ config SYS_PPC_E500_DEBUG_TLB ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 @@ -1404,7 +1305,6 @@ config SYS_FSL_LBC_CLK_DIV default 2 if ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 default 1 @@ -1429,11 +1329,9 @@ source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" source "board/freescale/t208xrdb/Kconfig" source "board/freescale/t4rdb/Kconfig" -source "board/gdsys/p1022/Kconfig" source "board/keymile/Kconfig" source "board/sbc8548/Kconfig" source "board/socrates/Kconfig" -source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 14e46626f3..b9d87ddb65 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o obj-$(CONFIG_ARCH_P2041) += p2041_ids.o obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o -obj-$(CONFIG_ARCH_P5020) += p5020_ids.o obj-$(CONFIG_ARCH_P5040) += p5040_ids.o obj-$(CONFIG_ARCH_T4240) += t4240_ids.o obj-$(CONFIG_ARCH_T4160) += t4240_ids.o @@ -51,7 +50,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_ids.o obj-$(CONFIG_ARCH_T1023) += t1024_ids.o obj-$(CONFIG_ARCH_T1024) += t1024_ids.o obj-$(CONFIG_ARCH_T2080) += t2080_ids.o -obj-$(CONFIG_ARCH_T2081) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o @@ -70,7 +68,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o -obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o @@ -78,7 +75,6 @@ obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o -obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o @@ -90,7 +86,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o -obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c deleted file mode 100644 index 719cb4f3d4..0000000000 --- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Author: Timur Tabi <timur@freescale.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> - -#define SRDS1_MAX_LANES 4 -#define SRDS2_MAX_LANES 2 - -static u32 serdes1_prtcl_map, serdes2_prtcl_map; - -static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { - [0x00] = {NONE, NONE, NONE, NONE}, - [0x01] = {NONE, NONE, NONE, NONE}, - [0x02] = {NONE, NONE, NONE, NONE}, - [0x03] = {NONE, NONE, NONE, NONE}, - [0x04] = {NONE, NONE, NONE, NONE}, - [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, - [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, - [0x09] = {PCIE1, NONE, NONE, NONE}, - [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, - [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, - [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, - [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, -}; - -static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { - [0x00] = {PCIE3, PCIE3}, - [0x01] = {PCIE2, PCIE3}, - [0x02] = {SATA1, SATA2}, - [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x04] = {NONE, NONE}, - [0x06] = {SATA1, SATA2}, - [0x07] = {NONE, NONE}, - [0x09] = {PCIE3, PCIE2}, - [0x0a] = {SATA1, SATA2}, - [0x0b] = {NONE, NONE}, - [0x0d] = {PCIE3, PCIE2}, - [0x0e] = {SATA1, SATA2}, - [0x0f] = {NONE, NONE}, - [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x16] = {SATA1, SATA2}, - [0x17] = {NONE, NONE}, - [0x18] = {PCIE3, PCIE3}, - [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x1a] = {SATA1, SATA2}, - [0x1b] = {NONE, NONE}, - [0x1c] = {PCIE3, PCIE3}, - [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x1e] = {SATA1, SATA2}, - [0x1f] = {NONE, NONE}, -}; - -int is_serdes_configured(enum srds_prtcl device) -{ - int ret; - - if (!(serdes1_prtcl_map & (1 << NONE))) - fsl_serdes_init(); - - ret = (1 << device) & serdes1_prtcl_map; - - if (ret) - return ret; - - if (!(serdes2_prtcl_map & (1 << NONE))) - fsl_serdes_init(); - - return (1 << device) & serdes2_prtcl_map; -} - -void fsl_serdes_init(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - int lane; - - if (serdes1_prtcl_map & (1 << NONE) && - serdes2_prtcl_map & (1 << NONE)) - return; - - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); - - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); - return; - } - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; - serdes1_prtcl_map |= (1 << lane_prtcl); - } - - /* Set the first bit to indicate serdes has been initialized */ - serdes1_prtcl_map |= (1 << NONE); - - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); - return; - } - - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; - serdes2_prtcl_map |= (1 << lane_prtcl); - } - - /* Set the first bit to indicate serdes has been initialized */ - serdes2_prtcl_map |= (1 << NONE); -} diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c deleted file mode 100644 index 575b604c21..0000000000 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> - -#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { - /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO(1, 2, 1, 0), - SET_QP_INFO(3, 4, 2, 1), - SET_QP_INFO(5, 6, 3, 0), - SET_QP_INFO(7, 8, 4, 1), - SET_QP_INFO(9, 10, 5, 0), - SET_QP_INFO(11, 12, 6, 1), - SET_QP_INFO(13, 14, 7, 0), - SET_QP_INFO(15, 16, 8, 1), - SET_QP_INFO(17, 18, 9, 0), - SET_QP_INFO(19, 20, 10, 1), -}; -#endif - -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_2(1, 199, 200), - SET_SRIO_LIODN_2(2, 201, 202), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - -struct liodn_id_table liodn_tbl[] = { -#ifdef CONFIG_SYS_DPAA_QBMAN - SET_QMAN_LIODN(31), - SET_BMAN_LIODN(32), -#endif - - SET_SDHC_LIODN(1, 64), - - SET_PME_LIODN(117), - - SET_USB_LIODN(1, "fsl-usb2-mph", 125), - SET_USB_LIODN(2, "fsl-usb2-dr", 126), - - SET_SATA_LIODN(1, 127), - SET_SATA_LIODN(2, 128), - - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - - SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), - SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), - - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), -}; -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); - -#ifdef CONFIG_SYS_DPAA_FMAN -struct fman_liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 10), - SET_FMAN_RX_1G_LIODN(1, 1, 11), - SET_FMAN_RX_1G_LIODN(1, 2, 12), - SET_FMAN_RX_1G_LIODN(1, 3, 13), - SET_FMAN_RX_1G_LIODN(1, 4, 14), - SET_FMAN_RX_10G_LIODN(1, 0, 15), -}; -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 129, 130), - SET_SEC_JR_LIODN_ENTRY(1, 131, 132), - SET_SEC_JR_LIODN_ENTRY(2, 133, 134), - SET_SEC_JR_LIODN_ENTRY(3, 135, 136), - SET_SEC_RTIC_LIODN_ENTRY(a, 154), - SET_SEC_RTIC_LIODN_ENTRY(b, 155), - SET_SEC_RTIC_LIODN_ENTRY(c, 156), - SET_SEC_RTIC_LIODN_ENTRY(d, 157), - SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), - SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), -}; -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); - -#ifdef CONFIG_SYS_FSL_RAID_ENGINE -struct liodn_id_table raide_liodn_tbl[] = { - SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), -}; -int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); -#endif - -#ifdef CONFIG_SYS_DPAA_RMAN -struct liodn_id_table rman_liodn_tbl[] = { - /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 6), - SET_RMAN_LIODN(1, 7), - SET_RMAN_LIODN(2, 8), - SET_RMAN_LIODN(3, 9), -}; -int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); -#endif - -struct liodn_id_table liodn_bases[] = { - [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), -#ifdef CONFIG_SYS_DPAA_FMAN - [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#endif -#ifdef CONFIG_SYS_DPAA_PME - [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), -#endif -#ifdef CONFIG_SYS_FSL_RAID_ENGINE - [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), -#endif -#ifdef CONFIG_SYS_DPAA_RMAN - [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), -#endif -}; diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c deleted file mode 100644 index ec8234c1c1..0000000000 --- a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_serdes.h> -#include <asm/processor.h> -#include <asm/io.h> -#include "fsl_corenet_serdes.h" - -static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { - [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, - [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, }, - [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, - SRIO1, }, - [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, - SATA1, SATA2, }, - [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, }, - [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, - SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, - AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, - NONE, SATA1, SATA2, }, - [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, - XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, - [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, - SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, - AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, - NONE, SATA1, SATA2, }, - [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, - XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, -}; - -enum srds_prtcl serdes_get_prtcl(int cfg, int lane) -{ - if (!serdes_lane_enabled(lane)) - return NONE; - - return serdes_cfg_tbl[cfg][lane]; -} - -int is_serdes_prtcl_valid(u32 prtcl) { - int i; - - if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[prtcl][i] != NONE) - return 1; - } - - return 0; -} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9c89ce5d70..864c53ce2e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) + defined(CONFIG_ARCH_T2080) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: @@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ - defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) + defined(CONFIG_ARCH_T2080) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) @@ -608,8 +608,7 @@ int get_clocks(void) * AN2919. */ #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ - defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ - defined(CONFIG_ARCH_P1022) + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) gd->arch.i2c1_clk = sys_info.freq_systembus; #elif defined(CONFIG_ARCH_MPC8544) /* diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 32cfcc0242..5f34aab453 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = { {} }; -#ifndef CONFIG_ARCH_T2081 static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, @@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = { {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, {} }; -#endif static const struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, -#ifndef CONFIG_ARCH_T2081 serdes2_cfg_tbl, -#endif }; enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4d70259f09..2053548731 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -66,10 +66,6 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_ARCH_P1022) -#define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 @@ -157,24 +153,6 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 -#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 - #elif defined(CONFIG_ARCH_P5040) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 @@ -364,7 +342,7 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 @@ -381,9 +359,6 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 #endif #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 035bf12467..6499e10ef4 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -25,7 +25,6 @@ defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ - defined(CONFIG_TARGET_T1040QDS) || \ defined(CONFIG_TARGET_T1040RDB) || \ defined(CONFIG_TARGET_T1040D4RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ @@ -58,7 +57,6 @@ #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_ARCH_P5020) || \ defined(CONFIG_ARCH_P5040) || \ defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 905613fa31..59bc32fd17 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1808,7 +1808,7 @@ typedef struct ccsr_gur { #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#elif defined(CONFIG_ARCH_T2080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1853,7 +1853,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif #if defined(CONFIG_ARCH_P2041) || \ - defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) + defined(CONFIG_ARCH_P3041) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1880,7 +1880,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#if defined(CONFIG_ARCH_T2080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2157,10 +2157,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_ARCH_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else @@ -2278,12 +2275,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 -#define MPC85xx_PMUXCR_TDM 0x00014800 -#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 -#define MPC85xx_PMUXCR_SPI 0x00000000 -#endif #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 @@ -2363,10 +2354,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 -#define MPC85xx_PMUXCR2_USB 0x00150000 -#endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig deleted file mode 100644 index 040eb866b5..0000000000 --- a/board/advantech/dms-ba16/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_ADVANTECH_DMS_BA16 - -choice - prompt "DDR Size" - default SYS_DDR_2G - -config SYS_DDR_1G - bool "1GiB" - -config SYS_DDR_2G - bool "2GiB" - -endchoice - -config IMX_CONFIG - default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G - default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G - -config SYS_BOARD - default "dms-ba16" - -config SYS_VENDOR - default "advantech" - -config SYS_SOC - default "mx6" - -config SYS_CONFIG_NAME - default "advantech_dms-ba16" - -endif diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS deleted file mode 100644 index e8ea3dd7b3..0000000000 --- a/board/advantech/dms-ba16/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -ADVANTECH_DMS-BA16 BOARD -M: Akshay Bhat <akshaybhat@timesys.com> -M: Ken Lin <Ken.Lin@advantech.com.tw> -S: Maintained -F: board/advantech/dms-ba16/ -F: include/configs/advantech_dms-ba16.h -F: configs/dms-ba16_defconfig -F: configs/dms-ba16-1g_defconfig diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile deleted file mode 100644 index b87fc29f06..0000000000 --- a/board/advantech/dms-ba16/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2016 Timesys Corporation -# Copyright 2016 Advantech Corporation - -obj-y := dms-ba16.o diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg deleted file mode 100644 index abc769c4e5..0000000000 --- a/board/advantech/dms-ba16/clocks.cfg +++ /dev/null @@ -1,25 +0,0 @@ -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en 1 --> CKO1 enabled - * cko1_div 111 --> divide by 8 - * cko1_sel 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/advantech/dms-ba16/ddr-setup.cfg b/board/advantech/dms-ba16/ddr-setup.cfg deleted file mode 100644 index 4c43e648f7..0000000000 --- a/board/advantech/dms-ba16/ddr-setup.cfg +++ /dev/null @@ -1,39 +0,0 @@ -/* DDR IO */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c deleted file mode 100644 index 07a47e9fbb..0000000000 --- a/board/advantech/dms-ba16/dms-ba16.c +++ /dev/null @@ -1,630 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Timesys Corporation - * Copyright 2016 Advantech Corporation - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <input.h> -#include <pwm.h> -DECLARE_GLOBAL_DATA_PTR; - -#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - /* AR8033 PHY Reset */ - MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset AR8033 PHY */ - gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(1, 28), 1); - mdelay(1); -} - -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} -#endif - -static iomux_v3_cfg_t const pcie_pads[] = { - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_pcie(void) -{ - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - gpio_direction_input(USDHC4_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers\n" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - /* set device address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - /* offset 0x8016: CLK_25M Clock Select */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - /* enable register write, no post increment, address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - /* set to 125 MHz from local PLL source */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); - /* set debug port address: SerDes Test and System Mode Control */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - /* enable rgmii tx clock delay */ - /* set the reserved bits to avoid board specific voltage peak issue*/ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - mx6_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#if defined(CONFIG_VIDEO_IPUV3) -static iomux_v3_cfg_t const backlight_pads[] = { - /* Power for LVDS Display */ - MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define LVDS_POWER_GP IMX_GPIO_NR(3, 22) - /* Backlight enable for LVDS display */ - MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) - /* backlight PWM brightness control */ - MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -int board_cfb_skip(void) -{ - gpio_direction_output(LVDS_POWER_GP, 1); - - return 0; -} - -static int detect_baseboard(struct display_info_t const *dev) -{ - return 0 == dev->addr; -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_baseboard, - .enable = NULL, - .mode = { - .name = "SHARP-LQ156M1LG21", - .refresh = 60, - .xres = 1920, - .yres = 1080, - .pixclock = 7851, - .left_margin = 100, - .right_margin = 40, - .upper_margin = 30, - .lower_margin = 3, - .hsync_len = 10, - .vsync_len = 2, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 3, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} } }; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - - imx_setup_hdmi(); - - /* Set LDB_DI0 as clock source for IPU_DI0 */ - clrsetbits_le32(&mxc_ccm->chsccdr, - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, - (CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); - - /* Turn on IPU LDB DI0 clocks */ - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); - - enable_ipu_clock(); - - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | - IOMUXC_GPR2_SPLIT_MODE_EN_MASK | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | - IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, - &iomux->gpr[2]); - - clrsetbits_le32(&iomux->gpr[3], - IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | - IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | - IOMUXC_GPR3_HDMI_MUX_CTL_MASK, - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); - - /* backlights off until needed */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - - gpio_direction_input(LVDS_POWER_GP); - gpio_direction_input(LVDS_BACKLIGHT_GP); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_eth_init(struct bd_info *bis) -{ - setup_iomux_enet(); - setup_pcie(); - - return cpu_eth_init(bis); -} - -static iomux_v3_cfg_t const misc_pads[] = { - MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), - MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), - MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), - MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), - MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), -}; -#define SUS_S3_OUT IMX_GPIO_NR(4, 11) -#define WIFI_EN IMX_GPIO_NR(6, 14) - -int setup_ba16_sata(void) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) - |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED - |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 - |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB - |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V - |IOMUXC_GPR13_SATA_PHY_1_SLOW); - - return 0; -} - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(misc_pads, - ARRAY_SIZE(misc_pads)); - - setup_iomux_uart(); - -#if defined(CONFIG_VIDEO_IPUV3) - /* Set LDB clock to PLL2 PFD0 */ - select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK); -#endif - return 0; -} - -int board_init(void) -{ - gpio_direction_output(SUS_S3_OUT, 1); - gpio_direction_output(WIFI_EN, 1); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -void pmic_init(void) -{ - -#define DA9063_ADDR 0x58 -#define BCORE2_CONF 0x9D -#define BCORE1_CONF 0x9E -#define BPRO_CONF 0x9F -#define BIO_CONF 0xA0 -#define BMEM_CONF 0xA1 -#define BPERI_CONF 0xA2 -#define MODE_BIT_H 7 -#define MODE_BIT_L 6 - - uchar val; - i2c_set_bus_num(2); - - i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1); - - i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1); - - i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1); - - i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1); - - i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1); - - i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1); - val |= (1 << MODE_BIT_H); - val &= ~(1 << MODE_BIT_L); - i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1); - -} - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#if defined(CONFIG_VIDEO_IPUV3) - /* - * We need at least 200ms between power on and backlight on - * as per specifications from CHI MEI - */ - mdelay(250); - - /* enable backlight PWM 1 */ - pwm_init(0, 0, 0); - - /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(0, 5000000, 5000000); - - /* Backlight Power */ - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); - - pwm_enable(0); -#endif - -#ifdef CONFIG_SATA - setup_ba16_sata(); -#endif - - /* board specific pmic init */ - pmic_init(); - - return 0; -} - -int checkboard(void) -{ - printf("BOARD: %s\n", CONFIG_BOARD_NAME); - return 0; -} diff --git a/board/advantech/dms-ba16/dms-ba16_1g.cfg b/board/advantech/dms-ba16/dms-ba16_1g.cfg deleted file mode 100644 index 1c737baaf2..0000000000 --- a/board/advantech/dms-ba16/dms-ba16_1g.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -IMAGE_VERSION 2 -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#include "micron-1g.cfg" -#include "clocks.cfg" diff --git a/board/advantech/dms-ba16/dms-ba16_2g.cfg b/board/advantech/dms-ba16/dms-ba16_2g.cfg deleted file mode 100644 index 371a84eb7e..0000000000 --- a/board/advantech/dms-ba16/dms-ba16_2g.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -IMAGE_VERSION 2 -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#include "samsung-2g.cfg" -#include "clocks.cfg" diff --git a/board/advantech/dms-ba16/micron-1g.cfg b/board/advantech/dms-ba16/micron-1g.cfg deleted file mode 100644 index 8cfefe28e2..0000000000 --- a/board/advantech/dms-ba16/micron-1g.cfg +++ /dev/null @@ -1,63 +0,0 @@ -/* Calibrations */ -/* ZQ */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 -/* write leveling */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F -/* Read DQS Gating calibration */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43480350 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x033C0340 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43480350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03340314 -/* Read calibration */ -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x382E2C32 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363044 -/* Write calibration */ -DATA 4 MX6_MMDC_P0_MPWRDLCTL, 0x3A38403A -DATA 4 MX6_MMDC_P1_MPWRDLCTL, 0x4432483E -/* read data bit delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* Complete calibration by forced measurment */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* MMDC init */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A79A5 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005a1023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831a0000 - -/* Initialize memory */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048039 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00033337 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00033337 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/advantech/dms-ba16/samsung-2g.cfg b/board/advantech/dms-ba16/samsung-2g.cfg deleted file mode 100644 index 4166cc9c57..0000000000 --- a/board/advantech/dms-ba16/samsung-2g.cfg +++ /dev/null @@ -1,63 +0,0 @@ -/* Calibrations */ -/* ZQ */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 -/* write leveling */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F -/* Read DQS Gating calibration */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C -/* Read calibration */ -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 -/* Write calibration */ -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E -/* read data bit delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* Complete calibration by forced measurment */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* MMDC init */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 -DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 - -/* Initialize memory */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b -DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/amazon/kc1/Kconfig b/board/amazon/kc1/Kconfig deleted file mode 100644 index 1b46a8f3c7..0000000000 --- a/board/amazon/kc1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KC1 - -config SYS_BOARD - default "kc1" - -config SYS_VENDOR - default "amazon" - -config SYS_CONFIG_NAME - default "kc1" - -endif diff --git a/board/amazon/kc1/MAINTAINERS b/board/amazon/kc1/MAINTAINERS deleted file mode 100644 index 7e596d906e..0000000000 --- a/board/amazon/kc1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KC1 BOARD -M: Paul Kocialkowski <contact@paulk.fr> -S: Maintained -F: board/amazon/kc1/ -F: include/configs/kc1.h -F: configs/kc1_defconfig diff --git a/board/amazon/kc1/Makefile b/board/amazon/kc1/Makefile deleted file mode 100644 index bad24dc0c2..0000000000 --- a/board/amazon/kc1/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Amazon Kindle Fire (first generation) codename kc1 config -# -# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - -obj-y := kc1.o diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c deleted file mode 100644 index 75fb14025c..0000000000 --- a/board/amazon/kc1/kc1.c +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Amazon Kindle Fire (first generation) codename kc1 config - * - * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - */ - -#include <config.h> -#include <common.h> -#include <env.h> -#include <fastboot.h> -#include <init.h> -#include <asm/global_data.h> -#include <linux/ctype.h> -#include <linux/usb/musb.h> -#include <asm/omap_musb.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/gpio.h> -#include <asm/emif.h> -#include <twl6030.h> -#include "kc1.h" -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -const struct omap_sysinfo sysinfo = { - .board_string = "kc1" -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12 -}; - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_UTMI, -}; - -static struct musb_hdrc_platform_data musb_platform_data = { - .mode = MUSB_PERIPHERAL, - .config = &musb_config, - .power = 100, - .platform_ops = &omap2430_ops, - .board_data = &musb_board_data, -}; - - -void set_muxconf_regs(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array, - sizeof(core_padconf_array) / sizeof(struct pad_conf_entry)); -} - -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) -{ - if (cs == CS1) - return NULL; - - *lpddr2_dev_details = elpida_2G_S4_details; - - return lpddr2_dev_details; -} - -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) -{ - *cs0_device_timings = &elpida_2G_S4_timings; - *cs1_device_timings = NULL; -} - -int board_init(void) -{ - /* GPMC init */ - gpmc_init(); - - /* MACH number */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; - - /* ATAGs location */ - gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100; - - return 0; -} - -int misc_init_r(void) -{ - char reboot_mode[2] = { 0 }; - u32 data = 0; - u32 value; - int rc; - - /* Reboot mode */ - - rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); - - /* USB ID pin pull-up indicates factory (fastboot) cable detection. */ - gpio_request(KC1_GPIO_USB_ID, "USB_ID"); - gpio_direction_input(KC1_GPIO_USB_ID); - value = gpio_get_value(KC1_GPIO_USB_ID); - - if (value) - reboot_mode[0] = 'b'; - - if (rc < 0 || reboot_mode[0] == 'o') { - /* - * When not rebooting, valid power on reasons are either the - * power button, charger plug or USB plug. - */ - - data |= twl6030_input_power_button(); - data |= twl6030_input_charger(); - data |= twl6030_input_usb(); - - if (!data) - twl6030_power_off(); - } - - if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { - if (!env_get("reboot-mode")) - env_set("reboot-mode", (char *)reboot_mode); - } - - omap_reboot_mode_clear(); - - /* Serial number */ - - omap_die_id_serial(); - - /* MUSB */ - - musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE); - - return 0; -} - -u32 get_board_rev(void) -{ - u32 value = 0; - - gpio_request(KC1_GPIO_MBID0, "MBID0"); - gpio_request(KC1_GPIO_MBID1, "MBID1"); - gpio_request(KC1_GPIO_MBID2, "MBID2"); - gpio_request(KC1_GPIO_MBID3, "MBID3"); - - gpio_direction_input(KC1_GPIO_MBID0); - gpio_direction_input(KC1_GPIO_MBID1); - gpio_direction_input(KC1_GPIO_MBID2); - gpio_direction_input(KC1_GPIO_MBID3); - - value |= (gpio_get_value(KC1_GPIO_MBID0) << 0); - value |= (gpio_get_value(KC1_GPIO_MBID1) << 1); - value |= (gpio_get_value(KC1_GPIO_MBID2) << 2); - value |= (gpio_get_value(KC1_GPIO_MBID3) << 3); - - return value; -} - -void get_board_serial(struct tag_serialnr *serialnr) -{ - omap_die_id_get_board_serial(serialnr); -} - -int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) -{ - if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER) - return -ENOTSUPP; - - return omap_reboot_mode_store("b"); -} - -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(1, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl6030_power_mmc_init(1); -} diff --git a/board/amazon/kc1/kc1.h b/board/amazon/kc1/kc1.h deleted file mode 100644 index da15b0843e..0000000000 --- a/board/amazon/kc1/kc1.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amazon Kindle Fire (first generation) codename kc1 config - * - * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - */ - -#ifndef _KC1_H_ -#define _KC1_H_ - -#include <asm/arch/mux_omap4.h> - -#define KC1_GPIO_USB_ID 52 -#define KC1_GPIO_MBID1 173 -#define KC1_GPIO_MBID0 174 -#define KC1_GPIO_MBID3 177 -#define KC1_GPIO_MBID2 178 - -const struct pad_conf_entry core_padconf_array[] = { - /* GPMC */ - { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */ - { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */ - { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */ - { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */ - { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */ - { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */ - { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */ - { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */ - { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */ - { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */ - { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */ - /* CAM */ - { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ - { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ - { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */ - /* HDQ */ - { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ - /* I2C1 */ - { I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */ - { I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */ - /* I2C2 */ - { I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */ - { I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */ - /* I2C3 */ - { I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */ - { I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */ - /* I2C4 */ - { I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */ - { I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */ - /* MCSPI1 */ - { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ - { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ - /* UART3 */ - { UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */ - { UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */ - { UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */ - { UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */ - /* SDMMC5 */ - { SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */ - { SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */ - { SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */ - { SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */ - { SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */ - { SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */ - /* MCSPI4 */ - { MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */ - { MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */ - { MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */ - { MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */ - /* UART4 */ - { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ - { UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */ - /* UNIPRO */ - { UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */ - { UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */ - { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */ - { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */ - { UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */ - { UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */ - { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */ - { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */ - { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */ - { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */ - { UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */ - { UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */ - /* USBA0_OTG */ - { USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */ - { USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */ - { USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */ -}; - -#endif diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig deleted file mode 100644 index 65544a8448..0000000000 --- a/board/armadeus/apf27/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APF27 - -config SYS_BOARD - default "apf27" - -config SYS_VENDOR - default "armadeus" - -config SYS_SOC - default "mx27" - -config SYS_CONFIG_NAME - default "apf27" - -endif diff --git a/board/armadeus/apf27/MAINTAINERS b/board/armadeus/apf27/MAINTAINERS deleted file mode 100644 index 09f0525c51..0000000000 --- a/board/armadeus/apf27/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -APF27 BOARD -M: Philippe Reynes <tremyfr@yahoo.fr> -M: Eric Jarrige <eric.jarrige@armadeus.org> -S: Maintained -F: board/armadeus/apf27/ -F: include/configs/apf27.h -F: configs/apf27_defconfig diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile deleted file mode 100644 index 57129718d5..0000000000 --- a/board/armadeus/apf27/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2012-2013 -# Eric Jarrige <eric.jarrige@armadeus.org> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := apf27.o -obj-y += lowlevel_init.o -obj-$(CONFIG_FPGA) += fpga.o diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c deleted file mode 100644 index 5e3fdd36fa..0000000000 --- a/board/armadeus/apf27/apf27.c +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> - * - * based on the files by - * Sascha Hauer, Pengutronix - */ - -#include <common.h> -#include <hang.h> -#include <init.h> -#include <asm/global_data.h> -#include <jffs2/jffs2.h> -#include <nand.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/errno.h> -#include <u-boot/crc.h> -#include "apf27.h" -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Fuse bank 1 row 8 is "reserved for future use" and therefore available for - * customer use. The APF27 board uses this fuse to store the board revision: - * 0: initial board revision - * 1: first revision - Presence of the second RAM chip on the board is blown in - * fuse bank 1 row 9 bit 0 - No hardware change - * N: to be defined - */ -static u32 get_board_rev(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - - return readl(&iim->bank[1].fuse_regs[8]); -} - -/* - * Fuse bank 1 row 9 is "reserved for future use" and therefore available for - * customer use. The APF27 board revision 1 uses the bit 0 to permanently store - * the presence of the second RAM chip - * 0: AFP27 with 1 RAM of 64 MiB - * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB) - */ -static int get_num_ram_bank(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - int nr_dram_banks = 1; - - if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1)) - nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01; - else - nr_dram_banks = CONFIG_NR_DRAM_POPULATED; - - return nr_dram_banks; -} - -static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2, - u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2, - u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr, - u32 puen, u32 gius) -{ - struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; - - writel(gpio_dr, ®s->port[port].gpio_dr); - writel(ocr1, ®s->port[port].ocr1); - writel(ocr2, ®s->port[port].ocr2); - writel(iconfa1, ®s->port[port].iconfa1); - writel(iconfa2, ®s->port[port].iconfa2); - writel(iconfb1, ®s->port[port].iconfb1); - writel(iconfb2, ®s->port[port].iconfb2); - writel(icr1, ®s->port[port].icr1); - writel(icr2, ®s->port[port].icr2); - writel(imr, ®s->port[port].imr); - writel(gpio_dir, ®s->port[port].gpio_dir); - writel(gpr, ®s->port[port].gpr); - writel(puen, ®s->port[port].puen); - writel(gius, ®s->port[port].gius); -} - -#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \ - ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \ - ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \ - ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \ - ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \ - ACFG_GIUS_##n##_VAL) - -static void apf27_iomux_init(void) -{ - APF27_PORT_INIT(A); - APF27_PORT_INIT(B); - APF27_PORT_INIT(C); - APF27_PORT_INIT(D); - APF27_PORT_INIT(E); - APF27_PORT_INIT(F); -} - -static int apf27_devices_init(void) -{ - int i; - unsigned int mode[] = { - PC5_PF_I2C2_DATA, - PC6_PF_I2C2_CLK, - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -#ifdef CONFIG_MXC_UART - mx27_uart1_init_pins(); -#endif - -#ifdef CONFIG_FEC_MXC - mx27_fec_init_pins(); -#endif - -#ifdef CONFIG_MMC_MXC - mx27_sd2_init_pins(); - imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16)); - gpio_request(PC_PWRON, "pc_pwron"); - gpio_set_value(PC_PWRON, 1); -#endif - return 0; -} - -static void apf27_setup_csx(void) -{ - struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE; - - writel(ACFG_CS0U_VAL, &weim->cs0u); - writel(ACFG_CS0L_VAL, &weim->cs0l); - writel(ACFG_CS0A_VAL, &weim->cs0a); - - writel(ACFG_CS1U_VAL, &weim->cs1u); - writel(ACFG_CS1L_VAL, &weim->cs1l); - writel(ACFG_CS1A_VAL, &weim->cs1a); - - writel(ACFG_CS2U_VAL, &weim->cs2u); - writel(ACFG_CS2L_VAL, &weim->cs2l); - writel(ACFG_CS2A_VAL, &weim->cs2a); - - writel(ACFG_CS3U_VAL, &weim->cs3u); - writel(ACFG_CS3L_VAL, &weim->cs3l); - writel(ACFG_CS3A_VAL, &weim->cs3a); - - writel(ACFG_CS4U_VAL, &weim->cs4u); - writel(ACFG_CS4L_VAL, &weim->cs4l); - writel(ACFG_CS4A_VAL, &weim->cs4a); - - writel(ACFG_CS5U_VAL, &weim->cs5u); - writel(ACFG_CS5L_VAL, &weim->cs5l); - writel(ACFG_CS5A_VAL, &weim->cs5a); - - writel(ACFG_EIM_VAL, &weim->eim); -} - -static void apf27_setup_port(void) -{ - struct system_control_regs *system = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; - - writel(ACFG_FMCR_VAL, &system->fmcr); -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - apf27_setup_csx(); - apf27_setup_port(); - apf27_iomux_init(); - apf27_devices_init(); -#if defined(CONFIG_FPGA) - APF27_init_fpga(); -#endif - - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - if (get_num_ram_bank() > 1) - gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - if (get_num_ram_bank() > 1) - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - else - gd->bd->bi_dram[1].size = 0; - - return 0; -} - -ulong board_get_usable_ram_top(ulong total_size) -{ - ulong ramtop; - - if (get_num_ram_bank() > 1) - ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - else - ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return ramtop; -} - -int checkboard(void) -{ - printf("Board: Armadeus APF27 revision %d\n", get_board_rev()); - return 0; -} - -#ifdef CONFIG_SPL_BUILD -inline void hang(void) -{ - for (;;) - ; -} - -void board_init_f(ulong bootflag) -{ - /* - * copy ourselves from where we are running to where we were - * linked at. Use ulong pointers as all addresses involved - * are 4-byte-aligned. - */ - ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; - asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); - asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); - asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); - asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); - for (dst = start_ptr; dst < end_ptr; dst++) - *dst = *(dst+(run_ptr-link_ptr)); - - /* - * branch to nand_boot's link-time address. - */ - asm volatile("ldr pc, =nand_boot"); -} -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h deleted file mode 100644 index 9c3cfd3cf4..0000000000 --- a/board/armadeus/apf27/apf27.h +++ /dev/null @@ -1,488 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> - */ - -#ifndef __APF27_H -#define __APF27_H - -/* FPGA program pin configuration */ -#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ -#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ -#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ -#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ -#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ -#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ -#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ -#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ -#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ -#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ -#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ - -/* MMC pin */ -#define PC_PWRON (GPIO_PORTF | 16) - -/* - * MPU CLOCK source before PLL - * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) - */ -#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ -#define ACFG_MPCTL1_VAL 0 -#define CONFIG_MPLL_FREQ 399 - -#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ - -/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ -#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ -#define ACFG_SPCTL1_VAL 0 -#define CONFIG_SPLL_FREQ 300 /* MHz */ - -/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ -#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ - -/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ -#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ - -#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ -#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ -#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ -#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ -#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ -#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ -#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ -#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ -#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ -#define CONFIG_CLK0_EN 1 /* CLK0 enabled */ - -/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ -#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ - -/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ -#define CONFIG_USB_FREQ 60 /* 60 MHz */ - -/* - * SDRAM - */ -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read - * cycle delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half - * 2=quater 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read - * cycle delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half - * 2=quater 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle - * delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength - * 1=half - * 2=quater - * 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -/* - * External interface - */ -/* - * CSCRxU_VAL: - * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 - * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | - * - * 15| x x | x x x x x x | x | x x x x | x x x x |0 - * | CNC | WSC |EW | WWS | EDC | - * - * CSCRxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x |16 - * | OEA | OEN | EBWA | EBWN | - * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 - * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| - * - * CSCRxA_VAL: - * 31| x x x x | x x x x | x x x x | x x x x |16 - * | EBRA | EBRN | RWA | RWN | - * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 - * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| - */ - -/* CS0 configuration for 16 bit nor flash */ -#define ACFG_CS0U_VAL 0x0000CC03 -#define ACFG_CS0L_VAL 0xa0330D01 -#define ACFG_CS0A_VAL 0x00220800 - -#define ACFG_CS1U_VAL 0x00000f00 -#define ACFG_CS1L_VAL 0x00000D01 -#define ACFG_CS1A_VAL 0 - -#define ACFG_CS2U_VAL 0 -#define ACFG_CS2L_VAL 0 -#define ACFG_CS2A_VAL 0 - -#define ACFG_CS3U_VAL 0 -#define ACFG_CS3L_VAL 0 -#define ACFG_CS3A_VAL 0 - -#define ACFG_CS4U_VAL 0 -#define ACFG_CS4L_VAL 0 -#define ACFG_CS4A_VAL 0 - -/* FPGA 16 bit data bus */ -#define ACFG_CS5U_VAL 0x00000600 -#define ACFG_CS5L_VAL 0x00000D01 -#define ACFG_CS5A_VAL 0 - -#define ACFG_EIM_VAL 0x00002200 - - -/* - * FPGA specific settings - */ - -/* CLKO */ -#define ACFG_CCSR_VAL 0x00000305 -/* drive strength CLKO set to 2 */ -#define ACFG_DSCR10_VAL 0x00020000 -/* drive strength A1..A12 set to 2 */ -#define ACFG_DSCR3_VAL 0x02AAAAA8 -/* drive strength ctrl */ -#define ACFG_DSCR7_VAL 0x00020880 -/* drive strength data */ -#define ACFG_DSCR2_VAL 0xAAAAAAAA - - -/* - * Default configuration for GPIOs and peripherals - */ -#define ACFG_DDIR_A_VAL 0x00000000 -#define ACFG_OCR1_A_VAL 0x00000000 -#define ACFG_OCR2_A_VAL 0x00000000 -#define ACFG_ICFA1_A_VAL 0xFFFFFFFF -#define ACFG_ICFA2_A_VAL 0xFFFFFFFF -#define ACFG_ICFB1_A_VAL 0xFFFFFFFF -#define ACFG_ICFB2_A_VAL 0xFFFFFFFF -#define ACFG_DR_A_VAL 0x00000000 -#define ACFG_GIUS_A_VAL 0xFFFFFFFF -#define ACFG_ICR1_A_VAL 0x00000000 -#define ACFG_ICR2_A_VAL 0x00000000 -#define ACFG_IMR_A_VAL 0x00000000 -#define ACFG_GPR_A_VAL 0x00000000 -#define ACFG_PUEN_A_VAL 0xFFFFFFFF - -#define ACFG_DDIR_B_VAL 0x00000000 -#define ACFG_OCR1_B_VAL 0x00000000 -#define ACFG_OCR2_B_VAL 0x00000000 -#define ACFG_ICFA1_B_VAL 0xFFFFFFFF -#define ACFG_ICFA2_B_VAL 0xFFFFFFFF -#define ACFG_ICFB1_B_VAL 0xFFFFFFFF -#define ACFG_ICFB2_B_VAL 0xFFFFFFFF -#define ACFG_DR_B_VAL 0x00000000 -#define ACFG_GIUS_B_VAL 0xFF3FFFF0 -#define ACFG_ICR1_B_VAL 0x00000000 -#define ACFG_ICR2_B_VAL 0x00000000 -#define ACFG_IMR_B_VAL 0x00000000 -#define ACFG_GPR_B_VAL 0x00000000 -#define ACFG_PUEN_B_VAL 0xFFFFFFFF - -#define ACFG_DDIR_C_VAL 0x00000000 -#define ACFG_OCR1_C_VAL 0x00000000 -#define ACFG_OCR2_C_VAL 0x00000000 -#define ACFG_ICFA1_C_VAL 0xFFFFFFFF -#define ACFG_ICFA2_C_VAL 0xFFFFFFFF -#define ACFG_ICFB1_C_VAL 0xFFFFFFFF -#define ACFG_ICFB2_C_VAL 0xFFFFFFFF -#define ACFG_DR_C_VAL 0x00000000 -#define ACFG_GIUS_C_VAL 0xFFFFC07F -#define ACFG_ICR1_C_VAL 0x00000000 -#define ACFG_ICR2_C_VAL 0x00000000 -#define ACFG_IMR_C_VAL 0x00000000 -#define ACFG_GPR_C_VAL 0x00000000 -#define ACFG_PUEN_C_VAL 0xFFFFFF87 - -#define ACFG_DDIR_D_VAL 0x00000000 -#define ACFG_OCR1_D_VAL 0x00000000 -#define ACFG_OCR2_D_VAL 0x00000000 -#define ACFG_ICFA1_D_VAL 0xFFFFFFFF -#define ACFG_ICFA2_D_VAL 0xFFFFFFFF -#define ACFG_ICFB1_D_VAL 0xFFFFFFFF -#define ACFG_ICFB2_D_VAL 0xFFFFFFFF -#define ACFG_DR_D_VAL 0x00000000 -#define ACFG_GIUS_D_VAL 0xFFFFFFFF -#define ACFG_ICR1_D_VAL 0x00000000 -#define ACFG_ICR2_D_VAL 0x00000000 -#define ACFG_IMR_D_VAL 0x00000000 -#define ACFG_GPR_D_VAL 0x00000000 -#define ACFG_PUEN_D_VAL 0xFFFFFFFF - -#define ACFG_DDIR_E_VAL 0x00000000 -#define ACFG_OCR1_E_VAL 0x00000000 -#define ACFG_OCR2_E_VAL 0x00000000 -#define ACFG_ICFA1_E_VAL 0xFFFFFFFF -#define ACFG_ICFA2_E_VAL 0xFFFFFFFF -#define ACFG_ICFB1_E_VAL 0xFFFFFFFF -#define ACFG_ICFB2_E_VAL 0xFFFFFFFF -#define ACFG_DR_E_VAL 0x00000000 -#define ACFG_GIUS_E_VAL 0xFCFFCCF8 -#define ACFG_ICR1_E_VAL 0x00000000 -#define ACFG_ICR2_E_VAL 0x00000000 -#define ACFG_IMR_E_VAL 0x00000000 -#define ACFG_GPR_E_VAL 0x00000000 -#define ACFG_PUEN_E_VAL 0xFFFFFFFF - -#define ACFG_DDIR_F_VAL 0x00000000 -#define ACFG_OCR1_F_VAL 0x00000000 -#define ACFG_OCR2_F_VAL 0x00000000 -#define ACFG_ICFA1_F_VAL 0xFFFFFFFF -#define ACFG_ICFA2_F_VAL 0xFFFFFFFF -#define ACFG_ICFB1_F_VAL 0xFFFFFFFF -#define ACFG_ICFB2_F_VAL 0xFFFFFFFF -#define ACFG_DR_F_VAL 0x00000000 -#define ACFG_GIUS_F_VAL 0xFF7F8000 -#define ACFG_ICR1_F_VAL 0x00000000 -#define ACFG_ICR2_F_VAL 0x00000000 -#define ACFG_IMR_F_VAL 0x00000000 -#define ACFG_GPR_F_VAL 0x00000000 -#define ACFG_PUEN_F_VAL 0xFFFFFFFF - -/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ -#define ACFG_GPCR_VAL 0x0003000F - -#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN - -/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ -#if (CONFIG_NR_DRAM_BANKS == 1) -#define ACFG_FMCR_VAL 0xFFFFFFF9 -#elif (CONFIG_NR_DRAM_BANKS == 2) -#define ACFG_FMCR_VAL 0xFFFFFFFB -#endif - -#define ACFG_AIPI1_PSR0_VAL 0x20040304 -#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB -#define ACFG_AIPI2_PSR0_VAL 0x00000000 -#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF - -/* PCCR enable DMA FEC I2C1 IIM SDHC1 */ -#define ACFG_PCCR0_VAL 0x05070410 -#define ACFG_PCCR1_VAL 0xA14A0608 - -/* - * From here, there should not be any user configuration. - * All Equations are automatic - */ - -/* fixme none integer value (7.5ns) => 2*hclock = 15ns */ -#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ - -/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ -#define CSCR_MASK 0x0300800D - -#define ACFG_CSCR_VAL \ - (CSCR_MASK \ - |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ - |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ - |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) - -/* SSIx CLKO NFC H264 MSHC */ -#define ACFG_PCDR0_VAL\ - (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ - |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ - |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ - |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ - |(((CONFIG_CLK0_DIV)&0x07)<<22)\ - |(((CONFIG_CLK0_EN)&0x01)<<25)\ - |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) - -/* PERCLKx */ -#define ACFG_PCDR1_VAL\ - (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) - -/* SDRAM controller programming Values */ -#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ - (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) -#define REG_FIELD_SCL_VAL 3 -#define REG_FIELD_SCLIMX_VAL 0 -#else -#define REG_FIELD_SCL_VAL\ - ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH) -#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL -#endif - -#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) -#define REG_FIELD_SRC_VAL 0 -#else -#define REG_FIELD_SRC_VAL\ - ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH) -#endif - -/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ -#define REG_ESDCTL_BASE_CONFIG (0x80020485\ - | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ - | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ - | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) - -#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) - -/* ESDRAMC Configuration Registers : force CL=3 to lpddr */ -#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ - | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ - | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ - | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ - ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ - | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ - | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ - | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ - | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ - | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ - | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ - | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) - -/* Issue Mode register Command to SDRAM */ -#define ACFG_SDRAM_MODE_REGISTER_VAL\ - ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ - | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ - | ((0)<<(3)) /* sequentiql access */ \ - /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) - -/* Issue Extended Mode register Command to SDRAM */ -#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ - ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ - | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ - | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) - -/* Issue Precharge all Command to SDRAM */ -#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) - -#endif /* __APF27_H */ diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c deleted file mode 100644 index 9e2f39f981..0000000000 --- a/board/armadeus/apf27/fpga.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002-2013 - * Eric Jarrige <eric.jarrige@armadeus.org> - * - * based on the files by - * Rich Ireland, Enterasys Networks, rireland@enterasys.com - * and - * Keith Outwater, keith_outwater@mvis.com - */ -#include <common.h> -#include <log.h> -#include <linux/delay.h> - -#include <asm/arch/imx-regs.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <command.h> -#include <config.h> -#include "fpga.h" -#include <spartan3.h> -#include "apf27.h" - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * Spartan2 code is used to download our Spartan 3 :) code is compatible. - * Just take care about the file size - */ -xilinx_spartan3_slave_parallel_fns fpga_fns = { - fpga_pre_fn, - fpga_pgm_fn, - fpga_init_fn, - NULL, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_rdata_fn, - fpga_wdata_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_fn, -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {xilinx_spartan3, - slave_parallel, - 1196128l/8, - (void *)&fpga_fns, - 0, - &spartan3_op, - "3s200aft256"} -}; - -/* - * Initialize GPIO port B before download - */ -int fpga_pre_fn(int cookie) -{ - /* Initialize GPIO pins */ - gpio_set_value(ACFG_FPGA_PWR, 1); - imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO); - gpio_set_value(ACFG_FPGA_RESET, 1); - imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - gpio_set_value(ACFG_FPGA_PRG, 1); - gpio_set_value(ACFG_FPGA_CLK, 1); - gpio_set_value(ACFG_FPGA_RW, 1); - gpio_set_value(ACFG_FPGA_CS, 1); - gpio_set_value(ACFG_FPGA_SUSPEND, 0); - gpio_set_value(ACFG_FPGA_PWR, 0); - udelay(30000); /*wait until supply started*/ - - return cookie; -} - -/* - * Set the FPGA's active-low program line to the specified level - */ -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, - assert ? "high" : "low"); - gpio_set_value(ACFG_FPGA_PRG, !assert); - return assert; -} - -/* - * Set the FPGA's active-high clock line to the specified level - */ -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, - assert_clk ? "high" : "low"); - gpio_set_value(ACFG_FPGA_CLK, !assert_clk); - return assert_clk; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn(int cookie) -{ - int value; - debug("%s:%d: INIT check... ", __func__, __LINE__); - value = gpio_get_value(ACFG_FPGA_INIT); - /* printf("init value read %x",value); */ -#ifdef CONFIG_SYS_FPGA_IS_PROTO - return value; -#else - return !value; -#endif -} - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn(int cookie) -{ - debug("%s:%d: DONE check... %s", __func__, __LINE__, - gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low"); - return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL; -} - -/* - * Set the FPGA's wr line to the specified level - */ -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - debug("%s:%d: FPGA RW... %s ", __func__, __LINE__, - assert_write ? "high" : "low"); - gpio_set_value(ACFG_FPGA_RW, !assert_write); - return assert_write; -} - -int fpga_cs_fn(int assert_cs, int flush, int cookie) -{ - debug("%s:%d: FPGA CS %s ", __func__, __LINE__, - assert_cs ? "high" : "low"); - gpio_set_value(ACFG_FPGA_CS, !assert_cs); - return assert_cs; -} - -int fpga_rdata_fn(unsigned char *data, int cookie) -{ - debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__, - *((char *)ACFG_FPGA_RDATA)); - *data = (unsigned char) - ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF); - return *data; -} - -int fpga_wdata_fn(unsigned char data, int flush, int cookie) -{ - debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__, - data); - *((unsigned short *)ACFG_FPGA_WDATA) = data; - return data; -} - -int fpga_abort_fn(int cookie) -{ - return fpga_post_fn(cookie); -} - - -int fpga_busy_fn(int cookie) -{ - return 1; -} - -int fpga_post_fn(int cookie) -{ - debug("%s:%d: FPGA POST ", __func__, __LINE__); - - imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN); - imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN); - imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN); - gpio_set_value(ACFG_FPGA_PRG, 1); - gpio_set_value(ACFG_FPGA_RESET, 0); - imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - return cookie; -} - -void apf27_fpga_setup(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - struct system_control_regs *system = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; - - /* Configure FPGA CLKO */ - writel(ACFG_CCSR_VAL, &pll->ccsr); - - /* Configure strentgh for FPGA */ - writel(ACFG_DSCR10_VAL, &system->dscr10); - writel(ACFG_DSCR3_VAL, &system->dscr3); - writel(ACFG_DSCR7_VAL, &system->dscr7); - writel(ACFG_DSCR2_VAL, &system->dscr2); -} - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -void APF27_init_fpga(void) -{ - int i; - - apf27_fpga_setup(); - - fpga_init(); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); - fpga_add(fpga_xilinx, &fpga[i]); - } - - return; -} diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h deleted file mode 100644 index d6394e976a..0000000000 --- a/board/armadeus/apf27/fpga.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002-2013 - * Eric Jarrige <eric.jarrige@armadeus.org> - * - * based on the files by - * Rich Ireland, Enterasys Networks, rireland@enterasys.com - * and - * Keith Outwater, keith_outwater@mvis.com - */ -extern void APF27_init_fpga(void); - -extern int fpga_pre_fn(int cookie); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_rdata_fn(unsigned char *data, int cookie); -extern int fpga_wdata_fn(unsigned char data, int flush, int cookie); -extern int fpga_abort_fn(int cookie); -extern int fpga_post_fn(int cookie); -extern int fpga_busy_fn(int cookie); diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S deleted file mode 100644 index 0991b7ddf4..0000000000 --- a/board/armadeus/apf27/lowlevel_init.S +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr> - */ - -#include <config.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> -#include <asm/arch/imx-regs.h> -#include "apf27.h" - - .macro init_aipi - /* - * setup AIPI1 and AIPI2 - */ - write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL - write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL - write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL - write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL - - /* Change SDRAM signal strengh */ - ldr r0, =GPCR - ldr r1, =ACFG_GPCR_VAL - ldr r5, [r0] - orr r5, r5, r1 - str r5, [r0] - - .endm /* init_aipi */ - - .macro init_clock - ldr r0, =CSCR - /* disable MPLL/SPLL first */ - ldr r1, [r0] - bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) - str r1, [r0] - - /* - * pll clock initialization predefined in apf27.h - */ - write32 MPCTL0, ACFG_MPCTL0_VAL - write32 SPCTL0, ACFG_SPCTL0_VAL - - write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART - - /* - * add some delay here - */ - mov r1, #0x1000 - 1: subs r1, r1, #0x1 - bne 1b - - /* peripheral clock divider */ - write32 PCDR0, ACFG_PCDR0_VAL - write32 PCDR1, ACFG_PCDR1_VAL - - /* Configure PCCR0 and PCCR1 */ - write32 PCCR0, ACFG_PCCR0_VAL - write32 PCCR1, ACFG_PCCR1_VAL - - .endm /* init_clock */ - - .macro init_ddr - /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ - ldr r0, =IMX_ESD_BASE - ldr r4, =ESDMISC_SDRAM_RDY -2: ldr r1, [r0, #ESDMISC_ROF] - ands r1, r1, r4 - bpl 2b - - /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ - ldr r0, =IMX_ESD_BASE - ldr r4, =ACFG_ESDMISC_VAL - orr r1, r4, #ESDMISC_MDDR_DL_RST - str r1, [r0, #ESDMISC_ROF] - - /* Hold for more than 200ns */ - ldr r1, =0x10000 -1: subs r1, r1, #0x1 - bne 1b - - str r4, [r0] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL - str r1, [r0, #ESDCFG0_ROF] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_PRECHARGE_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* write8(0xA0001000, any value) */ - ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL - strb r2, [r1] - - ldr r1, =ACFG_AUTOREFRESH_CMD - str r1, [r0, #ESDCTL0_ROF] - - ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ - - ldr r6,=0x7 /* load loop counter */ -1: str r5,[r4] /* run auto-refresh cycle to array 0 */ - subs r6,r6,#1 - bne 1b - - ldr r1, =ACFG_SET_MODE_REG_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* set standard mode register */ - ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL - strb r2, [r4] - - /* set extended mode register */ - ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL - strb r5, [r4] - - ldr r1, =ACFG_NORMAL_RW_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* 2nd sdram */ - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL - str r1, [r0, #ESDCFG1_ROF] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_PRECHARGE_CMD - str r1, [r0, #ESDCTL1_ROF] - - /* write8(0xB0001000, any value) */ - ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL - strb r2, [r1] - - ldr r1, =ACFG_AUTOREFRESH_CMD - str r1, [r0, #ESDCTL1_ROF] - - ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ - - ldr r6,=0x7 /* load loop counter */ -1: str r5,[r4] /* run auto-refresh cycle to array 0 */ - subs r6,r6,#1 - bne 1b - - ldr r1, =ACFG_SET_MODE_REG_CMD - str r1, [r0, #ESDCTL1_ROF] - - /* set standard mode register */ - ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL - strb r2, [r4] - - /* set extended mode register */ - ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL - strb r2, [r4] - - ldr r1, =ACFG_NORMAL_RW_CMD - str r1, [r0, #ESDCTL1_ROF] - .endm /* init_ddr */ - -.globl lowlevel_init -lowlevel_init: - - init_aipi - init_clock -#ifdef CONFIG_SPL_BUILD - init_ddr -#endif - - mov pc, lr diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig deleted file mode 100644 index 2e15e0d497..0000000000 --- a/board/armltd/vexpress/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -if TARGET_VEXPRESS_CA15_TC2 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca15_tc2" - -endif - -if TARGET_VEXPRESS_CA5X2 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca5x2" - -endif - -if TARGET_VEXPRESS_CA9X4 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca9x4" - -endif diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS deleted file mode 100644 index 7b3fb42e56..0000000000 --- a/board/armltd/vexpress/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -VERSATILE EXPRESS BOARDS -M: Linus Walleij <linus.walleij@linaro.org> -S: Maintained -F: board/armltd/vexpress/ -F: include/configs/vexpress_ca15_tc2.h -F: configs/vexpress_ca15_tc2_defconfig -F: include/configs/vexpress_ca5x2.h -F: configs/vexpress_ca5x2_defconfig -F: include/configs/vexpress_ca9x4.h -F: configs/vexpress_ca9x4_defconfig diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile deleted file mode 100644 index 2a659de012..0000000000 --- a/board/armltd/vexpress/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := vexpress_common.o -obj-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress_tc2.o diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c deleted file mode 100644 index ba3278a199..0000000000 --- a/board/armltd/vexpress/vexpress_common.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - */ -#include <common.h> -#include <bootstage.h> -#include <cpu_func.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/arch/systimer.h> -#include <asm/arch/sysctrl.h> -#include <asm/arch/wdt.h> -#include "../drivers/mmc/arm_pl180_mmci.h" - -static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; -static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; - -static void flash__init(void); -static void vexpress_timer_init(void); -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -static inline void delay(ulong loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_init(void) -{ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; - - icache_enable(); - flash__init(); - vexpress_timer_init(); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -int cpu_mmc_init(struct bd_info *bis) -{ - int rc = 0; - (void) bis; -#ifdef CONFIG_ARM_PL180_MMCI - struct pl180_mmc_host *host; - struct mmc *mmc; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - strcpy(host->name, "MMC"); - host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; - host->pwr_init = INIT_PWR; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; - host->voltages = VOLTAGE_WINDOW_MMC; - host->caps = 0; - host->clock_in = ARM_MCLK; - host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); - host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; - rc = arm_pl180_mmci_init(host, &mmc); -#endif - return rc; -} - -static void flash__init(void) -{ - /* Setup the sytem control register to allow writing to flash */ - writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, - &sysctrl_base->scflashctrl); -} - -int dram_init(void) -{ - gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = - get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -/* - * Start timer: - * Setup a 32 bit timer, running at 1KHz - * Versatile Express Motherboard provides 1 MHz timer - */ -static void vexpress_timer_init(void) -{ - /* - * Set clock frequency in system controller: - * VEXPRESS_REFCLK is 32KHz - * VEXPRESS_TIMCLK is 1MHz - */ - writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | - SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | - readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); - - /* - * Set Timer0 to be: - * Enabled, free running, no interrupt, 32-bit, wrapping - */ - writel(SYSTIMER_RELOAD, &systimer_base->timer0load); - writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT | - readl(&systimer_base->timer0control), - &systimer_base->timer0control); -} - -int v2m_cfg_write(u32 devfn, u32 data) -{ - /* Configuration interface broken? */ - u32 val; - - devfn |= SYS_CFG_START | SYS_CFG_WRITE; - - val = readl(V2M_SYS_CFGSTAT); - writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); - - writel(data, V2M_SYS_CFGDATA); - writel(devfn, V2M_SYS_CFGCTRL); - - do { - val = readl(V2M_SYS_CFGSTAT); - } while (val == 0); - - return !!(val & SYS_CFG_ERR); -} - -/* Use the ARM Watchdog System to cause reset */ -void reset_cpu(void) -{ - if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) - printf("Unable to reboot\n"); -} - -void lowlevel_init(void) -{ -} - -ulong get_board_rev(void){ - return readl((u32 *)SYS_ID); -} - -#ifdef CONFIG_ARMV7_NONSEC -/* Setting the address at which secondary cores start from. - * Versatile Express uses one address for all cores, so ignore corenr - */ -void smp_set_core_boot_addr(unsigned long addr, int corenr) -{ - /* The SYSFLAGS register on VExpress needs to be cleared first - * by writing to the next address, since any writes to the address - * at offset 0 will only be ORed in - */ - writel(~0, CONFIG_SYSFLAGS_ADDR + 4); - writel(addr, CONFIG_SYSFLAGS_ADDR); -} -#endif diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c deleted file mode 100644 index 8ee24bdde7..0000000000 --- a/board/armltd/vexpress/vexpress_tc2.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Linaro - * Jon Medhurst <tixy@linaro.org> - * - * TC2 specific code for Versatile Express. - */ - -#include <asm/armv7.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include <common.h> -#include <linux/libfdt.h> - -#define SCC_BASE 0x7fff0000 - -bool armv7_boot_nonsec_default(void) -{ -#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT - return false; -#else - /* - * The Serial Configuration Controller (SCC) register at address 0x700 - * contains flags for configuring the behaviour of the Boot Monitor - * (which CPUs execute from reset). Two of these bits are of interest: - * - * bit 12 = Use per-cpu mailboxes for power management - * bit 13 = Power down the non-boot cluster - * - * It is only when both of these are false that U-Boot's current - * implementation of 'nonsec' mode can work as expected because we - * rely on getting all CPUs to execute _nonsec_init, so let's check that. - */ - return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; -#endif -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *fdt, struct bd_info *bd) -{ - int offset, tmp, len; - const struct fdt_property *prop; - const char *cci_compatible = "arm,cci-400-ctrl-if"; - -#ifdef CONFIG_ARMV7_NONSEC - if (!armv7_boot_nonsec()) - return 0; -#else - return 0; -#endif - /* Booting in nonsec mode, disable CCI access */ - offset = fdt_path_offset(fdt, "/cpus"); - if (offset < 0) { - printf("couldn't find /cpus\n"); - return offset; - } - - /* delete cci-control-port in each cpu node */ - for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0; - tmp = fdt_next_subnode(fdt, tmp)) - fdt_delprop(fdt, tmp, "cci-control-port"); - - /* disable all ace cci slave ports */ - offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", - cci_compatible, 20); - while (offset > 0) { - prop = fdt_get_property(fdt, offset, "interface-type", - &len); - if (!prop) - continue; - if (len < 4) - continue; - if (strcmp(prop->data, "ace")) - continue; - - fdt_setprop_string(fdt, offset, "status", "disabled"); - - offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", - cci_compatible, 20); - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig deleted file mode 100644 index 4ccb60a97f..0000000000 --- a/board/bachmann/ot1200/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OT1200 - -config SYS_BOARD - default "ot1200" - -config SYS_VENDOR - default "bachmann" - -config SYS_CONFIG_NAME - default "ot1200" - -endif diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS deleted file mode 100644 index ad75c24ee4..0000000000 --- a/board/bachmann/ot1200/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BACHMANN ELECTRONIC OT1200 BOARD -M: Christian Gmeiner <christian.gmeiner@gmail.com> -S: Maintained -F: board/bachmann/ot1200 -F: include/configs/ot1200.h -F: configs/ot1200*_defconfig diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile deleted file mode 100644 index 73000e3d3c..0000000000 --- a/board/bachmann/ot1200/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de> -# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. -# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> - -ifdef CONFIG_SPL_BUILD -obj-y := ot1200.o ot1200_spl.o -else -obj-y := ot1200.o -endif diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README deleted file mode 100644 index c03d44e458..0000000000 --- a/board/bachmann/ot1200/README +++ /dev/null @@ -1,20 +0,0 @@ -U-Boot for the Bachmann electronic GmbH OT1200 devices - -There are two different versions of the base board, which differ -in the way ethernet is done. The variant detection is done during -runtime based on the address of the found phy. - -- "mr" variant -FEC is connected directly to an ethernet switch (KSZ8895). The ethernet -port is always up and auto-negotiation is not possible. - -- normal variant -FEC is connected to a normal phy and auto-negotiation is possible. - - -The variant name is part of the dtb file name loaded by u-boot. This -make is possible to boot the linux kernel and make use variant specific -devicetree (fixed-phy link). - -In order to support different display resoltuions/sizes the OT1200 devices -are making use of EDID data stored in an i2c EEPROM. diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg deleted file mode 100644 index f4f605fc8d..0000000000 --- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7974 -DATA 4 0x021b0010 0xDB538F64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005A1023 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0x831A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19308030 -DATA 4 0x021b001c 0x19308038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4 0x020c4060 0x000000fb diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c deleted file mode 100644 index 69d1b106b0..0000000000 --- a/board/bachmann/ot1200/ot1200.c +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2014, Bachmann electronic GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <env.h> -#include <malloc.h> -#include <asm/arch/mx6-pins.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/sys_proto.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <netdev.h> -#include <i2c.h> -#include <pca953x.h> -#include <asm/gpio.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ - PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ - PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ - PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), -}; - -static void setup_iomux_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; -} - -static iomux_v3_cfg_t const feature_pads[] = { - /* SD card detect */ - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), - - /* eMMC soldered? */ - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), -}; - -static void setup_iomux_features(void) -{ - imx_iomux_v3_setup_multiple_pads(feature_pads, - ARRAY_SIZE(feature_pads)); -} - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C2 - EEPROM */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - -/* I2C3 - IO expander */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -static void setup_iomux_i2c(void) -{ - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -} - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC33, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -int board_early_init_f(void) -{ - ccgr_init(); - gpr_init(); - - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_i2c(); - setup_iomux_features(); - - return 0; -} - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(4, 5)); - ret = gpio_get_value(IMX_GPIO_NR(4, 5)); - } else { - gpio_direction_input(IMX_GPIO_NR(1, 5)); - ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); - } - - return ret; -} - -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - -static void leds_on(void) -{ - /* turn on all possible leds connected via GPIO expander */ - i2c_set_bus_num(2); - pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); - pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); -} - -static void backlight_lcd_off(void) -{ - unsigned gpio = IMX_GPIO_NR(2, 0); - gpio_direction_output(gpio, 0); - - gpio = IMX_GPIO_NR(2, 3); - gpio_direction_output(gpio, 0); -} - -int board_eth_init(struct bd_info *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - setup_iomux_enet(); - - bus = fec_get_miibus(base, -1); - if (!bus) - return -EINVAL; - - /* scan phy 0 and 5 */ - phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - ret = -EINVAL; - goto free_bus; - } - - /* depending on the phy address we can detect our board version */ - if (phydev->addr == 0) - env_set("boardver", ""); - else - env_set("boardver", "mr"); - - printf("using phy at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) - goto free_phydev; - - return 0; - -free_phydev: - free(phydev); -free_bus: - free(bus); - return ret; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - backlight_lcd_off(); - - leds_on(); - -#ifdef CONFIG_SATA - setup_sata(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: "CONFIG_SYS_BOARD"\n"); - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c deleted file mode 100644 index 7fbd6f2c5d..0000000000 --- a/board/bachmann/ot1200/ot1200_spl.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015, Bachmann electronic GmbH - */ - -#include <common.h> -#include <init.h> -#include <spl.h> -#include <asm/arch/mx6-ddr.h> - -/* Configure MX6Q/DUAL mmdc DDR io registers */ -static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ - .dram_sdclk_0 = 0x00000028, - .dram_sdclk_1 = 0x00000028, - .dram_cas = 0x00000028, - .dram_ras = 0x00000028, - .dram_reset = 0x00000028, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 48 ohm */ - .dram_sdodt0 = 0x00000028, - .dram_sdodt1 = 0x00000028, - /* SDQS[0:7]: Differential input, 48 ohm */ - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_sdqs2 = 0x00000028, - .dram_sdqs3 = 0x00000028, - .dram_sdqs4 = 0x00000028, - .dram_sdqs5 = 0x00000028, - .dram_sdqs6 = 0x00000028, - .dram_sdqs7 = 0x00000028, - /* DQM[0:7]: Differential input, 48 ohm */ - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_dqm2 = 0x00000028, - .dram_dqm3 = 0x00000028, - .dram_dqm4 = 0x00000028, - .dram_dqm5 = 0x00000028, - .dram_dqm6 = 0x00000028, - .dram_dqm7 = 0x00000028, -}; - -/* Configure MX6Q/DUAL mmdc GRP io registers */ -static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - /* Disable DDR pullups */ - .grp_ddrpke = 0x00000000, - /* ADDR[00:16], SDBA[0:1]: 48 ohm */ - .grp_addds = 0x00000028, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */ - .grp_ctlds = 0x00000028, - /* DATA[00:63]: Differential input, 48 ohm */ - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_b2ds = 0x00000028, - .grp_b3ds = 0x00000028, - .grp_b4ds = 0x00000028, - .grp_b5ds = 0x00000028, - .grp_b6ds = 0x00000028, - .grp_b7ds = 0x00000028, -}; - -static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { - /* Width of data bus: 0=16, 1=32, 2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* Single chip select */ - .ncs = 1, - .cs1_mirror = 0, /* war 0 */ - .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */ - .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg micron_2gib_1600 = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, -}; - -static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00260025, - .p0_mpwldectrl1 = 0x00270021, - .p1_mpwldectrl0 = 0x00180034, - .p1_mpwldectrl1 = 0x00180024, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x04380344, - .p0_mpdgctrl1 = 0x0330032C, - .p1_mpdgctrl0 = 0x0338033C, - .p1_mpdgctrl1 = 0x032C0300, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C2E3238, - .p1_mprddlctl = 0x3A2E303C, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36384036, - .p1_mpwrdlctl = 0x442E4438, -}; - -static void ot1200_spl_dram_init(void) -{ - mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs); - mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib, - µn_2gib_1600); -} - -/* - * called from C runtime startup code (arch/arm/lib/crt0.S:_main) - * - we have a stack and a place to store GD, both in SRAM - * - no variable global data is available - */ -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* configure MMDC for SDRAM width/size and per-model calibration */ - ot1200_spl_dram_init(); -} diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig deleted file mode 100644 index cc0648cd73..0000000000 --- a/board/barco/platinum/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_PLATINUM_PICON - -config SYS_CPU - default "armv7" - -config SYS_VENDOR - default "barco" - -config SYS_BOARD - default "platinum" - -config SYS_CONFIG_NAME - default "platinum_picon" - -endif - -if TARGET_PLATINUM_TITANIUM - -config SYS_CPU - default "armv7" - -config SYS_VENDOR - default "barco" - -config SYS_BOARD - default "platinum" - -config SYS_CONFIG_NAME - default "platinum_titanium" - -endif diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS deleted file mode 100644 index a22584b5e5..0000000000 --- a/board/barco/platinum/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PLATINUM BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/barco/platinum/ -F: include/configs/platinum.h -F: configs/platinum_picon_defconfig -F: configs/platinum_titanium_defconfig diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile deleted file mode 100644 index 1e1bf101a8..0000000000 --- a/board/barco/platinum/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014, Barco (www.barco.com) - -obj-y := platinum.o -obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o -obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o - -ifneq ($(CONFIG_SPL_BUILD),) -obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o -obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o -endif diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c deleted file mode 100644 index ec8d552888..0000000000 --- a/board/barco/platinum/platinum.c +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Barco (www.barco.com) - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - */ - -#include <common.h> -#include <init.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <net.h> -#include <netdev.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> - -#include "platinum.h" - -DECLARE_GLOBAL_DATA_PTR; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -struct fsl_esdhc_cfg usdhc_cfg[] = { - { USDHC3_BASE_ADDR }, -}; - -void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -int board_ehci_hcd_init(int port) -{ - return 0; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { - unsigned sd3_cd = IMX_GPIO_NR(7, 0); - gpio_direction_input(sd3_cd); - return !gpio_get_value(sd3_cd); - } - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -void board_init_gpio(void) -{ - platinum_init_gpio(); -} - -void board_init_gpmi_nand(void) -{ - setup_gpmi_nand(); -} - -void board_init_i2c(void) -{ - platinum_setup_i2c(); -} - -void board_init_spi(void) -{ - platinum_setup_spi(); -} - -void board_init_uart(void) -{ - platinum_setup_uart(); -} - -void board_init_usb(void) -{ - platinum_init_usb(); -} - -void board_init_finished(void) -{ - platinum_init_finished(); -} - -int board_phy_config(struct phy_device *phydev) -{ - return platinum_phy_config(phydev); -} - -int board_eth_init(struct bd_info *bis) -{ - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - board_init_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - board_init_spi(); - - board_init_i2c(); - - board_init_gpmi_nand(); - - board_init_gpio(); - - board_init_usb(); - - board_init_finished(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: " CONFIG_PLATINUM_BOARD "\n"); - return 0; -} - -static const struct boot_mode board_boot_modes[] = { - /* NAND */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - /* 4 bit bus width */ - { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, - { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, - { NULL, 0 }, -}; - -int misc_init_r(void) -{ - add_board_boot_modes(board_boot_modes); - - return 0; -} diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h deleted file mode 100644 index 9988caec12..0000000000 --- a/board/barco/platinum/platinum.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - */ - -#ifndef _PLATINUM_H_ -#define _PLATINUM_H_ - -#include <miiphy.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> - -/* Defines */ - -#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) -#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) -#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ - PAD_CTL_HYS) -#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) -#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ - PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_SLOW) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ - PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ - PAD_CTL_HYS) - - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) - -/* Prototypes */ - -int platinum_setup_enet(void); -int platinum_setup_i2c(void); -int platinum_setup_spi(void); -int platinum_setup_uart(void); -int platinum_phy_config(struct phy_device *phydev); -int platinum_init_gpio(void); -int platinum_init_usb(void); -int platinum_init_finished(void); - -static inline void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -#endif /* _PLATINUM_H_ */ diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c deleted file mode 100644 index 3fc29f9e08..0000000000 --- a/board/barco/platinum/platinum_picon.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Barco (www.barco.com) - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - */ - -#include <common.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <i2c.h> -#include <miiphy.h> -#include <linux/delay.h> - -#include "platinum.h" - -#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) -#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) -#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) - -#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) -#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) -#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) - -#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) -#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) -#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) - -#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) - -iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), - MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), - MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), -}; - -iomux_v3_cfg_t const ecspi2_pads[] = { - MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), - MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), - MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), - MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), - MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -/* PHY nRESET */ -iomux_v3_cfg_t const phy_reset_pad = { - MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart5_pads[] = { - MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const i2c0_mux_pads[] = { - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const i2c2_mux_pads[] = { - MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -/* - * This enet related pin-muxing and GPIO handling is done - * in SPL U-Boot. For early initialization. And to give the - * PHY some time to come out of reset before the U-Boot - * ethernet driver tries to access its registers via MDIO. - */ -int platinum_setup_enet(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - unsigned phy_reset = IMX_GPIO_NR(1, 19); - - /* First configure PHY reset GPIO pin */ - imx_iomux_v3_setup_pad(phy_reset_pad); - - /* Reconfigure enet muxing while PHY is in reset */ - gpio_direction_output(phy_reset, 0); - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - mdelay(10); - gpio_set_value(phy_reset, 1); - udelay(100); - - /* set GPIO_16 as ENET_REF_CLK_OUT */ - setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - return enable_fec_anatop_clock(0, ENET_50MHZ); -} - -int platinum_setup_i2c(void) -{ - imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, - ARRAY_SIZE(i2c0_mux_pads)); - imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, - ARRAY_SIZE(i2c2_mux_pads)); - - mdelay(10); - - /* Disable i2c mux 0 */ - gpio_direction_output(GPIO_I2C0_SEL0, 0); - gpio_direction_output(GPIO_I2C0_SEL1, 0); - gpio_direction_output(GPIO_I2C0_ENBN, 1); - - /* Disable i2c mux 1 */ - gpio_direction_output(GPIO_I2C2_SEL0, 0); - gpio_direction_output(GPIO_I2C2_SEL1, 0); - gpio_direction_output(GPIO_I2C2_ENBN, 1); - - udelay(10); - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - /* Disable all leds */ - i2c_set_bus_num(0); - i2c_reg_write(0x60, 0x05, 0x55); - - return 0; -} - -int platinum_setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); - - return 0; -} - -int platinum_setup_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); - imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); - - return 0; -} - -int platinum_phy_config(struct phy_device *phydev) -{ - /* Use generic infrastructure, no specific setup */ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int platinum_init_gpio(void) -{ - /* Reset FPGA's */ - gpio_direction_output(GPIO_IP_NCONFIG, 0); - gpio_direction_output(GPIO_HK_NCONFIG, 0); - gpio_direction_output(GPIO_LS_NCONFIG, 0); - udelay(3); - gpio_set_value(GPIO_IP_NCONFIG, 1); - gpio_set_value(GPIO_HK_NCONFIG, 1); - gpio_set_value(GPIO_LS_NCONFIG, 1); - - /* no dmd configuration yet */ - - return 0; -} - -int platinum_init_usb(void) -{ - /* Reset usb hub */ - gpio_direction_output(GPIO_USB_RESET, 0); - udelay(100); - gpio_set_value(GPIO_USB_RESET, 1); - - return 0; -} - -int platinum_init_finished(void) -{ - /* Enable led 0 */ - i2c_set_bus_num(0); - i2c_reg_write(0x60, 0x05, 0x54); - - return 0; -} diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c deleted file mode 100644 index 9f7c93b4d5..0000000000 --- a/board/barco/platinum/platinum_titanium.c +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Barco (www.barco.com) - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - */ - -#include <common.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <miiphy.h> -#include <micrel.h> -#include <linux/delay.h> - -#include "platinum.h" - -iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), - /* non mounted spi nor flash for booting */ - MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), - MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), -}; - -iomux_v3_cfg_t const ecspi2_pads[] = { - MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), - MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), - MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), - MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), -}; - -iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -/* - * This enet related pin-muxing and GPIO handling is done - * in SPL U-Boot. For early initialization. And to give the - * PHY some time to come out of reset before the U-Boot - * ethernet driver tries to access its registers via MDIO. - */ -int platinum_setup_enet(void) -{ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); - - /* Need delay 10ms according to KSZ9021 spec */ - mdelay(10); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - udelay(100); - - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); - - return 0; -} - -int platinum_setup_i2c(void) -{ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - return 0; -} - -int platinum_setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); - - return 0; -} - -int platinum_setup_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); - - return 0; -} - -int platinum_phy_config(struct phy_device *phydev) -{ - /* min rx data delay */ - ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - /* min tx data delay */ - ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - /* max rx/tx clock delay, min rx/tx control */ - ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int platinum_init_gpio(void) -{ - /* Default GPIO's */ - /* Toggle CONFIG_n to reset fpga on every boot */ - gpio_direction_output(IMX_GPIO_NR(5, 18), 0); - /* Need delay >=2uS */ - udelay(3); - gpio_set_value(IMX_GPIO_NR(5, 18), 1); - - /* Default pin 1,15 high - DLP_FLASH_WPZ */ - gpio_direction_output(IMX_GPIO_NR(1, 15), 1); - - return 0; -} - -int platinum_init_usb(void) -{ - return 0; -} - -int platinum_init_finished(void) -{ - return 0; -} diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c deleted file mode 100644 index 253a64d28e..0000000000 --- a/board/barco/platinum/spl_picon.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - * - * Based on: gw_ventana_spl.c which is: - * Copyright (C) 2014 Gateworks Corporation - */ - -#include <common.h> -#include <i2c.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <spl.h> - -#include "platinum.h" - -#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ - -/* Configure MX6Q/DUAL mmdc DDR io registers */ -struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -/* Configure MX6Q/DUAL mmdc GRP io registers */ -struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - /* disable DDR pullups */ - .grp_ddrpke = 0x00000000, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = 0x00000030, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = 0x00000030, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -/* MT41K256M16HA-125 */ -static struct mx6_ddr3_cfg mt41k256m16ha_125 = { - .mem_speed = 1600, - .density = 4, /* 4Gbit */ - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* - * Values from running the Freescale DDR stress tool via USB - */ -static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x0044004E, - .p0_mpwldectrl1 = 0x001F0023, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x02480248, - .p0_mpdgctrl1 = 0x0210021C, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x42444444, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36322C32, -}; - -static void spl_dram_init(int width) -{ - struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = width / 32, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 1, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ -#ifdef RTT_NOM_120OHM - .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ -#else - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ -#endif - .walat = 0, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); -} - -/* - * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) - * - we have a stack and a place to store GD, both in SRAM - * - no variable global data is available - */ -void board_init_f(ulong dummy) -{ - /* Setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* UART iomux */ - board_early_init_f(); - - /* Setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Init DDR with 32bit width */ - spl_dram_init(32); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* - * Setup enet related MUXing early to give the PHY - * some time to wake-up from reset - */ - platinum_setup_enet(); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c deleted file mode 100644 index 8c91b752ff..0000000000 --- a/board/barco/platinum/spl_titanium.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> - * - * Based on: gw_ventana_spl.c which is: - * Copyright (C) 2014 Gateworks Corporation - */ - -#include <common.h> -#include <i2c.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <spl.h> - -#include "platinum.h" - -#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ - -/* Configure MX6Q/DUAL mmdc DDR io registers */ -struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -/* Configure MX6Q/DUAL mmdc GRP io registers */ -struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - /* disable DDR pullups */ - .grp_ddrpke = 0x00000000, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = 0x00000030, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = 0x00000030, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -/* MT41J128M16JT-125 */ -static struct mx6_ddr3_cfg mt41j128m16jt_125 = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { - /* Write leveling calibration determine */ - .p0_mpwldectrl0 = 0x001f001f, - .p0_mpwldectrl1 = 0x001f001f, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x434b0350, - .p0_mpdgctrl1 = 0x034c0359, - .p1_mpdgctrl0 = 0x434b0350, - .p1_mpdgctrl1 = 0x03650348, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x4436383b, - .p1_mprddlctl = 0x39393341, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254a36, -}; - -static void spl_dram_init(int width) -{ - struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = width / 32, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 1, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ -#ifdef RTT_NOM_120OHM - .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ -#else - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ -#endif - .walat = 0, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); -} - -/* - * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) - * - we have a stack and a place to store GD, both in SRAM - * - no variable global data is available - */ -void board_init_f(ulong dummy) -{ - /* Setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* UART iomux */ - board_early_init_f(); - - /* Setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Init DDR with 32bit width */ - spl_dram_init(32); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* - * Setup enet related MUXing early to give the PHY - * some time to wake-up from reset - */ - platinum_setup_enet(); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig deleted file mode 100644 index 21bc36e004..0000000000 --- a/board/barco/titanium/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TITANIUM - -config SYS_BOARD - default "titanium" - -config SYS_VENDOR - default "barco" - -config SYS_CONFIG_NAME - default "titanium" - -endif diff --git a/board/barco/titanium/MAINTAINERS b/board/barco/titanium/MAINTAINERS deleted file mode 100644 index 7e9913ffa6..0000000000 --- a/board/barco/titanium/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TITANIUM BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/barco/titanium/ -F: include/configs/titanium.h -F: configs/titanium_defconfig diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile deleted file mode 100644 index 6bc5c134f6..0000000000 --- a/board/barco/titanium/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := titanium.o diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg deleted file mode 100644 index 1fc26ed2c9..0000000000 --- a/board/barco/titanium/imximage.cfg +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Projectiondesign AS - * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg - * - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * sd, nand - */ -BOOT_FROM nand - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c deleted file mode 100644 index efd1dc35ef..0000000000 --- a/board/barco/titanium/titanium.c +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Stefan Roese <sr@denx.de> - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/boot_mode.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <micrel.h> -#include <miiphy.h> -#include <netdev.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} - -static void setup_iomux_enet(void) -{ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); - - /* Need delay 10ms according to KSZ9021 spec */ - udelay(1000 * 10); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - return 0; -} - -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[1] = { - { USDHC3_BASE_ADDR }, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - return !gpio_get_value(IMX_GPIO_NR(7, 0)); - } - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - /* - * Only one USDHC controller on titianium - */ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ - /* min rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); - /* min tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); - /* max rx/tx clock delay, min rx/tx control */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - setup_gpmi_nand(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: Titanium\n"); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* NAND */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - /* 4 bit bus width */ - { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, - { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, - { NULL, 0 }, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} diff --git a/board/broadcom/bcm23550_w1d/Kconfig b/board/broadcom/bcm23550_w1d/Kconfig deleted file mode 100644 index 007a127250..0000000000 --- a/board/broadcom/bcm23550_w1d/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCM23550_W1D - -config SYS_BOARD - default "bcm23550_w1d" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "bcm235xx" - -config SYS_CONFIG_NAME - default "bcm23550_w1d" - -endif diff --git a/board/broadcom/bcm23550_w1d/MAINTAINERS b/board/broadcom/bcm23550_w1d/MAINTAINERS deleted file mode 100644 index bde6337ce3..0000000000 --- a/board/broadcom/bcm23550_w1d/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM23550_W1D BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcm23550_w1d/ -F: include/configs/bcm23550_w1d.h -F: configs/bcm23550_w1d_defconfig diff --git a/board/broadcom/bcm23550_w1d/Makefile b/board/broadcom/bcm23550_w1d/Makefile deleted file mode 100644 index 0552f3762e..0000000000 --- a/board/broadcom/bcm23550_w1d/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Broadcom Corporation. - -obj-y += bcm23550_w1d.o diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c deleted file mode 100644 index 90685c072a..0000000000 --- a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <env.h> -#include <mmc.h> -#include <asm/kona-common/kona_sdhci.h> -#include <asm/kona-common/clk.h> -#include <asm/arch/sysmap.h> - -#include <usb.h> -#include <usb/dwc2_udc.h> -#include <g_dnl.h> - -#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 -#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 -#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 -#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 -#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 - -#ifndef CONFIG_USB_SERIALNO -#define CONFIG_USB_SERIALNO "1234567890" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * board_init - early hardware init - */ -int board_init(void) -{ - printf("Relocation Offset is: %08lx\n", gd->reloc_off); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - clk_init(); - - return 0; -} - -/* - * misc_init_r - miscellaneous platform dependent initializations - */ -int misc_init_r(void) -{ - return 0; -} - -/* - * dram_init - sets uboots idea of sdram size - */ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -/* This is called after dram_init() so use get_ram_size result */ -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - -#ifdef CONFIG_MMC_SDHCI_KONA -/* - * mmc_init - Initializes mmc - */ -int board_mmc_init(struct bd_info *bis) -{ - int ret = 0; - - /* Register eMMC - SDIO2 */ - ret = kona_sdhci_init(1, 400000, 0); - if (ret) - return ret; - - /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ - ret = kona_sdhci_init(3, 400000, 0); - return ret; -} -#endif - -#ifdef CONFIG_USB_GADGET -static struct dwc2_plat_otg_data bcm_otg_data = { - .regs_otg = HSOTG_BASE_ADDR -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - debug("%s: performing dwc2_udc_probe\n", __func__); - return dwc2_udc_probe(&bcm_otg_data); -} - -int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -{ - debug("%s\n", __func__); - if (!env_get("serial#")) - g_dnl_set_serialnumber(CONFIG_USB_SERIALNO); - return 0; -} - -int g_dnl_get_board_bcd_device_number(int gcnum) -{ - debug("%s\n", __func__); - return 1; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - debug("%s\n", __func__); - return 0; -} -#endif diff --git a/board/broadcom/bcm28155_ap/Kconfig b/board/broadcom/bcm28155_ap/Kconfig deleted file mode 100644 index f1b4e08941..0000000000 --- a/board/broadcom/bcm28155_ap/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCM28155_AP - -config SYS_BOARD - default "bcm28155_ap" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "bcm281xx" - -config SYS_CONFIG_NAME - default "bcm28155_ap" - -endif diff --git a/board/broadcom/bcm28155_ap/MAINTAINERS b/board/broadcom/bcm28155_ap/MAINTAINERS deleted file mode 100644 index e1e99d0784..0000000000 --- a/board/broadcom/bcm28155_ap/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM28155_AP BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcm28155_ap/ -F: include/configs/bcm28155_ap.h -F: configs/bcm28155_ap_defconfig diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile deleted file mode 100644 index 06eba8fbfd..0000000000 --- a/board/broadcom/bcm28155_ap/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Broadcom Corporation. - -obj-y += bcm28155_ap.o diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c deleted file mode 100644 index 43726f79bd..0000000000 --- a/board/broadcom/bcm28155_ap/bcm28155_ap.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <env.h> -#include <mmc.h> -#include <asm/kona-common/kona_sdhci.h> -#include <asm/kona-common/clk.h> -#include <asm/arch/sysmap.h> - -#include <usb.h> -#include <usb/dwc2_udc.h> -#include <g_dnl.h> - -#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 -#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 -#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 -#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 -#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 - -#ifndef CONFIG_USB_SERIALNO -#define CONFIG_USB_SERIALNO "1234567890" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * board_init - early hardware init - */ -int board_init(void) -{ - printf("Relocation Offset is: %08lx\n", gd->reloc_off); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - clk_init(); - - return 0; -} - -/* - * misc_init_r - miscellaneous platform dependent initializations - */ -int misc_init_r(void) -{ - /* Disable watchdog reset - watchdog unused */ - writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) | - (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) | - (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) | - (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT), - (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET)); - - return 0; -} - -/* - * dram_init - sets uboots idea of sdram size - */ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -/* This is called after dram_init() so use get_ram_size result */ -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - -#ifdef CONFIG_MMC_SDHCI_KONA -/* - * mmc_init - Initializes mmc - */ -int board_mmc_init(struct bd_info *bis) -{ - int ret = 0; - - /* Register eMMC - SDIO2 */ - ret = kona_sdhci_init(1, 400000, 0); - if (ret) - return ret; - - /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ - ret = kona_sdhci_init(3, 400000, 0); - return ret; -} -#endif - -#ifdef CONFIG_USB_GADGET -static struct dwc2_plat_otg_data bcm_otg_data = { - .regs_otg = HSOTG_BASE_ADDR -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - debug("%s: performing dwc2_udc_probe\n", __func__); - return dwc2_udc_probe(&bcm_otg_data); -} - -int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -{ - debug("%s\n", __func__); - if (!env_get("serial#")) - g_dnl_set_serialnumber(CONFIG_USB_SERIALNO); - return 0; -} - -int g_dnl_get_board_bcd_device_number(int gcnum) -{ - debug("%s\n", __func__); - return 1; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - debug("%s\n", __func__); - return 0; -} -#endif diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS deleted file mode 100644 index 8b831d8cb7..0000000000 --- a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM911360_ENTPHN-NS BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm911360_entphn-ns_defconfig diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS deleted file mode 100644 index d4f6aefe48..0000000000 --- a/board/broadcom/bcm911360_entphn/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM911360_ENTPHN BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm911360_entphn_defconfig diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS deleted file mode 100644 index 32e60327cf..0000000000 --- a/board/broadcom/bcm911360k/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM911360K BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm911360k_defconfig diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS deleted file mode 100644 index 237d344629..0000000000 --- a/board/broadcom/bcm958300k-ns/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958300K-NS BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm958300k-ns_defconfig diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS deleted file mode 100644 index bbb6d64e1f..0000000000 --- a/board/broadcom/bcm958300k/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958300K BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm958300k_defconfig diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS deleted file mode 100644 index 5ca0effc00..0000000000 --- a/board/broadcom/bcm958305k/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958305K BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmcygnus/ -F: include/configs/bcm_ep_board.h -F: configs/bcm958305k_defconfig diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS deleted file mode 100644 index de44dd1159..0000000000 --- a/board/broadcom/bcm958622hr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958622HR BOARD -M: Steve Rae <steve.rae@raedomain.com> -S: Maintained -F: board/broadcom/bcmnsp/ -F: include/configs/bcm_ep_board.h -F: configs/bcm958622hr_defconfig diff --git a/board/broadcom/bcm958712k/MAINTAINERS b/board/broadcom/bcm958712k/MAINTAINERS deleted file mode 100644 index 024fb1447d..0000000000 --- a/board/broadcom/bcm958712k/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958712K BOARD -M: Jon Mason <jon.mason@broadcom.com> -S: Maintained -F: board/broadcom/bcmns2/ -F: include/configs/bcm_northstar2.h -F: configs/bcm958712k_defconfig diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig deleted file mode 100644 index faba4cf82b..0000000000 --- a/board/broadcom/bcmcygnus/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCMCYGNUS - -config SYS_BOARD - default "bcm_ep" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "bcmcygnus" - -config SYS_CONFIG_NAME - default "bcm_ep_board" - -endif diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig deleted file mode 100644 index 3ac67249c4..0000000000 --- a/board/broadcom/bcmns2/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCMNS2 - -config SYS_BOARD - default "bcmns2" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "ns2" - -config SYS_CONFIG_NAME - default "bcm_northstar2" - -endif diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile deleted file mode 100644 index 29274bd106..0000000000 --- a/board/broadcom/bcmns2/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2016 Broadcom Ltd. - -obj-y := northstar2.o diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c deleted file mode 100644 index ee586d5660..0000000000 --- a/board/broadcom/bcmns2/northstar2.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Broadcom Ltd. - */ -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/cache.h> -#include <asm/global_data.h> -#include <asm/system.h> -#include <asm/armv8/mmu.h> - -static struct mm_region ns2_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = ns2_mem_map; - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -void reset_cpu(void) -{ - psci_system_reset(); -} diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig deleted file mode 100644 index a975082355..0000000000 --- a/board/broadcom/bcmnsp/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCMNSP - -config SYS_BOARD - default "bcm_ep" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "bcmnsp" - -config SYS_CONFIG_NAME - default "bcm_ep_board" - -endif diff --git a/board/ccv/xpress/Kconfig b/board/ccv/xpress/Kconfig deleted file mode 100644 index 9157013c30..0000000000 --- a/board/ccv/xpress/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_XPRESS - -config SYS_BOARD - default "xpress" - -config SYS_VENDOR - default "ccv" - -config SYS_CONFIG_NAME - default "xpress" - -endif diff --git a/board/ccv/xpress/MAINTAINERS b/board/ccv/xpress/MAINTAINERS deleted file mode 100644 index e242bfb206..0000000000 --- a/board/ccv/xpress/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CCV XPRESS BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/ccv/xpress/ -F: include/configs/xpress.h -F: configs/xpress_defconfig -F: configs/xpress_spl_defconfig diff --git a/board/ccv/xpress/Makefile b/board/ccv/xpress/Makefile deleted file mode 100644 index b750b6ae49..0000000000 --- a/board/ccv/xpress/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> - -obj-y := xpress.o -obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg deleted file mode 100644 index b59dc842c1..0000000000 --- a/board/ccv/xpress/imximage.cfg +++ /dev/null @@ -1,175 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * sd, nand - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include <config.h> - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff -DATA 4 0x020c4084 0xffffffff - -/* ddr io type */ -DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ -DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ - -/* clock */ -DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ - -/* control and address */ -DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ -DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ -DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ -DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ -DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be - configured using Group Control Register: - IOMUXC_SW_PAD_CTL_GRP_CTLDS */ -DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ -DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ -DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ - -/* data strobes */ -DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ -DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ -DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ - -/* data */ -DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ -DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ -DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ -DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ -DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ - -/* - * DDR Controller Registers - * - * Manufacturer: IM - * Device Part Number: IME1G16D3EEBG-15EI - * Clock Freq.: 400MHz - * Density per CS in Gb: 1 - * Chip Selects used: 1 - * Number of Banks: 8 - * Row address: 13 - * Column address: 10 - * Data bus width 16 - */ -DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit - during MMDC set up */ - -/* - * Calibration setup - */ -DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & - periodic HW ZQ calibration. */ - -/* - * For target board, may need to run write leveling calibration to fine tune - * these settings. - */ -DATA 4 0x021b080c 0x00000000 - -/* Read DQS Gating calibration */ -DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */ - -/* Read calibration */ -DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */ - -/* Write calibration */ -DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */ - -/* - * read data bit delay: (3 is the reccommended default value, although out of - * reset value is 0) - */ -DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */ -DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */ -DATA 4 0x021b082c 0xF3333333 -DATA 4 0x021b0830 0xF3333333 - -DATA 4 0x021b08c0 0x00921012 - -/* Clock Fine Tuning */ -DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */ - -/* Complete calibration by forced measurement: */ -DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */ -/* - * Calibration setup end - */ - -/* MMDC init: */ -DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */ -DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */ -DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */ -DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */ -DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */ - -/* - * MDMISC: RALAT kept to the high level of 5. - * MDMISC: consider reducing RALAT if your 528MHz board design allow that. - * Lower RALAT benefits: - * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT - * to 3 - * b. Small performence improvment - */ -DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */ - -DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit - during MMDC set up */ - -DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */ -DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */ -DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */ -DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */ - -/* Mode register writes */ -DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */ -DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */ -DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */ -DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */ -DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to - device on CS0 */ - -DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ -DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */ -DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */ -DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will - enter automatically to self-refresh while the - number of idle cycle reached. */ -DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially - the configuration bit as initialization is - complete) */ diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c deleted file mode 100644 index 38bda8d184..0000000000 --- a/board/ccv/xpress/spl.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL specific code for CCV xPress - * - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> - */ - -#include <common.h> -#include <init.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/crm_regs.h> - -/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */ - -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; - -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000030, - .dram_odt1 = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000008, - .dram_sdqs0 = 0x00000038, - .dram_sdqs1 = 0x00000030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0x4164015C, - .p0_mprddlctl = 0x40404446, - .p0_mpwrdlctl = 0x40405A52, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* Setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* Setup iomux and i2c */ - board_early_init_f(); - - /* Setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); -} diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c deleted file mode 100644 index 9f5e78ce68..0000000000 --- a/board/ccv/xpress/xpress.c +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> - */ - -#include <init.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6ul_pins.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <common.h> -#include <env.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <miiphy.h> -#include <mmc.h> -#include <netdev.h> -#include <usb.h> -#include <linux/delay.h> -#include <usb/ehci-ci.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_FAST) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, - .gp = IMX_GPIO_NR(1, 2), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3), - }, -}; - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; - -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC, - .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC, - .gp = IMX_GPIO_NR(1, 20), - }, - .sda = { - .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC, - .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC, - .gp = IMX_GPIO_NR(1, 21), - }, -}; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart5_pads[] = { - MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart7_pads[] = { - MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart8_pads[] = { - MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); - imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); - imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads)); - imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads)); -} - -/* eMMC on USDHC2 */ -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - /* - * RST_B - */ - MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg = { - .esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 8, -}; - -#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9) - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eMMC is always present */ - return 1; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg); -} - -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - /* OTG1 */ - MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), - /* OTG2 */ - MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); -} - -int board_usb_phy_mode(int port) -{ - if (port == 1) - return USB_INIT_HOST; - else - return usb_phy_mode(port); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 1) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - /* Set Power polarity */ - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} - -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), - MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - - /* ENET1 reset */ - MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* ENET1 interrupt */ - MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17) - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - - /* Reset LAN8742 PHY */ - ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); - if (!ret) - gpio_direction_output(ENET_PHY_RESET_GPIO , 0); - mdelay(10); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); - mdelay(10); - - return cpu_eth_init(bis); -} - -static int setup_fec(int fec_id) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - /* - * Use 50M anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); - if (ret) - return ret; - - enable_enet_clk(1); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); - - setup_fec(CONFIG_FEC_ENET_DEV); - - setup_usb(); - - return 0; -} - -static const struct boot_mode board_boot_modes[] = { - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)}, - { NULL, 0 }, -}; - -int board_late_init(void) -{ - add_board_boot_modes(board_boot_modes); - env_set("board_name", "xpress"); - - return 0; -} - -int checkboard(void) -{ - puts("Board: CCV-EVA xPress\n"); - - return 0; -} diff --git a/board/congatec/cgtqmx6eval/Kconfig b/board/congatec/cgtqmx6eval/Kconfig deleted file mode 100644 index 773551baa9..0000000000 --- a/board/congatec/cgtqmx6eval/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CGTQMX6EVAL - -config SYS_BOARD - default "cgtqmx6eval" - -config SYS_VENDOR - default "congatec" - -config SYS_CONFIG_NAME - default "cgtqmx6eval" - -endif diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS deleted file mode 100644 index 48c08891b3..0000000000 --- a/board/congatec/cgtqmx6eval/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CGTQMX6EVAL BOARD -M: Otavio Salvador <otavio@ossystems.com.br> -S: Maintained -F: board/congatec/cgtqmx6eval/ -F: include/configs/cgtqmx6eval.h -F: configs/cgtqmx6eval_defconfig diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile deleted file mode 100644 index 2c45ca0e12..0000000000 --- a/board/congatec/cgtqmx6eval/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com> - -obj-y := cgtqmx6eval.o diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README deleted file mode 100644 index 0777c781c2..0000000000 --- a/board/congatec/cgtqmx6eval/README +++ /dev/null @@ -1,74 +0,0 @@ -U-Boot for the Congatec QMX6 boards - -This file contains information for the port of U-Boot to the Congatec -QMX6 boards. - -1. Building U-Boot ------------------- - -- Build U-Boot for Congatec QMX6 boards: - -$ make mrproper -$ make cgtqmx6eval_defconfig -$ make - -This will generate the following binaries: - -- SPL -- u-boot.img - -2. Flashing U-Boot in the SPI NOR ---------------------------------- - -Copy SPL and u-boot.img to the exported TFTP directory of the -host PC (/tftpboot , for example). - -=> sf probe - -=> setenv serverip <server_ip_address> - -=> setenv ipaddr <board_ip_address> - -=> tftp 0x12000000 SPL - -=> sf erase 0x0 0x10000 - -=> sf write 0x12000000 0x400 0x10000 - -=> tftp 0x12000000 u-boot.img - -=> sf erase 0x10000 0x70000 - -=> sf write 0x12000000 0x10000 0x70000 - -Reboot the board and the new U-Boot should come up. - -3. Booting from the SD card ---------------------------- - -- Flash the SPL image into the SD card: - -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync - -- Flash the u-boot.img image into the SD card: - -sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync - -- Insert the SD card into the big slot. - -The boot medium of Congatec QMX6 boards is the SPI NOR flash, so boot -the board from SPI first. - -It is also possible to boot from the SD card slot by using the 'bmode' -command: - -=> bmode esdhc4 - -And then the U-Boot from the big slot will boot. - -Note: If the "bmode" command is not available from your pre-installed U-Boot, -these instruction will produce the same effect: - -=> mw.l 0x20d8040 0x3850 -=> mw.l 0x020d8044 0x10000000 -=> reset diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c deleted file mode 100644 index 6ae4a1af89..0000000000 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ /dev/null @@ -1,1097 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * Based on mx6qsabrelite.c file - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Leo Sartre, <lsartre@adeneo-embedded.com> - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <env.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <input.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/pfuze100_pmic.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <malloc.h> -#include <miiphy.h> -#include <netdev.h> -#include <micrel.h> -#include <spi_flash.h> -#include <spi.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9) - - -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart2_pads[] = { - IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -#ifndef CONFIG_SPL_BUILD -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; -#endif - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usb_otg_pads[] = { - IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t enet_pads_ksz9031[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t enet_pads_final_ksz9031[] = { - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - -static iomux_v3_cfg_t enet_pads_ar8035[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info mx6q_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -#define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */ - -struct interface_level { - char *name; - uchar value; -}; - -static struct interface_level mipi_levels[] = { - {"0V0", 0x00}, - {"2V5", 0x17}, -}; - -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - u32 id1, id2, i; - int ret; - char const *lv_mipi; - - /* configure I2C multiplexer */ - gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1); - - power_pfuze100_init(I2C_PMIC); - p = pmic_get("PFUZE100"); - if (!p) - return -EINVAL; - - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, &id1); - pmic_reg_read(p, PFUZE100_REVID, &id2); - printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2); - - if (id2 >= 0x20) - return 0; - - /* set level of MIPI if specified */ - lv_mipi = env_get("lv_mipi"); - if (lv_mipi) - return 0; - - for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) { - if (!strcmp(mipi_levels[i].name, lv_mipi)) { - printf("set MIPI level %s\n", mipi_levels[i].name); - ret = pmic_reg_write(p, PFUZE100_VGEN4VOL, - mipi_levels[i].value); - if (ret) - return ret; - } - } - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct phy_device *phydev; - struct mii_dev *bus; - unsigned short id1, id2; - int ret; - - /* check whether KSZ9031 or AR8035 has to be configured */ - SETUP_IOMUX_PADS(enet_pads_ar8035); - - /* phy reset */ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - udelay(2000); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - udelay(500); - - bus = fec_get_miibus(IMX_FEC_BASE, -1); - if (!bus) - return -EINVAL; - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - printf("Error: phy device not found.\n"); - ret = -ENODEV; - goto free_bus; - } - - /* get the PHY id */ - id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); - id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); - - if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { - /* re-configure for Micrel KSZ9031 */ - printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n", - phydev->addr); - - /* phy reset: gpio3-23 */ - gpio_set_value(IMX_GPIO_NR(3, 23), 0); - gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); - gpio_set_value(IMX_GPIO_NR(6, 25), 1); - gpio_set_value(IMX_GPIO_NR(6, 27), 1); - gpio_set_value(IMX_GPIO_NR(6, 28), 1); - gpio_set_value(IMX_GPIO_NR(6, 29), 1); - SETUP_IOMUX_PADS(enet_pads_ksz9031); - gpio_set_value(IMX_GPIO_NR(6, 24), 1); - udelay(500); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - SETUP_IOMUX_PADS(enet_pads_final_ksz9031); - } else if ((id1 == 0x004d) && (id2 == 0xd072)) { - /* configure Atheros AR8035 - actually nothing to do */ - printf("configure Atheros AR8035 Ethernet Phy at address %d\n", - phydev->addr); - } else { - printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2); - ret = -EINVAL; - goto free_phydev; - } - - ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); - if (ret) - goto free_phydev; - - return 0; - -free_phydev: - free(phydev); -free_bus: - free(bus); - return ret; -} - -int mx6_rgmii_rework(struct phy_device *phydev) -{ - unsigned short id1, id2; - unsigned short val; - - /* check whether KSZ9031 or AR8035 has to be configured */ - id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); - id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); - - if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { - /* finalize phy configuration for Micrel KSZ9031 */ - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); - - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG); - - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF); - - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF); - - /* fix KSZ9031 link up issue */ - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80); - } - - if ((id1 == 0x004d) && (id2 == 0xd072)) { - /* enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16); - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7); - val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA); - val &= 0xfe63; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - /* disable hibernation */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40); - } - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - mx6_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart2_pads); -} - -#ifdef CONFIG_MXC_SPI -static void setup_spi(void) -{ - SETUP_IOMUX_PADS(ecspi1_pads); - gpio_direction_output(IMX_GPIO_NR(3, 19), 0); -} -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - gpio_direction_input(IMX_GPIO_NR(1, 4)); - ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - gpio_direction_input(IMX_GPIO_NR(2, 6)); - ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - break; - default: - printf("Bad USDHC interface\n"); - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - int i; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - SETUP_IOMUX_PADS(usdhc2_pads); - SETUP_IOMUX_PADS(usdhc3_pads); - SETUP_IOMUX_PADS(usdhc4_pads); - - for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) { - status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (status) - return status; - } - - return 0; -#else - SETUP_IOMUX_PADS(usdhc4_pads); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif -} -#endif - -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - SETUP_IOMUX_PADS(usb_otg_pads); - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 1); - break; - case 1: - /* nothing to do */ - break; - default: - printf("Invalid USB port: %d\n", port); - return -EINVAL; - } - - return 0; -} - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - break; - case 1: - gpio_direction_output(IMX_GPIO_NR(5, 5), on); - break; - default: - printf("Invalid USB port: %d\n", port); - return -EINVAL; - } - - return 0; -} - -struct display_info_t { - int bus; - int addr; - int pixfmt; - int (*detect)(struct display_info_t const *dev); - void (*enable)(struct display_info_t const *dev); - struct fb_videomode mode; -}; - -static void disable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK | - IOMUXC_GPR2_LVDS_CH1_MODE_MASK); -} - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - disable_lvds(dev); - imx_enable_hdmi_phy(); -} - -static struct display_info_t const displays[] = { -{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = NULL, - .enable = NULL, - .mode = { - .name = - "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED } }, -{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = NULL, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED } } -}; - -int board_video_skip(void) -{ - int i; - int ret; - char const *panel = env_get("panel"); - if (!panel) { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - struct display_info_t const *dev = displays + i; - if (dev->detect && dev->detect(dev)) { - panel = dev->mode.name; - printf("auto-detected panel %s\n", panel); - break; - } - } - if (!panel) { - panel = displays[0].mode.name; - printf("No panel detected: default to %s\n", panel); - i = 0; - } - } else { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - if (!strcmp(panel, displays[i].mode.name)) - break; - } - } - if (i < ARRAY_SIZE(displays)) { - ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt); - if (!ret) { - if (displays[i].enable) - displays[i].enable(displays + i); - printf("Display: %s (%ux%u)\n", - displays[i].mode.name, displays[i].mode.xres, - displays[i].mode.yres); - } else - printf("LCD %s cannot be configured: %d\n", - displays[i].mode.name, ret); - } else { - printf("unsupported panel %s\n", panel); - return -EINVAL; - } - - return 0; -} - -int ipu_displays_init(void) -{ - return board_video_skip(); -} - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK | - MXC_CCM_CCGR3_LDB_DI1_MASK); - - /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | - MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV); - - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | - CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | - IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - - if (is_mx6dq()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); - - setup_display(); - -#ifdef CONFIG_SATA - setup_sata(); -#endif - - return 0; -} - -int checkboard(void) -{ - char *type = "unknown"; - - if (is_cpu_type(MXC_CPU_MX6Q)) - type = "Quad"; - else if (is_cpu_type(MXC_CPU_MX6D)) - type = "Dual"; - else if (is_cpu_type(MXC_CPU_MX6DL)) - type = "Dual-Lite"; - else if (is_cpu_type(MXC_CPU_MX6SOLO)) - type = "Solo"; - - printf("Board: conga-QMX6 %s\n", type); - - return 0; -} - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL; -} -#endif - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)}, - {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_mx6dq()) - env_set("board_rev", "MX6Q"); - else - env_set("board_rev", "MX6DL"); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#include <asm/arch/mx6-ddr.h> -#include <spl.h> -#include <linux/libfdt.h> -#include <spi_flash.h> -#include <spi.h> - -const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00000030, - .dram_sdodt1 = 0x00000030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_dqm4 = 0x00000030, - .dram_dqm5 = 0x00000030, - .dram_dqm6 = 0x00000030, - .dram_dqm7 = 0x00000030, -}; - -static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00000030, - .dram_sdodt1 = 0x00000030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_dqm4 = 0x00000030, - .dram_dqm5 = 0x00000030, - .dram_dqm6 = 0x00000030, - .dram_dqm7 = 0x00000030, -}; - -const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6q_mmcd_calib = { - .p0_mpwldectrl0 = 0x0016001A, - .p0_mpwldectrl1 = 0x0023001C, - .p1_mpwldectrl0 = 0x0028003A, - .p1_mpwldectrl1 = 0x001F002C, - .p0_mpdgctrl0 = 0x43440354, - .p0_mpdgctrl1 = 0x033C033C, - .p1_mpdgctrl0 = 0x43300368, - .p1_mpdgctrl1 = 0x03500330, - .p0_mprddlctl = 0x3228242E, - .p1_mprddlctl = 0x2C2C2636, - .p0_mpwrdlctl = 0x36323A38, - .p1_mpwrdlctl = 0x42324440, -}; - -const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { - .p0_mpwldectrl0 = 0x00080016, - .p0_mpwldectrl1 = 0x001D0016, - .p1_mpwldectrl0 = 0x0018002C, - .p1_mpwldectrl1 = 0x000D001D, - .p0_mpdgctrl0 = 0x43200334, - .p0_mpdgctrl1 = 0x0320031C, - .p1_mpdgctrl0 = 0x0344034C, - .p1_mpdgctrl1 = 0x03380314, - .p0_mprddlctl = 0x3E36383A, - .p1_mprddlctl = 0x38363240, - .p0_mpwrdlctl = 0x36364238, - .p1_mpwrdlctl = 0x4230423E, -}; - -static const struct mx6_mmdc_calibration mx6s_mmcd_calib = { - .p0_mpwldectrl0 = 0x00480049, - .p0_mpwldectrl1 = 0x00410044, - .p0_mpdgctrl0 = 0x42480248, - .p0_mpdgctrl1 = 0x023C023C, - .p0_mprddlctl = 0x40424644, - .p0_mpwrdlctl = 0x34323034, -}; - -const struct mx6_mmdc_calibration mx6dl_mmcd_calib = { - .p0_mpwldectrl0 = 0x0043004B, - .p0_mpwldectrl1 = 0x003A003E, - .p1_mpwldectrl0 = 0x0047004F, - .p1_mpwldectrl1 = 0x004E0061, - .p0_mpdgctrl0 = 0x42500250, - .p0_mpdgctrl1 = 0x0238023C, - .p1_mpdgctrl0 = 0x42640264, - .p1_mpdgctrl1 = 0x02500258, - .p0_mprddlctl = 0x40424846, - .p1_mprddlctl = 0x46484842, - .p0_mpwrdlctl = 0x38382C30, - .p1_mpwrdlctl = 0x34343430, -}; - -static struct mx6_ddr3_cfg mem_ddr_2g = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1310, - .trcmin = 4875, - .trasmin = 3500, -}; - -static struct mx6_ddr3_cfg mem_ddr_4g = { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1310, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -/* Define a minimal structure so that the part number can be read via SPL */ -struct mfgdata { - unsigned char tsize; - /* size of checksummed part in bytes */ - unsigned char ckcnt; - /* checksum corrected byte */ - unsigned char cksum; - /* decimal serial number, packed BCD */ - unsigned char serial[6]; - /* part number, right justified, ASCII */ - unsigned char pn[16]; -}; - -static void conv_ascii(unsigned char *dst, unsigned char *src, int len) -{ - int remain = len; - unsigned char *sptr = src; - unsigned char *dptr = dst; - - while (remain) { - if (*sptr) { - *dptr = *sptr; - dptr++; - } - sptr++; - remain--; - } - *dptr = 0x0; -} - -#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K) -static bool is_2gb(void) -{ - struct spi_flash *spi; - int ret; - char buf[sizeof(struct mfgdata)]; - struct mfgdata *data = (struct mfgdata *)buf; - unsigned char outbuf[32]; - - spi = spi_flash_probe(CONFIG_ENV_SPI_BUS, - CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata), - buf); - if (ret) - return false; - - /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */ - conv_ascii(outbuf, data->pn, sizeof(data->pn)); - if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6)) - return true; - else - return false; -} - -static void spl_dram_init(int width) -{ - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = width / 32, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 2, - .walat = 0, - .ralat = 5, - .mif3_mode = 3, - .bi_on = 1, - .sde_to_rst = 0x0d, - .rst_to_cke = 0x20, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) { - mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); - return; - } - - if (is_mx6dq()) { - mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g); - } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { - sysinfo.walat = 1; - mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g); - } else if (is_cpu_type(MXC_CPU_MX6DL)) { - sysinfo.walat = 1; - mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g); - } -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Needed for malloc() to work in SPL prior to board_init_r() */ - spl_init(); - - /* DDR initialization */ - if (is_cpu_type(MXC_CPU_MX6SOLO)) - spl_dram_init(32); - else - spl_dram_init(64); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig deleted file mode 100644 index 345ac83d48..0000000000 --- a/board/corscience/tricorder/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TRICORDER - -config SYS_BOARD - default "tricorder" - -config SYS_VENDOR - default "corscience" - -config SYS_CONFIG_NAME - default "tricorder" - -endif diff --git a/board/corscience/tricorder/MAINTAINERS b/board/corscience/tricorder/MAINTAINERS deleted file mode 100644 index 8a8171b550..0000000000 --- a/board/corscience/tricorder/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -TRICORDER BOARD -M: Thomas Weber <weber@corscience.de> -S: Maintained -F: board/corscience/tricorder/ -F: include/configs/tricorder.h -F: configs/tricorder_defconfig -F: configs/tricorder_flash_defconfig diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile deleted file mode 100644 index bee39a4f6a..0000000000 --- a/board/corscience/tricorder/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2012 -# Thomas Weber <weber@corscience.de> - -obj-y := tricorder.o tricorder-eeprom.o led.o diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c deleted file mode 100644 index d876dd7b9f..0000000000 --- a/board/corscience/tricorder/led.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2013 Corscience GmbH & Co.KG - * Andreas Bießmann <andreas.biessmann@corscience.de> - */ -#include <common.h> -#include <status_led.h> -#include <twl4030.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> - -#define TRICORDER_STATUS_LED_YELLOW 42 -#define TRICORDER_STATUS_LED_GREEN 43 - -void __led_init(led_id_t mask, int state) -{ - __led_set(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - int toggle_gpio = 0; -#ifdef CONFIG_LED_STATUS0 - if (!toggle_gpio && CONFIG_LED_STATUS_BIT & mask) - toggle_gpio = TRICORDER_STATUS_LED_GREEN; -#endif -#ifdef CONFIG_LED_STATUS1 - if (!toggle_gpio && CONFIG_LED_STATUS_BIT1 & mask) - toggle_gpio = TRICORDER_STATUS_LED_YELLOW; -#endif -#ifdef CONFIG_LED_STATUS2 - if (!toggle_gpio && CONFIG_LED_STATUS_BIT2 & mask) { - uint8_t val; - twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, - &val); - val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM); - twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, - val); - } -#endif - if (toggle_gpio) { - int state; - gpio_request(toggle_gpio, ""); - state = gpio_get_value(toggle_gpio); - gpio_set_value(toggle_gpio, !state); - } -} - -void __led_set(led_id_t mask, int state) -{ -#ifdef CONFIG_LED_STATUS0 - if (CONFIG_LED_STATUS_BIT & mask) { - gpio_request(TRICORDER_STATUS_LED_GREEN, ""); - gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0); - gpio_set_value(TRICORDER_STATUS_LED_GREEN, state); - } -#endif -#ifdef CONFIG_LED_STATUS1 - if (CONFIG_LED_STATUS_BIT1 & mask) { - gpio_request(TRICORDER_STATUS_LED_YELLOW, ""); - gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0); - gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state); - } -#endif -#ifdef CONFIG_LED_STATUS2 - if (CONFIG_LED_STATUS_BIT2 & mask) { - if (CONFIG_LED_STATUS_OFF == state) - twl4030_i2c_write_u8(TWL4030_CHIP_LED, - TWL4030_LED_LEDEN, 0); - else - twl4030_i2c_write_u8(TWL4030_CHIP_LED, - TWL4030_LED_LEDEN, - (TWL4030_LED_LEDEN_LEDAON | - TWL4030_LED_LEDEN_LEDAPWM)); - } -#endif -} diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c deleted file mode 100644 index 192af304d9..0000000000 --- a/board/corscience/tricorder/tricorder-eeprom.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Andreas Bießmann <andreas.biessmann@corscience.de> - */ -#include <common.h> -#include <command.h> -#include <eeprom.h> -#include <i2c.h> -#include <u-boot/crc.h> - -#include "tricorder-eeprom.h" - -static inline void warn_wrong_value(const char *msg, unsigned int a, - unsigned int b) -{ - printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b); -} - -static int handle_eeprom_v0(struct tricorder_eeprom *eeprom) -{ - struct tricorder_eeprom_v0 { - uint32_t magic; - uint16_t length; - uint16_t version; - char board_name[TRICORDER_BOARD_NAME_LENGTH]; - char board_version[TRICORDER_BOARD_VERSION_LENGTH]; - char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; - uint32_t crc32; - } __packed eepromv0; - uint32_t crc; - - printf("Old EEPROM (v0), consider rewrite!\n"); - - if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) { - warn_wrong_value("length", sizeof(eepromv0), - be16_to_cpu(eeprom->length)); - return 1; - } - - memcpy(&eepromv0, eeprom, sizeof(eepromv0)); - - crc = crc32(0L, (unsigned char *)&eepromv0, - sizeof(eepromv0) - sizeof(eepromv0.crc32)); - if (be32_to_cpu(eepromv0.crc32) != crc) { - warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32), - crc); - return 1; - } - - /* Ok the content is correct, do the conversion */ - memset(eeprom->interface_version, 0x0, - TRICORDER_INTERFACE_VERSION_LENGTH); - crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); - eeprom->crc32 = cpu_to_be32(crc); - - return 0; -} - -static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) -{ - uint32_t crc; - - if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) { - warn_wrong_value("length", TRICORDER_EEPROM_SIZE, - be16_to_cpu(eeprom->length)); - return 1; - } - - crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); - if (be32_to_cpu(eeprom->crc32) != crc) { - warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc); - return 1; - } - - return 0; -} - -int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) -{ - unsigned int bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); - - memset(eeprom, 0, TRICORDER_EEPROM_SIZE); - - i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); - i2c_set_bus_num(bus); - - if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { - warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, - be32_to_cpu(eeprom->magic)); - return 1; - } - - switch (be16_to_cpu(eeprom->version)) { - case 0: - return handle_eeprom_v0(eeprom); - case 1: - return handle_eeprom_v1(eeprom); - default: - warn_wrong_value("version", TRICORDER_EEPROM_VERSION, - be16_to_cpu(eeprom->version)); - return 1; - } -} - -#if !defined(CONFIG_SPL) -int tricorder_eeprom_read(unsigned devaddr) -{ - struct tricorder_eeprom eeprom; - int ret = tricorder_get_eeprom(devaddr, &eeprom); - - if (ret) - return ret; - - printf("Board type: %.*s\n", - sizeof(eeprom.board_name), eeprom.board_name); - printf("Board version: %.*s\n", - sizeof(eeprom.board_version), eeprom.board_version); - printf("Board serial: %.*s\n", - sizeof(eeprom.board_serial), eeprom.board_serial); - printf("Board interface version: %.*s\n", - sizeof(eeprom.interface_version), - eeprom.interface_version); - - return ret; -} - -int tricorder_eeprom_write(unsigned devaddr, const char *name, - const char *version, const char *serial, const char *interface) -{ - struct tricorder_eeprom eeprom, eeprom_verify; - size_t length; - uint32_t crc; - int ret; - unsigned char *p; - int i; - - memset(eeprom, 0, TRICORDER_EEPROM_SIZE); - memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); - - eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC); - eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE); - eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION); - - length = min(sizeof(eeprom.board_name), strlen(name)); - strncpy(eeprom.board_name, name, length); - - length = min(sizeof(eeprom.board_version), strlen(version)); - strncpy(eeprom.board_version, version, length); - - length = min(sizeof(eeprom.board_serial), strlen(serial)); - strncpy(eeprom.board_serial, serial, length); - - if (interface) { - length = min(sizeof(eeprom.interface_version), - strlen(interface)); - strncpy(eeprom.interface_version, interface, length); - } - - crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE); - eeprom.crc32 = cpu_to_be32(crc); - -#if defined(DEBUG) - puts("Tricorder EEPROM content:\n"); - print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); -#endif - - eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM); - - ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom, - TRICORDER_EEPROM_SIZE); - if (ret) - printf("Tricorder: Could not write EEPROM content!\n"); - - ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify, - TRICORDER_EEPROM_SIZE); - if (ret) - printf("Tricorder: Could not read EEPROM content!\n"); - - if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { - printf("Tricorder: Could not verify EEPROM content!\n"); - ret = 1; - } - - return ret; -} - -int do_tricorder_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *argv[]) -{ - if (argc == 3) { - ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - - if (strcmp(argv[1], "read") == 0) - return tricorder_eeprom_read(dev_addr); - } else if (argc == 6 || argc == 7) { - ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - char *name = argv[3]; - char *version = argv[4]; - char *serial = argv[5]; - char *interface = NULL; - - if (argc == 7) - interface = argv[6]; - - if (strcmp(argv[1], "write") == 0) - return tricorder_eeprom_write(dev_addr, name, version, - serial, interface); - } - - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - tricordereeprom, 7, 1, do_tricorder_eeprom, - "Tricorder EEPROM", - "read devaddr\n" - " - read Tricorder EEPROM at devaddr and print content\n" - "tricordereeprom write devaddr name version serial [interface]\n" - " - write Tricorder EEPROM at devaddr with 'name', 'version'" - "and 'serial'\n" - " optional add an HW interface parameter" -); -#endif /* CONFIG_SPL */ diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h deleted file mode 100644 index 7107b02a2c..0000000000 --- a/board/corscience/tricorder/tricorder-eeprom.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Andreas Bießmann <andreas.biessmann@corscience.de> - */ -#ifndef TRICORDER_EEPROM_H_ -#define TRICORDER_EEPROM_H_ - -#include <linux/compiler.h> - -#define TRICORDER_EEPROM_MAGIC 0xc2a94f52 -#define TRICORDER_EEPROM_VERSION 1 - -#define TRICORDER_BOARD_NAME_LENGTH 12 -#define TRICORDER_BOARD_VERSION_LENGTH 4 -#define TRICORDER_BOARD_SERIAL_LENGTH 12 -#define TRICORDER_INTERFACE_VERSION_LENGTH 4 - -struct tricorder_eeprom { - uint32_t magic; - uint16_t length; - uint16_t version; - char board_name[TRICORDER_BOARD_NAME_LENGTH]; - char board_version[TRICORDER_BOARD_VERSION_LENGTH]; - char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; - char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH]; - uint32_t crc32; -} __packed; - -#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom) -#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \ - sizeof(uint32_t)) - -/** - * @brief read eeprom information from a specific eeprom address - */ -int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom); - -#endif /* TRICORDER_EEPROM_H_ */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c deleted file mode 100644 index 3f4a40fd65..0000000000 --- a/board/corscience/tricorder/tricorder.c +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Thomas Weber <weber@corscience.de> - * Sunil Kumar <sunilsaini05@gmail.com> - * Shashi Ranjan <shashiranjanmca05@gmail.com> - * - * Derived from Devkit8000 code by - * Frederik Kriewitz <frederik@kriewitz.eu> - */ -#include <common.h> -#include <init.h> -#include <malloc.h> -#include <twl4030.h> -#include <status_led.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mem.h> -#include "tricorder.h" -#include "tricorder-eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/** - * get_eeprom - read the eeprom - * - * @eeprom - pointer to a eeprom struct to fill - * - * This function will panic() on wrong EEPROM content - */ -static void get_eeprom(struct tricorder_eeprom *eeprom) -{ - int ret; - - if (!eeprom) - panic("No eeprom given!\n"); - - ret = gpio_request(7, "BMS"); - if (ret) - panic("gpio: requesting BMS pin failed\n"); - - ret = gpio_direction_input(7); - if (ret) - panic("gpio: set BMS as input failed\n"); - - ret = gpio_get_value(7); - if (ret < 0) - panic("gpio: get BMS pin state failed\n"); - - gpio_free(7); - - if (ret == 0) { - /* BMS is _not_ set, do the EEPROM check */ - ret = tricorder_get_eeprom(0x51, eeprom); - if (!ret) { - if (strncmp(eeprom->board_name, "CS10411", 7) != 0) - panic("Wrong board name '%.*s'\n", - sizeof(eeprom->board_name), - eeprom->board_name); - if (eeprom->board_version[0] < 'D') - panic("Wrong board version '%.*s'\n", - sizeof(eeprom->board_version), - eeprom->board_version); - } else { - panic("Could not get board revision\n"); - } - } else { - memset(eeprom, 0, TRICORDER_EEPROM_SIZE); - } -} - -/** - * print_hwversion - print out a HW version string - * - * @eeprom - pointer to the eeprom - */ -static void print_hwversion(struct tricorder_eeprom *eeprom) -{ - size_t len; - if (!eeprom) - panic("No eeprom given!"); - - printf("Board %.*s:%.*s serial %.*s", - sizeof(eeprom->board_name), eeprom->board_name, - sizeof(eeprom->board_version), eeprom->board_version, - sizeof(eeprom->board_serial), eeprom->board_serial); - - len = strnlen(eeprom->interface_version, - sizeof(eeprom->interface_version)); - if (len > 0) - printf(" HW interface version %.*s", - sizeof(eeprom->interface_version), - eeprom->interface_version); - puts("\n"); -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - struct tricorder_eeprom eeprom; - get_eeprom(&eeprom); - print_hwversion(&eeprom); - - twl4030_power_init(); - status_led_set(0, CONFIG_LED_STATUS_ON); - status_led_set(1, CONFIG_LED_STATUS_ON); - status_led_set(2, CONFIG_LED_STATUS_ON); - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_TRICORDER(); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on the first bank. This - * provides the timing values back to the function that configures - * the memory. We have either one or two banks of 128MB DDR. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - struct tricorder_eeprom eeprom; - get_eeprom(&eeprom); - - /* General SDRC config */ - if (eeprom.board_version[0] > 'D') { - /* use optimized timings for our SDRAM device */ - timings->mcfg = MCFG((256 << 20), 14); -#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define MT46H64M32_TRRD 2 /* 12/6 = 2 */ -#define MT46H64M32_TRCD 3 /* 18/6 = 3 */ -#define MT46H64M32_TRP 3 /* 18/6 = 3 */ -#define MT46H64M32_TRAS 7 /* 42/6 = 7 */ -#define MT46H64M32_TRC 10 /* 60/6 = 10 */ -#define MT46H64M32_TRFC 12 /* 72/6 = 12 */ - timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, - MT46H64M32_TRAS, MT46H64M32_TRP, - MT46H64M32_TRCD, MT46H64M32_TRRD, - MT46H64M32_TDPL, - MT46H64M32_TDAL); - -#define MT46H64M32_TWTR 1 -#define MT46H64M32_TCKE 1 -#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */ -#define MT46H64M32_TXP 1 - timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, - MT46H64M32_TXP, MT46H64M32_XSR); - - timings->mr = MICRON_V_MR_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - /* use conservative beagleboard timings as default */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->mr = MICRON_V_MR_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } -} diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h deleted file mode 100644 index f083a5e9a2..0000000000 --- a/board/corscience/tricorder/tricorder.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Dirk Behme <dirk.behme@gmail.com> - * - * (C) Copyright 2012 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Thomas Weber <weber@corscience.de> - */ -#ifndef _TRICORDER_H_ -#define _TRICORDER_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Tricorder", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_TRICORDER() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ - /* Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - /* MMC Slot */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - /* Expansion Header */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\ - MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ - /* Serial Interface */\ - MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - /* Host USB0 */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\ - MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ - /* USB EHCI (port 2) */\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - BOOTMODE*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SIMO*/\ - MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SOMI*/\ - MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS0*/\ - MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CLK*/\ - MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M4)) /*GPIO_18*/\ - MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M4)) /*GPIO_19*/\ - MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M4)) /*GPIO_20*/\ - MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS1*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M4)) /*MSECURE*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ - /*HSUSB2 */\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\ - /* */\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ - -#endif diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig deleted file mode 100644 index 7b681cd81b..0000000000 --- a/board/creative/xfi3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_XFI3 - -config SYS_BOARD - default "xfi3" - -config SYS_VENDOR - default "creative" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "xfi3" - -endif diff --git a/board/creative/xfi3/MAINTAINERS b/board/creative/xfi3/MAINTAINERS deleted file mode 100644 index fb8235a329..0000000000 --- a/board/creative/xfi3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -XFI3 BOARD -M: Marek Vasut <marek.vasut@gmail.com> -S: Maintained -F: board/creative/xfi3/ -F: include/configs/xfi3.h -F: configs/xfi3_defconfig diff --git a/board/creative/xfi3/Makefile b/board/creative/xfi3/Makefile deleted file mode 100644 index 67d68dd621..0000000000 --- a/board/creative/xfi3/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := xfi3.o -else -obj-y := spl_boot.o -endif diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c deleted file mode 100644 index 67c1e9801b..0000000000 --- a/board/creative/xfi3/spl_boot.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Creative ZEN X-Fi3 setup - * - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP, - - MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, - MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP, - - /* PWM -- FIXME */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* mDDR configuration values */ - const uint32_t regs[] = { - 0x01010001, 0x00010000, 0x01000000, 0x00000001, - 0x00010101, 0x00000001, 0x00010000, 0x01000001, - 0x01010000, 0x00000001, 0x07000200, 0x04070203, - 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, - 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, - 0x03061323, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000000, 0x00000020, 0x00000000, - 0x001023cd, 0x20410010, 0x00006665, 0x00000000, - 0x00000101, 0x00000001, 0x00000000, 0x00000000, - }; - memcpy(dram_vals, regs, sizeof(regs)); -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c deleted file mode 100644 index 2aa2435e49..0000000000 --- a/board/creative/xfi3/xfi3.c +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Creative ZEN X-Fi3 board - * - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * Hardware investigation done by: - * - * Amaury Pouly <amaury.pouly@gmail.com> - */ - -#include <common.h> -#include <errno.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int xfi3_mmc_cd(int id) -{ - switch (id) { - case 0: - /* The SSP_DETECT is inverted on this board. */ - return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); - case 1: - /* Phison bridge always present */ - return 1; - default: - return 0; - } -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - /* MicroSD slot */ - gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); - gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0); - ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); - if (ret) - return ret; - - /* Phison SD-NAND bridge */ - ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); - - return ret; -} -#endif - -#ifdef CONFIG_VIDEO_MXS -static int mxsfb_write_byte(uint32_t payload, const unsigned int data) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - const unsigned int timeout = 0x10000; - - if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout)) - return -ETIMEDOUT; - - writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | - (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), - ®s->hw_lcdif_transfer_count); - - writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, - ®s->hw_lcdif_ctrl_clr); - - if (data) - writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); - - writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); - - if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, - timeout)) - return -ETIMEDOUT; - - writel(payload, ®s->hw_lcdif_data); - return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout); -} - -static void mxsfb_write_register(uint32_t reg, uint32_t data) -{ - mxsfb_write_byte(reg, 0); - mxsfb_write_byte(data, 1); -} - -static const struct { - uint8_t reg; - uint8_t delay; - uint16_t val; -} lcd_regs[] = { - { 0x01, 0, 0x001c }, - { 0x02, 0, 0x0100 }, - /* Writing 0x30 to reg. 0x03 flips the LCD */ - { 0x03, 0, 0x1038 }, - { 0x08, 0, 0x0808 }, - /* This can contain 0x111 to rotate the LCD. */ - { 0x0c, 0, 0x0000 }, - { 0x0f, 0, 0x0c01 }, - { 0x20, 0, 0x0000 }, - { 0x21, 30, 0x0000 }, - /* Wait 30 mS here */ - { 0x10, 0, 0x0a00 }, - { 0x11, 30, 0x1038 }, - /* Wait 30 mS here */ - { 0x12, 0, 0x1010 }, - { 0x13, 0, 0x0050 }, - { 0x14, 0, 0x4f58 }, - { 0x30, 0, 0x0000 }, - { 0x31, 0, 0x00db }, - { 0x32, 0, 0x0000 }, - { 0x33, 0, 0x0000 }, - { 0x34, 0, 0x00db }, - { 0x35, 0, 0x0000 }, - { 0x36, 0, 0x00af }, - { 0x37, 0, 0x0000 }, - { 0x38, 0, 0x00db }, - { 0x39, 0, 0x0000 }, - { 0x50, 0, 0x0000 }, - { 0x51, 0, 0x0705 }, - { 0x52, 0, 0x0e0a }, - { 0x53, 0, 0x0300 }, - { 0x54, 0, 0x0a0e }, - { 0x55, 0, 0x0507 }, - { 0x56, 0, 0x0000 }, - { 0x57, 0, 0x0003 }, - { 0x58, 0, 0x090a }, - { 0x59, 30, 0x0a09 }, - /* Wait 30 mS here */ - { 0x07, 30, 0x1017 }, - /* Wait 40 mS here */ - { 0x36, 0, 0x00af }, - { 0x37, 0, 0x0000 }, - { 0x38, 0, 0x00db }, - { 0x39, 0, 0x0000 }, - { 0x20, 0, 0x0000 }, - { 0x21, 0, 0x0000 }, -}; - -void mxsfb_system_setup(void) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - int i; - - /* Switch the LCDIF into System-Mode */ - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | - LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); - - /* Restart the SmartLCD controller */ - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_clr); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - - /* Program the SmartLCD controller */ - writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); - - writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) | - (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) | - (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) | - (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET), - ®s->hw_lcdif_timing); - - /* - * OTM2201A init and configuration sequence. - */ - for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { - mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); - if (lcd_regs[i].delay) - mdelay(lcd_regs[i].delay); - } - /* Turn on Framebuffer Upload Mode */ - mxsfb_write_byte(0x22, 0); - - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, - ®s->hw_lcdif_ctrl_set); -} -#endif - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Turn on PWM backlight */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - usb_eth_initialize(bis); - return 0; -} diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig deleted file mode 100644 index aa9bf25fb4..0000000000 --- a/board/el/el6x/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_ZC5202 - -config SYS_BOARD - default "el6x" - -config SYS_VENDOR - default "el" - -config SYS_CONFIG_NAME - default "zc5202" - -endif - -if TARGET_ZC5601 - -config SYS_BOARD - default "el6x" - -config SYS_VENDOR - default "el" - -config SYS_CONFIG_NAME - default "zc5601" - -endif diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS deleted file mode 100644 index 9a40010f50..0000000000 --- a/board/el/el6x/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -EL6X BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/el/el6x/ -F: include/configs/zc5202.h -F: include/configs/zc5601.h -F: configs/zc5202_defconfig -F: configs/zc5601_defconfig diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile deleted file mode 100644 index 065a867475..0000000000 --- a/board/el/el6x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) Stefano Babic <sbabic@denx.de> - -obj-y := el6x.o diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c deleted file mode 100644 index ddac58f73d..0000000000 --- a/board/el/el6x/el6x.c +++ /dev/null @@ -1,637 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - * - * Based on other i.MX6 boards - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <env.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <input.h> -#include <power/pmic.h> -#include <power/pfuze100_pmic.h> -#include <asm/arch/mx6-ddr.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12)) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PMIC 1 - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define ETH_PHY_RESET IMX_GPIO_NR(2, 4) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#ifdef CONFIG_TARGET_ZC5202 -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - /* Switch Reset */ - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - /* Switch Interrupt */ - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* use CRS and COL pads as GPIOs */ - MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL), - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL), - -}; - -#define BOARD_NAME "EL6x-ZC5202" -#else -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#define BOARD_NAME "EL6x-ZC5601" -#endif - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - -#ifdef CONFIG_TARGET_ZC5202 - /* set CRS and COL to input */ - gpio_direction_input(IMX_GPIO_NR(4, 9)); - gpio_direction_input(IMX_GPIO_NR(4, 12)); - - /* Reset Switch */ - gpio_direction_output(ETH_PHY_RESET , 0); - mdelay(2); - gpio_set_value(ETH_PHY_RESET, 1); -#endif -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#ifdef CONFIG_MXC_SPI -#ifdef CONFIG_TARGET_ZC5202 -iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const ecspi3_pads[] = { - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL), -}; -#endif - -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) - ? (IMX_GPIO_NR(3, 20)) : -1; -} - -static void setup_spi(void) -{ -#ifdef CONFIG_TARGET_ZC5202 - gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0"); - gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1"); - gpio_direction_output(IMX_GPIO_NR(5, 17), 1); - gpio_direction_output(IMX_GPIO_NR(5, 9), 1); - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -#endif - - gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0"); - gpio_direction_output(IMX_GPIO_NR(3, 20), 1); - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); - - enable_spi_clk(true, 3); -} -#endif - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC2_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ -#ifndef CONFIG_SPL_BUILD - int ret; - int i; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -#else - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - } - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif - -} -#endif - - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_eth_init(struct bd_info *bis) -{ - setup_iomux_enet(); - enable_enet_clk(1); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - - setup_iomux_uart(); - setup_spi(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); - - /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); - - /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - env_set("board_name", BOARD_NAME); - return 0; -} - -int checkboard(void) -{ - puts("Board: "); - puts(BOARD_NAME "\n"); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#include <spl.h> -#include <linux/libfdt.h> - -const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x001F001F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - .p0_mpdgctrl0 = 0x434B0350, - .p0_mpdgctrl1 = 0x034C0359, - .p1_mpdgctrl0 = 0x434B0350, - .p1_mpdgctrl1 = 0x03650348, - .p0_mprddlctl = 0x4436383B, - .p1_mprddlctl = 0x39393341, - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254A36, -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -/* - * This section requires the differentiation between iMX6 Sabre boards, but - * for now, it will configure only for the mx6q variant. - */ -static void spl_dram_init(void) -{ - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} - -#endif diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig deleted file mode 100644 index 48d25e5a26..0000000000 --- a/board/freescale/mpc8308rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8308RDB - -config SYS_BOARD - default "mpc8308rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8308RDB" - -endif diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS deleted file mode 100644 index 07ff2abd13..0000000000 --- a/board/freescale/mpc8308rdb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8308RDB BOARD -M: Ilya Yanok <yanok@emcraft.com> -S: Maintained -F: board/freescale/mpc8308rdb/ -F: include/configs/MPC8308RDB.h -F: configs/MPC8308RDB_defconfig diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile deleted file mode 100644 index d6eb4dcef2..0000000000 --- a/board/freescale/mpc8308rdb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010 -# Ilya Yanok, Emcraft Systems, yanok@emcraft.com - -obj-y := mpc8308rdb.o sdram.o diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c deleted file mode 100644 index db9c5ba193..0000000000 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <spi.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <pci.h> -#include <mpc83xx.h> -#include <vsc7385.h> -#include <netdev.h> -#include <fsl_esdhc.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_mpc83xx_serdes.h> - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#ifdef CONFIG_MPC8XXX_SPI - -#define SPI_CS_MASK 0x00400000 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* active low */ - clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* inactive high */ - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -} -#endif /* CONFIG_MPC8XXX_SPI */ - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - return fsl_esdhc_mmc_init(bd); -} -#endif - -static u8 read_board_info(void) -{ - u8 val8; - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) - return val8; - else - return 0; -} - -int checkboard(void) -{ - static const char * const rev_str[] = { - "1.0", - "<reserved>", - "<reserved>", - "<reserved>", - "<unknown>", - }; - u8 info; - int i; - - info = read_board_info(); - i = (!info) ? 4 : info & 0x03; - - printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); - - return 0; -} - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *pcie_reg[] = { pcie_regions_0 }; - - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(1, pcie_reg); -} -/* - * Miscellaneous late-boot configurations - * - * If a VSC7385 microcode image is present, then upload it. -*/ -int misc_init_r(void) -{ -#ifdef CONFIG_MPC8XXX_SPI - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - - /* - * Set proper bits in SICRH to allow SPI on header J8 - * - * NOTE: this breaks the TSEC2 interface, attached to the Vitesse - * switch. The pinmux configuration does not have a fine enough - * granularity to support both simultaneously. - */ - clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); - puts("WARNING: SPI enabled, TSEC2 support is broken\n"); - - /* Set header J8 SPI chip select output, disabled */ - setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -#endif - -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - return 1; - } -#endif - - return 0; -} -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - int rv, num_if = 0; - - /* Initialize TSECs first */ - rv = cpu_eth_init(bis); - if (rv >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize TSECs.\n"); - - rv = pci_eth_init(bis); - if (rv >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize PCI Ethernet.\n"); - - return num_if; -} diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c deleted file mode 100644 index 6340fd16ea..0000000000 --- a/board/freescale/mpc8308rdb/sdram.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - * - * This files is mostly identical to the original from - * board\freescale\mpc8315erdb\sdram.c - */ - -#include <common.h> -#include <init.h> -#include <mpc83xx.h> -#include <asm/global_data.h> - -#include <asm/bitops.h> -#include <asm/io.h> - -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -static long fixed_sdram(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & 0xfffff000); - out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - - /* Currently we use only one CS, so disable the other bank. */ - out_be32(&im->ddr.cs_config[1], 0); - - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - sync(); - - /* enable DDR controller */ - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - sync(); - - return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); -} - -int dram_init(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize; - - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM */ - msize = fixed_sdram(); - - /* return total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig deleted file mode 100644 index ce3fffda7d..0000000000 --- a/board/freescale/mpc8349itx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8349ITX - -config SYS_BOARD - default "mpc8349itx" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349ITX" - -endif diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS deleted file mode 100644 index d0388ad6e5..0000000000 --- a/board/freescale/mpc8349itx/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC8349ITX BOARD -#M: - -S: Maintained -F: board/freescale/mpc8349itx/ -F: include/configs/MPC8349ITX.h -F: configs/MPC8349ITX_defconfig -F: configs/MPC8349ITX_LOWBOOT_defconfig -F: configs/MPC8349ITXGP_defconfig diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile deleted file mode 100644 index 803cba09ff..0000000000 --- a/board/freescale/mpc8349itx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. - -obj-y += mpc8349itx.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README deleted file mode 100644 index 3012b83737..0000000000 --- a/board/freescale/mpc8349itx/README +++ /dev/null @@ -1,186 +0,0 @@ -Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards ---------------------------------------------------- - -1. Board Description - - The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring - the Freescale MPC8349E processor in a Mini-ITX form factor. - - The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: - - A) One 8MB on-board flash EEPROM chip, instead of two. - B) No SATA controller - C) No Compact Flash slot - D) No Mini-PCI slot - E) No Vitesse 7385 5-port Ethernet switch - F) No 4-port USB Type-A interface - -2. Board Switches and Jumpers - -2.0 Descriptions for all of the board jumpers can be found in the User - Guide. Of particular interest to U-Boot developers is jumper J22: - - Pos. Name Default Description - ----------------------------------------------------------------------- - A LGPL0 ON (0) HRCW source, bit 0 - B LGPL1 ON (0) HRCW source, bit 1 - C LGPL3 ON (0) HRCW source, bit 2 - D LGPL5 OFF (1) PCI_SYNC_OUT frequency - E BOOT1 ON (0) Flash EEPROM boot device - F PCI_M66EN ON (0) PCI 66MHz enable - G I2C-WP ON (0) I2C EEPROM write protection - H F_WP OFF (1) Flash EEPROM write protection - - Jumper J22.E is only for the ITX, and it decides the configuration - of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip - U4 is located at address FE000000 and flash chip U7 is at FE800000. - If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. - - For U-Boot development, J22.E can be used to switch back-and-forth - between two U-Boot images. - -3. Memory Map - -3.1. The memory map should look pretty much like this: - - 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) - 0xF001_0000 - 0xF001_FFFF Local bus expansion slot - 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) - 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory - 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) - -3.2 Flash EEPROM layout. - - On the ITX, jumper J22.E is used to determine which flash chips are - at which address. When J22.E is switched, addresses from FE000000 - to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. - - On the ITX, at the normal boot address (aka HIGHBOOT): - - FE00_0000 HRCW - FE70_0000 Alternative U-Boot image - FE80_0000 Alternative HRCW - FEF0_0000 U-Boot image - FEFF_FFFF End of flash - - On the ITX, at the low boot address (LOWBOOT) - - FE00_0000 HRCW and U-Boot image - FE04_0000 U-Boot environment variables - FE80_0000 Alternative HRCW and U-Boot image - FEFF_FFFF End of flash - - On the ITX-GP, the only option is LOWBOOT and there is only one chip - - FE00_0000 HRCW and U-Boot image - FE04_0000 U-Boot environment variables - F7FF_FFFF End of flash - -4. Definitions - -4.1 Explanation of NEW definitions in: - - include/configs/MPC8349ITX.h - - CONFIG_MPC83xx MPC83xx family - CONFIG_MPC8349 MPC8349 specific - CONFIG_MPC8349ITX MPC8349E-mITX - -5. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - - make MPC8349ITX_config - or: - make MPC8349ITXGP_config - or: - make MPC8349ITX_LOWBOOT_config - - make - -6. Downloading and Flashing Images - -6.1 Download via tftp: - - tftp $loadaddr <uboot> - - where "<uboot>" is the path and filename, on the TFTP server, of - the U-Boot image. - -6.1 Reflash U-Boot Image using U-Boot - - setenv uboot <uboot> - run tftpflash - - where "<uboot>" is the path and filename, on the TFTP server, of - the U-Boot image. - -6.2 Using the HRCW to switch between two different U-Boot images on the ITX - - Because the ITX has 16MB of flash, it is possible to keep two U-Boot - images in flash, and use the HRCW to specify which one is to be used - when the board boots. This trick is especially effective with a - hardware debugger that can override the HRCW, such as the BDI-2000. - - When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image - at address FE000000. When the BMS bit is 1, the ITX will boot the - image at address FEF00000. - - Therefore, just put a U-Boot image at both FE000000 and FEF00000 and - change the BMS bit whenever you want to boot the other image. - - Step-by-step instructions: - - 1) Build an ITX image to be loaded at FEF00000 - - make distclean - make MPC8349ITX_config - make - - 2) Take the u-boot.bin image and flash it at FEF00000. - - tftp $loadaddr u-boot.bin - protect off all - erase FEF00000 +$filesize - cp.b $loadaddr FEF00000 $filesize - - 3) Build an ITX image to be loaded at FE000000 - - make distclean - make MPC8349ITX_LOWBOOT_config - make - - 4) Take the u-boot.bin image and flash it at FE000000. - - tftp $loadaddr u-boot.bin - protect off FE000000 +$filesize - erase FE000000 +$filesize - cp.b $loadaddr FE000000 $filesize - - The HRCW in flash is currently set to boot the image at FE000000. - - If you have a hardware debugger, configure it to set the HRCW to - B460A000 04040000 if you want to boot the image at FEF00000, or set - it to B060A000 04040000 if you want to boot the image at FE000000. - - To change the HRCW in flash to boot the image at FEF00000, use these - U-Boot commands: - - cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 - mw.b 1020 b4 8 ; modify BMS bit - protect off FE000000 +10000 - erase FE000000 +10000 - cp.b 1000 FE000000 10000 - -7. Notes - 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c deleted file mode 100644 index 5b4c290df1..0000000000 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <log.h> -#include <mpc83xx.h> -#include <i2c.h> -#include <miiphy.h> -#include <vsc7385.h> -#ifdef CONFIG_PCI -#include <asm/mpc8349_pci.h> -#include <pci.h> -#endif -#include <spd_sdram.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif -#include <linux/delay.h> - -#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" -#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SPD_EEPROM -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - /* The size of RAM, in bytes */ - u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; - u32 ddr_size_log2 = __ilog2(ddr_size); - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - - /* Only one CS for DDR */ - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); - debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); - - debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); - debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; - im->ddr.sdram_mode = - (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); - im->ddr.sdram_interval = - (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << - SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); - debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); - debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); - debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); - debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); - - return CONFIG_SYS_DDR_SIZE; -} -#endif - -#ifdef CONFIG_PCI -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxmitx_config_table[] = { - { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - 0x0f, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; -#ifdef CONFIG_DDR_ECC - volatile ddr83xx_t *ddr = &im->ddr; -#endif - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; -#ifdef CONFIG_SPD_EEPROM - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#ifdef CONFIG_DDR_ECC - if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) - /* Unlike every other board, on the 83xx spd_sdram() returns - megabytes instead of just bytes. That's why we need to - multiple by 1MB when calling ddr_enable_ecc(). */ - ddr_enable_ecc(msize * 1048576); -#endif - - /* return total bus RAM size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_TARGET_MPC8349ITX - puts("Board: Freescale MPC8349E-mITX\n"); -#else - puts("Board: Freescale MPC8349E-mITX-GP\n"); -#endif - - return 0; -} - -/* - * Implement a work-around for a hardware problem with compact - * flash. - * - * Program the UPM if compact flash is enabled. - */ -int misc_init_f(void) -{ -#ifdef CONFIG_VSC7385_ENET - volatile u32 *vsc7385_cpuctrl; - - /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up - default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That - means it is 0 when the IRQ is not active. This makes the wire-AND - logic always assert IRQ7 to CPU even if there is no request from the - switch. Since the compact flash and the switch share the same IRQ, - the Linux kernel will think that the compact flash is requesting irq - and get stuck when it tries to clear the IRQ. Thus we need to set - the L2_IRQ0 and L2_IRQ1 to active low. - - The following code sets the L1_IRQ and L2_IRQ polarity to active low. - Without this code, compact flash will not work in Linux because - unlike U-Boot, Linux uses the IRQ, so this code is necessary if we - don't enable compact flash for U-Boot. - */ - - vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); - *vsc7385_cpuctrl |= 0x0c; -#endif - -#ifdef CONFIG_COMPACT_FLASH - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, - 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, - 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); - - /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, - GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 - */ - immap->im_lbc.mamr = 0x08404440; - - upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - puts("UPMA: Configured for compact flash\n"); -#endif - - return 0; -} - -/* - * Miscellaneous late-boot configurations - * - * Make sure the EEPROM has the HRCW correctly programmed. - * Make sure the RTC is correctly programmed. - * - * The MPC8349E-mITX can be configured to load the HRCW from - * EEPROM instead of flash. This is controlled via jumpers - * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all - * jumpered), but if they're set to 001 or 010, then the HRCW is - * read from the "I2C EEPROM". - * - * This function makes sure that the I2C EEPROM is programmed - * correctly. - * - * If a VSC7385 microcode image is present, then upload it. - */ -int misc_init_r(void) -{ - int rc = 0; - -#if defined(CONFIG_SYS_I2C) - unsigned int orig_bus = i2c_get_bus_num(); - u8 i2c_data; - -#ifdef CONFIG_SYS_I2C_RTC_ADDR - u8 ds1339_data[17]; -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - static u8 eeprom_data[] = /* HRCW data */ - { - 0xAA, 0x55, 0xAA, /* Preamble */ - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ - (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, - (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, - (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, - CONFIG_SYS_HRCW_LOW & 0xFF, - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ - (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, - (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, - (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, - CONFIG_SYS_HRCW_HIGH & 0xFF - }; - - u8 data[sizeof(eeprom_data)]; -#endif - - printf("Board revision: "); - i2c_set_bus_num(1); - if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else { - printf("Unknown\n"); - rc = 1; - } - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { - if (memcmp(data, eeprom_data, sizeof(data)) != 0) { - if (i2c_write - (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, - sizeof(eeprom_data)) != 0) { - puts("Failure writing the HRCW to EEPROM via I2C.\n"); - rc = 1; - } - } - } else { - puts("Failure reading the HRCW from EEPROM via I2C.\n"); - rc = 1; - } -#endif - -#ifdef CONFIG_SYS_I2C_RTC_ADDR - i2c_set_bus_num(1); - - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) - == 0) { - - /* Work-around for MPC8349E-mITX bug #13601. - If the RTC does not contain valid register values, the DS1339 - Linux driver will not work. - */ - - /* Make sure status register bits 6-2 are zero */ - ds1339_data[0x0f] &= ~0x7c; - - /* Check for a valid day register value */ - ds1339_data[0x03] &= ~0xf8; - if (ds1339_data[0x03] == 0) { - ds1339_data[0x03] = 1; - } - - /* Check for a valid date register value */ - ds1339_data[0x04] &= ~0xc0; - if ((ds1339_data[0x04] == 0) || - ((ds1339_data[0x04] & 0x0f) > 9) || - (ds1339_data[0x04] >= 0x32)) { - ds1339_data[0x04] = 1; - } - - /* Check for a valid month register value */ - ds1339_data[0x05] &= ~0x60; - - if ((ds1339_data[0x05] == 0) || - ((ds1339_data[0x05] & 0x0f) > 9) || - ((ds1339_data[0x05] >= 0x13) - && (ds1339_data[0x05] <= 0x19))) { - ds1339_data[0x05] = 1; - } - - /* Enable Oscillator and rate select */ - ds1339_data[0x0e] = 0x1c; - - /* Work-around for MPC8349E-mITX bug #13330. - Ensure that the RTC control register contains the value 0x1c. - This affects SATA performance. - */ - - if (i2c_write - (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, - sizeof(ds1339_data))) { - puts("Failure writing to the RTC via I2C.\n"); - rc = 1; - } - } else { - puts("Failure reading from the RTC via I2C.\n"); - rc = 1; - } -#endif - - i2c_set_bus_num(orig_bus); -#endif - -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - rc = 1; - } -#endif - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c deleted file mode 100644 index a09b658688..0000000000 --- a/board/freescale/mpc8349itx/pci.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <linux/delay.h> - -#include <asm/mmu.h> -#include <asm/io.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <asm/fsl_i2c.h> - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - u8 reg8; - -#if defined(CONFIG_SYS_I2C) - i2c_set_bus_num(1); - /* Read the PCI_M66EN jumper setting */ - if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || - (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { - if (reg8 & I2C_8574_PCI66) - clk->occr = 0xff000000; /* 66 MHz PCI */ - else - clk->occr = 0xff600001; /* 33 MHz PCI */ - } else { - clk->occr = 0xff600001; /* 33 MHz PCI */ - } -#else - clk->occr = 0xff000000; /* 66 MHz PCI */ -#endif - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig deleted file mode 100644 index 20d29db099..0000000000 --- a/board/freescale/mpc837xemds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC837XEMDS - -config SYS_BOARD - default "mpc837xemds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC837XEMDS" - -endif diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS deleted file mode 100644 index ce9c446f2d..0000000000 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC837XEMDS BOARD -#M: Dave Liu <daveliu@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc837xemds/ -F: include/configs/MPC837XEMDS.h -F: configs/MPC837XEMDS_defconfig -F: configs/MPC837XEMDS_SLAVE_defconfig -F: configs/MPC837XEMDS_HOST_defconfig diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile deleted file mode 100644 index 5348cdf00c..0000000000 --- a/board/freescale/mpc837xemds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc837xemds.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README deleted file mode 100644 index dbb15171e6..0000000000 --- a/board/freescale/mpc837xemds/README +++ /dev/null @@ -1,104 +0,0 @@ -Freescale MPC837xEMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. - SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 For the MPC837xEMDS Processor Board - - First, make sure the board default setting is consistent with the - document shipped with your board. Then apply the following setting: - SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) - SW4[1-8]= 0000_0110 (core PLL setting) - SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) - SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) - SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) - J3 2-3, TSEC1 LVDD1 with 2.5V - J6 2-3, TSEC2 LVDD2 with 2.5V - J9 2-3, CLKIN from osc on board - J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND - J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) - mounted, HRCW load from BCSR. - - on board Oscillator: 66M - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - 0xe010_0000 0xe02f_ffff Empty 2M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xe05f_ffff Empty 2M - 0xe060_0000 0xe060_7fff NAND Flash 32K - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC837XEMDS.h - - CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360 - CONFIG_MPC837x MPC837x specific - CONFIG_MPC837XEMDS MPC837XEMDS board specific - -4. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC837XEMDS_config - make - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send <u-boot-bin-image> - c - ] - - - Or via tftp: - - tftp 40000 u-boot.bin - -5.1 Reflash U-Boot Image using U-Boot - - tftp 40000 u-boot.bin - protect off fe000000 fe1fffff - erase fe000000 fe1fffff - - cp.b 40000 fe000000 xxxx - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. - -6. Notes - 1) The console baudrate for MPC837XEMDS is 115200bps. diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c deleted file mode 100644 index 71875cf8f8..0000000000 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007,2010 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <spd_sdram.h> -#include <tsec.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_esdhc.h> -#include <fsl_mdio.h> -#include <phy.h> -#include "pci.h" -#include "../common/pq-mds-pib.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[0x9] &= ~0x04; - /* Clear all of the interrupt of BCSR */ - bcsr[0xe] = 0xff; - -#ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr = in_be32(&immr->sysconf.spridr); - - /* we check only part num, and don't look for CPU revisions */ - switch (PARTID_NO_E(spridr)) { - case SPR_8377: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); - break; - case SPR_8379: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - default: - printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); - break; - } -#endif /* CONFIG_FSL_SERDES */ - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - if (!hwconfig("esdhc")) - return 0; - - /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ - bcsr[0xc] |= 0x4c; - - /* Set proper bits in SICR to allow SD signals through */ - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, - SICRH_GPIO2_E_SD | SICRH_SPI_SD); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) -int board_eth_init(struct bd_info *bd) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - int num = 0; - - /* New line after Net: */ - printf("\n"); - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - - printf(CONFIG_TSEC1_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - - printf(CONFIG_TSEC2_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bd, &mdio_info); - - return tsec_eth_init(bd, tsec_info, num); -} - -static void __ft_tsec_fixup(void *blob, struct bd_info *bd, const char *alias, - int phy_addr) -{ - const u32 *ph; - int off; - int err; - - off = fdt_path_offset(blob, alias); - if (off < 0) { - printf("WARNING: could not find %s alias: %s.\n", alias, - fdt_strerror(off)); - return; - } - - err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII); - - if (err) { - printf("WARNING: could not set phy-connection-type for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } - - ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0); - if (!ph) { - printf("WARNING: could not get phy-handle for %s.\n", - alias); - return; - } - - off = fdt_node_offset_by_phandle(blob, *ph); - if (off < 0) { - printf("WARNING: could not get phy node for %s: %s\n", alias, - fdt_strerror(off)); - return; - } - - phy_addr = cpu_to_fdt32(phy_addr); - err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr)); - if (err < 0) { - printf("WARNING: could not set phy node's reg for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } -} - -static void ft_tsec_fixup(void *blob, struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - -#ifdef CONFIG_TSEC1 - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII); -#endif - -#ifdef CONFIG_TSEC2 - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII); -#endif -} -#else -static inline void ft_tsec_fixup(void *blob, struct bd_info *bd) {} -#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */ - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize DDR ECC byte */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus DDR size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - -#if (CONFIG_SYS_DDR_SIZE != 512) -#warning Currenly any ddr size other than 512 is not supported -#endif - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); - return CONFIG_SYS_DDR_SIZE; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC837xEMDS\n"); - return 0; -} - -#ifdef CONFIG_PCI -int board_pci_host_broken(void) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST; - - /* It's always OK in case of external arbiter. */ - if (hwconfig_subarg_cmp("pci", "arbiter", "external")) - return 0; - - if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask) - return 1; - - return 0; -} - -static void ft_pci_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "broken (no arbiter)"; - int off; - int err; - - off = fdt_path_offset(blob, "pci0"); - if (off < 0) { - printf("WARNING: could not find pci0 alias: %s.\n", - fdt_strerror(off)); - return; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for pci0: %s.\n", - fdt_strerror(err)); - return; - } -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - ft_tsec_fixup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); - if (board_pci_host_broken()) - ft_pci_fixup(blob, bd); - ft_pcie_fixup(blob, bd); -#endif - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c deleted file mode 100644 index 188e60ac08..0000000000 --- a/board/freescale/mpc837xemds/pci.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <env.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <fdt_support.h> -#include <asm/fsl_i2c.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <linux/delay.h> - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static int is_pex_x2(void) -{ - const char *pex_x2 = env_get("pex_x2"); - - if (pex_x2 && !strcmp(pex_x2, "yes")) - return 1; - return 0; -} - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - u32 spridr = in_be32(&immr->sysconf.spridr); - int pex2 = is_pex_x2(); - - if (board_pci_host_broken()) - goto skip_pci; - - /* Enable all 5 PCI_CLK_OUTPUTS */ - clk->occr |= 0xf8000000; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); -skip_pci: - /* There is no PEX in MPC8379 parts. */ - if (PARTID_NO_E(spridr) == SPR_8379) - return; - - if (pex2) - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - else - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - if (!pex2) - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg); -} - -void ft_pcie_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "disabled (PCIE1 is x2)"; - - if (!is_pex_x2()) - return; - - do_fixup_by_path(blob, "pci2", "status", status, - strlen(status) + 1, 1); -} diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h deleted file mode 100644 index a568031988..0000000000 --- a/board/freescale/mpc837xemds/pci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __BOARD_MPC837XEMDS_PCI_H -#define __BOARD_MPC837XEMDS_PCI_H - -extern void ft_pcie_fixup(void *blob, struct bd_info *bd); - -#endif /* __BOARD_MPC837XEMDS_PCI_H */ diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig deleted file mode 100644 index c226c1ca06..0000000000 --- a/board/freescale/mx53evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX53EVK - -config SYS_BOARD - default "mx53evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx53evk" - -endif diff --git a/board/freescale/mx53evk/MAINTAINERS b/board/freescale/mx53evk/MAINTAINERS deleted file mode 100644 index d511046cb0..0000000000 --- a/board/freescale/mx53evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX53EVK BOARD -M: Jason Liu <jason.hui.liu@nxp.com> -S: Maintained -F: board/freescale/mx53evk/ -F: include/configs/mx53evk.h -F: configs/mx53evk_defconfig diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile deleted file mode 100644 index cfe4be321e..0000000000 --- a/board/freescale/mx53evk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2010 Freescale Semiconductor, Inc. - -obj-y := mx53evk.o diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg deleted file mode 100644 index ef103d6da7..0000000000 --- a/board/freescale/mx53evk/imximage.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* Setting IOMUXC */ -DATA 4 0x53fa8554 0x00200000 -DATA 4 0x53fa8560 0x00200000 -DATA 4 0x53fa8594 0x00200000 -DATA 4 0x53fa8584 0x00200000 -DATA 4 0x53fa8558 0x00200040 -DATA 4 0x53fa8568 0x00200040 -DATA 4 0x53fa8590 0x00200040 -DATA 4 0x53fa857c 0x00200040 -DATA 4 0x53fa8564 0x00200040 -DATA 4 0x53fa8580 0x00200040 -DATA 4 0x53fa8570 0x00200000 -DATA 4 0x53fa8578 0x00200000 -DATA 4 0x53fa872c 0x00200000 -DATA 4 0x53fa8728 0x00200000 -DATA 4 0x53fa871c 0x00200000 -DATA 4 0x53fa8718 0x00200000 -DATA 4 0x53fa8574 0x00280000 -DATA 4 0x53fa8588 0x00280000 -DATA 4 0x53fa86f0 0x00280000 -DATA 4 0x53fa8720 0x00280000 -DATA 4 0x53fa86fc 0x00000000 -DATA 4 0x53fa86f4 0x00000200 -DATA 4 0x53fa8714 0x00000000 -DATA 4 0x53fa8724 0x06000000 -DATA 4 0x63fd9088 0x34333936 -DATA 4 0x63fd9090 0x49434942 -DATA 4 0x63fd90F8 0x00000800 -DATA 4 0x63fd907c 0x01350138 -DATA 4 0x63fd9080 0x01380139 -DATA 4 0x63fd9018 0x00001710 -DATA 4 0x63fd9000 0xc4110000 -DATA 4 0x63fd900C 0x4d5122d2 -DATA 4 0x63fd9010 0x92d18a22 -DATA 4 0x63fd9014 0x00c70092 -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f000e -DATA 4 0x63fd9008 0x12272000 -DATA 4 0x63fd9004 0x00030012 -DATA 4 0x63fd901c 0x04008010 -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00008031 -DATA 4 0x63fd901c 0x0b5280b0 -DATA 4 0x63fd901c 0x04008010 -DATA 4 0x63fd901c 0x00008020 -DATA 4 0x63fd901c 0x00008020 -DATA 4 0x63fd901c 0x0a528030 -DATA 4 0x63fd901c 0x03c68031 -DATA 4 0x63fd901c 0x00448031 -DATA 4 0x63fd901c 0x04008018 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00008039 -DATA 4 0x63fd901c 0x0b528138 -DATA 4 0x63fd901c 0x04008018 -DATA 4 0x63fd901c 0x00008028 -DATA 4 0x63fd901c 0x00008028 -DATA 4 0x63fd901c 0x0a528038 -DATA 4 0x63fd901c 0x03c68039 -DATA 4 0x63fd901c 0x00448039 -DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9058 0x00033335 -DATA 4 0x63fd901c 0x00000000 -DATA 4 0x63fd9040 0x05380003 -DATA 4 0x53fa8004 0x00194005 diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c deleted file mode 100644 index b006638e2c..0000000000 --- a/board/freescale/mx53evk/mx53evk.c +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <linux/errno.h> -#include <asm/mach-imx/boot_mode.h> -#include <netdev.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <asm/gpio.h> -#include <mc13892.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_ODE) - -static void setup_i2c(unsigned int port_number) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), - }; - - static const iomux_v3_cfg_t i2c2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL), - }; - - switch (port_number) { - case 0: - imx_iomux_v3_setup_multiple_pads(i2c1_pads, - ARRAY_SIZE(i2c1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(i2c2_pads, - ARRAY_SIZE(i2c2_pads)); - break; - default: - printf("Warning: Wrong I2C port number\n"); - break; - } -} - -void power_init(void) -{ - unsigned int val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_0); - if (ret) - return; - - p = pmic_get("FSL_PMIC"); - if (!p) - return; - - /* Set VDDA to 1.25V */ - pmic_reg_read(p, REG_SW_2, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_25; - pmic_reg_write(p, REG_SW_2, val); - - /* - * Need increase VCC and VDDA to 1.3V - * according to MX53 IC TO2 datasheet. - */ - if (is_soc_rev(CHIP_REV_2_0) == 0) { - /* Set VCC to 1.3V for TO2 */ - pmic_reg_read(p, REG_SW_1, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_30; - pmic_reg_write(p, REG_SW_1, val); - - /* Set VDDA to 1.3V for TO2 */ - pmic_reg_read(p, REG_SW_2, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_30; - pmic_reg_write(p, REG_SW_2, val); - } -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); - gpio_direction_input(IMX_GPIO_NR(3, 11)); - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); - gpio_direction_input(IMX_GPIO_NR(3, 13)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); - else - ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); - - return ret; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, - {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ - setup_i2c(1); - power_init(); - -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: MX53EVK\n"); - - return 0; -} diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig deleted file mode 100644 index 8ab8b460f9..0000000000 --- a/board/freescale/mx6qarm2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6QARM2 - -config SYS_BOARD - default "mx6qarm2" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6qarm2" - -endif diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS deleted file mode 100644 index fdbc7fa725..0000000000 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -MX6QARM2 BOARD -M: Jason Liu <jason.hui.liu@nxp.com> -M: Ye Li <ye.li@nxp.com> -S: Maintained -F: board/freescale/mx6qarm2/ -F: include/configs/mx6qarm2.h -F: configs/mx6qarm2_defconfig -F: configs/mx6dlarm2_defconfig -F: configs/mx6qarm2_lpddr2_defconfig -F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile deleted file mode 100644 index ef80a89672..0000000000 --- a/board/freescale/mx6qarm2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6qarm2.o diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg deleted file mode 100644 index 74a33c2503..0000000000 --- a/board/freescale/mx6qarm2/imximage.cfg +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -#ifdef CONFIG_MX6DQ_LPDDR2 -/* DCD */ -DATA 4 0x020C4018 0x60324 - -DATA 4 0x020E05a8 0x00003038 -DATA 4 0x020E05b0 0x00003038 -DATA 4 0x020E0524 0x00003038 -DATA 4 0x020E051c 0x00003038 - -DATA 4 0x020E0518 0x00003038 -DATA 4 0x020E050c 0x00003038 -DATA 4 0x020E05b8 0x00003038 -DATA 4 0x020E05c0 0x00003038 - -DATA 4 0x020E05ac 0x00000038 -DATA 4 0x020E05b4 0x00000038 -DATA 4 0x020E0528 0x00000038 -DATA 4 0x020E0520 0x00000038 - -DATA 4 0x020E0514 0x00000038 -DATA 4 0x020E0510 0x00000038 -DATA 4 0x020E05bc 0x00000038 -DATA 4 0x020E05c4 0x00000038 - -DATA 4 0x020E056c 0x00000038 -DATA 4 0x020E0578 0x00000038 -DATA 4 0x020E0588 0x00000038 -DATA 4 0x020E0594 0x00000038 - -DATA 4 0x020E057c 0x00000038 -DATA 4 0x020E0590 0x00000038 -DATA 4 0x020E0598 0x00000038 -DATA 4 0x020E058c 0x00000000 - -DATA 4 0x020E059c 0x00000038 -DATA 4 0x020E05a0 0x00000038 -DATA 4 0x020E0784 0x00000038 -DATA 4 0x020E0788 0x00000038 - -DATA 4 0x020E0794 0x00000038 -DATA 4 0x020E079c 0x00000038 -DATA 4 0x020E07a0 0x00000038 -DATA 4 0x020E07a4 0x00000038 - -DATA 4 0x020E07a8 0x00000038 -DATA 4 0x020E0748 0x00000038 -DATA 4 0x020E074c 0x00000038 -DATA 4 0x020E0750 0x00020000 - -DATA 4 0x020E0758 0x00000000 -DATA 4 0x020E0774 0x00020000 -DATA 4 0x020E078c 0x00000038 -DATA 4 0x020E0798 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b401c 0x00008000 - -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -DATA 4 0x021b0800 0xa1390000 -DATA 4 0x021b4800 0xa1390000 - -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b4890 0x00400000 - -DATA 4 0x021b48bc 0x00055555 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b482c 0xf3333333 -DATA 4 0x021b4830 0xf3333333 -DATA 4 0x021b4834 0xf3333333 -DATA 4 0x021b4838 0xf3333333 - -DATA 4 0x021b0848 0x49383b39 -DATA 4 0x021b0850 0x30364738 -DATA 4 0x021b4848 0x3e3c3846 -DATA 4 0x021b4850 0x4c294b35 - -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -DATA 4 0x021b0858 0xf00 -DATA 4 0x021b4858 0xf00 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b000c 0x555a61a5 -DATA 4 0x021b0004 0x20036 -DATA 4 0x021b0010 0x160e83 -DATA 4 0x021b0014 0xdd -DATA 4 0x021b0018 0x8174c -DATA 4 0x021b002c 0xf9f26d2 -DATA 4 0x021b0030 0x20e -DATA 4 0x021b0038 0x200aac -DATA 4 0x021b0008 0x0 - -DATA 4 0x021b0040 0x5f - -DATA 4 0x021b0000 0xc3010000 - -DATA 4 0x021b400c 0x555a61a5 -DATA 4 0x021b4004 0x20036 -DATA 4 0x021b4010 0x160e83 -DATA 4 0x021b4014 0xdd -DATA 4 0x021b4018 0x8174c -DATA 4 0x021b402c 0xf9f26d2 -DATA 4 0x021b4030 0x20e -DATA 4 0x021b4038 0x200aac -DATA 4 0x021b4008 0x0 - -DATA 4 0x021b4040 0x3f -DATA 4 0x021b4000 0xc3010000 - -DATA 4 0x021b001c 0x3f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0xc2018030 -DATA 4 0x021b001c 0x6028030 -DATA 4 0x021b001c 0x2038030 - -DATA 4 0x021b401c 0x3f8030 -DATA 4 0x021b401c 0xff0a8030 -DATA 4 0x021b401c 0xc2018030 -DATA 4 0x021b401c 0x6028030 -DATA 4 0x021b401c 0x2038030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b0020 0x7800 -DATA 4 0x021b4020 0x7800 - -DATA 4 0x021b0818 0x0 -DATA 4 0x021b4818 0x0 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b001c 0x0 -DATA 4 0x021b401c 0x0 - -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005B0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xC31A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg deleted file mode 100644 index 0d1353119b..0000000000 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ /dev/null @@ -1,461 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - - - -#ifdef CONFIG_MX6DL_LPDDR2 - -/* IOMUX SETTINGS */ -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ -DATA 4 0x020E04bc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ -DATA 4 0x020E04c0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ -DATA 4 0x020E04c4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ -DATA 4 0x020E04c8 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ -DATA 4 0x020E04cc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ -DATA 4 0x020E04d0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ -DATA 4 0x020E04d4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ -DATA 4 0x020E04d8 0x00003028 - -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ -DATA 4 0x020E0470 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ -DATA 4 0x020E0474 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ -DATA 4 0x020E0478 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ -DATA 4 0x020E047c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ -DATA 4 0x020E0480 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ -DATA 4 0x020E0484 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ -DATA 4 0x020E0488 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ -DATA 4 0x020E048c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ -DATA 4 0x020E0464 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ -DATA 4 0x020E0490 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ -DATA 4 0x020E04ac 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ -DATA 4 0x020E04b0 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ -DATA 4 0x020E0494 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ -DATA 4 0x020E04a4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ -DATA 4 0x020E04a8 0x00000038 -/* - * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - * DSE can be configured using Group Control Register: - * IOMUXC_SW_PAD_CTL_GRP_CTLDS - */ -DATA 4 0x020E04a0 0x00000000 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ -DATA 4 0x020E04b4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ -DATA 4 0x020E04b8 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ -DATA 4 0x020E0764 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ -DATA 4 0x020E0770 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ -DATA 4 0x020E0778 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ -DATA 4 0x020E077c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ -DATA 4 0x020E0780 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ -DATA 4 0x020E0784 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ -DATA 4 0x020E078c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ -DATA 4 0x020E0748 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ -DATA 4 0x020E074c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ -DATA 4 0x020E076c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ -DATA 4 0x020E0750 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ -DATA 4 0x020E0754 0x00000000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ -DATA 4 0x020E0760 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ -DATA 4 0x020E0774 0x00080000 - -/* - * DDR Controller Registers - * - * Manufacturer: Mocron - * Device Part Number: MT42L64M64D2KH-18 - * Clock Freq.: 528MHz - * MMDC channels: Both MMDC0, MMDC1 - *Density per CS in Gb: 256M - * Chip Selects used: 2 - * Number of Banks: 8 - * Row address: 14 - * Column address: 9 - * Data bus width 32 - */ - -/* MMDC_P0_BASE_ADDR = 0x021b0000 */ -/* MMDC_P1_BASE_ADDR = 0x021b4000 */ - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b001c 0x00008000 - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b401c 0x00008000 - -/*LPDDR2 ZQ params */ -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -/* Calibration setup. */ -/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ -DATA 4 0x021b0800 0xa1390003 - -/*ca bus abs delay */ -DATA 4 0x021b0890 0x00400000 -/*ca bus abs delay */ -DATA 4 0x021b4890 0x00400000 -/* values of 20,40,50,60,7f tried. no difference seen */ - -/* DDR_PHY_P1_MPWRCADL */ -DATA 4 0x021b48bc 0x00055555 - -/*frc_msr.*/ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr.*/ -DATA 4 0x021b48b8 0x00000800 - -/* DDR_PHY_P0_MPREDQBY0DL3 */ -DATA 4 0x021b081c 0x33333333 -/* DDR_PHY_P0_MPREDQBY1DL3 */ -DATA 4 0x021b0820 0x33333333 -/* DDR_PHY_P0_MPREDQBY2DL3 */ -DATA 4 0x021b0824 0x33333333 -/* DDR_PHY_P0_MPREDQBY3DL3 */ -DATA 4 0x021b0828 0x33333333 -/* DDR_PHY_P1_MPREDQBY0DL3 */ -DATA 4 0x021b481c 0x33333333 -/* DDR_PHY_P1_MPREDQBY1DL3 */ -DATA 4 0x021b4820 0x33333333 -/* DDR_PHY_P1_MPREDQBY2DL3 */ -DATA 4 0x021b4824 0x33333333 -/* DDR_PHY_P1_MPREDQBY3DL3 */ -DATA 4 0x021b4828 0x33333333 - -/* - * Read and write data delay, per byte. - * For optimized DDR operation it is recommended to run mmdc_calibration - * on your board, and replace 4 delay register assigns with resulted values - * Note: - * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section - * should be skipped, or the write/read calibration comming after that - * will stall - * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. - */ - -DATA 4 0x021b0848 0x4b4b524f -DATA 4 0x021b4848 0x494f4c44 - -DATA 4 0x021b0850 0x3c3d303c -DATA 4 0x021b4850 0x3c343d38 - -/*dqs gating dis */ -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -/*clk delay */ -DATA 4 0x021b0858 0xa00 -/*clk delay */ -DATA 4 0x021b4858 0xa00 - -/*frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr */ -DATA 4 0x021b48b8 0x00000800 -/* Calibration setup end */ - -/* Channel0 - startng address 0x80000000 */ -/* MMDC0_MDCFG0 */ -DATA 4 0x021b000c 0x34386145 - -/* MMDC0_MDPDC */ -DATA 4 0x021b0004 0x00020036 -/* MMDC0_MDCFG1 */ -DATA 4 0x021b0010 0x00100c83 -/* MMDC0_MDCFG2 */ -DATA 4 0x021b0014 0x000000Dc -/* MMDC0_MDMISC */ -DATA 4 0x021b0018 0x0000174C -/* MMDC0_MDRWD;*/ -DATA 4 0x021b002c 0x0f9f26d2 -/* MMDC0_MDOR */ -DATA 4 0x021b0030 0x009f0e10 -/* MMDC0_MDCFG3LP */ -DATA 4 0x021b0038 0x00190778 -/* MMDC0_MDOTC */ -DATA 4 0x021b0008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b0040 0x0000005f -/* ROC */ -DATA 4 0x021b0404 0x0000000f - -/* MMDC0_MDCTL */ -DATA 4 0x021b0000 0xc3010000 - -/* Channel1 - starting address 0x10000000 */ -/* MMDC1_MDCFG0 */ -DATA 4 0x021b400c 0x34386145 - -/* MMDC1_MDPDC */ -DATA 4 0x021b4004 0x00020036 -/* MMDC1_MDCFG1 */ -DATA 4 0x021b4010 0x00100c83 -/* MMDC1_MDCFG2 */ -DATA 4 0x021b4014 0x000000Dc -/* MMDC1_MDMISC */ -DATA 4 0x021b4018 0x0000174C -/* MMDC1_MDRWD;*/ -DATA 4 0x021b402c 0x0f9f26d2 -/* MMDC1_MDOR */ -DATA 4 0x021b4030 0x009f0e10 -/* MMDC1_MDCFG3LP */ -DATA 4 0x021b4038 0x00190778 -/* MMDC1_MDOTC */ -DATA 4 0x021b4008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b4040 0x0000003f - -/* MMDC1_MDCTL */ -DATA 4 0x021b4000 0xc3010000 - -/* Channel0 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b001c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b001c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b001c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b001c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b001c 0x01038030 - -/* Channel1 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b401c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b401c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b401c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b401c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b401c 0x01038030 - -/* MMDC0_MDREF */ -DATA 4 0x021b0020 0x00005800 -/* MMDC1_MDREF */ -DATA 4 0x021b4020 0x00005800 - -/* DDR_PHY_P0_MPODTCTRL */ -DATA 4 0x021b0818 0x0 -/* DDR_PHY_P1_MPODTCTRL */ -DATA 4 0x021b4818 0x0 - -/* - * calibration values based on calibration compare of 0x00ffff00: - * Note, these calibration values are based on Freescale's board - * May need to run calibration on target board to fine tune these - */ - -/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ -DATA 4 0x021b0800 0xa1310003 - -/* DDR_PHY_P0_MPMUR0, frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/* DDR_PHY_P1_MPMUR0, frc_msr */ -DATA 4 0x021b48b8 0x00000800 - -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b001c 0x00000000 -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b401c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else /* CONFIG_MX6DL_LPDDR2 */ - -DATA 4 0x020e0798 0x000c0000 -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0750 0x00020000 -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05b4 0x00000030 -DATA 4 0x020e0528 0x00000030 -DATA 4 0x020e0520 0x00000030 -DATA 4 0x020e0514 0x00000030 -DATA 4 0x020e0510 0x00000030 -DATA 4 0x020e05bc 0x00000030 -DATA 4 0x020e05c4 0x00000030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F -DATA 4 0x021b480c 0x00370037 -DATA 4 0x021b4810 0x00370037 -DATA 4 0x021b083c 0x422f0220 -DATA 4 0x021b0840 0x021f0219 -DATA 4 0x021b483C 0x422f0220 -DATA 4 0x021b4840 0x022d022f -DATA 4 0x021b0848 0x47494b49 -DATA 4 0x021b4848 0x48484c47 -DATA 4 0x021b0850 0x39382b2f -DATA 4 0x021b4850 0x2f35312c -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 - -DATA 4 0x021b000c 0x40445323 -DATA 4 0x021b0010 0xb66e8c63 - -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00081740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x00440e21 -#ifdef CONFIG_DDR_32BIT -DATA 4 0x021b0040 0x00000017 -DATA 4 0x021b0000 0xc3190000 -#else -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xc31a0000 -#endif -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x0400803a -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803b -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x07208030 -DATA 4 0x021b001c 0x07208038 -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 -DATA 4 0x021b0004 0x0002556d -DATA 4 0x021b4004 0x00011006 -DATA 4 0x021b001c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F -#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c deleted file mode 100644 index c06fd64367..0000000000 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/clock.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <usb.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -int dram_init(void) -{ -#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ - defined(CONFIG_DDR_32BIT) - gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; -#else - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; -#endif - - return 0; -} - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(6, 11)); - ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); - } else /* Don't have the CD GPIO pin on board */ - ret = 1; - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -#define MII_MMD_ACCESS_CTRL_REG 0xd -#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe -#define MII_DBG_PORT_REG 0x1d -#define MII_DBG_PORT2_REG 0x1e - -int fecmxc_mii_postcall(int phy) -{ - unsigned short val; - - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); - val &= 0xffe3; - val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); - - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); - val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct eth_device *dev; - int ret = cpu_eth_init(bis); - - if (ret) - return ret; - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); - - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 1); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 0) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_enet(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif - - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_MX6DL - puts("Board: MX6DL-Armadillo2\n"); -#else - puts("Board: MX6Q-Armadillo2\n"); -#endif - - return 0; -} diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig deleted file mode 100644 index e71dfc4ab2..0000000000 --- a/board/freescale/s32v234evb/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_S32V234EVB - -config SYS_CPU - string - default "armv8" - -config SYS_BOARD - string - default "s32v234evb" - -config SYS_VENDOR - string - default "freescale" - -config SYS_SOC - string - default "s32v234" - -config SYS_CONFIG_NAME - string - default "s32v234evb" - -endif diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS deleted file mode 100644 index 62b2e1b264..0000000000 --- a/board/freescale/s32v234evb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -S32V234 Evaluation BOARD -M: Eddy PetriÈ™or <eddy.petrisor@gmail.com> -S: Maintained -F: arch/arm/cpu/armv8/s32v234/ -F: arch/arm/include/asm/arch-s32v234/ -F: board/freescale/s32v234evb/ -F: include/configs/s32v234evb.h -F: configs/s32v234evb_defconfig diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile deleted file mode 100644 index f6028e1277..0000000000 --- a/board/freescale/s32v234evb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - -obj-y := clock.o -obj-y += lpddr2.o -obj-y += s32v234evb.o - -######################################################################### diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c deleted file mode 100644 index 21c619fa1a..0000000000 --- a/board/freescale/s32v234evb/clock.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/clock.h> - -/* - * Select the clock reference for required pll. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - */ -static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) -{ - u32 clk_src; - u32 pll_idx; - volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR; - - /* select the pll clock source */ - switch (refclk_freq) { - case FIRC_CLK_FREQ: - clk_src = SRC_GPR1_FIRC_CLK_SOURCE; - break; - case XOSC_CLK_FREQ: - clk_src = SRC_GPR1_XOSC_CLK_SOURCE; - break; - default: - /* The clock frequency for the source clock is unknown */ - return -1; - } - /* - * The hardware definition is not uniform, it has to calculate again - * the recurrence formula. - */ - switch (pll) { - case PERIPH_PLL: - pll_idx = 3; - break; - case ENET_PLL: - pll_idx = 1; - break; - case DDR_PLL: - pll_idx = 2; - break; - default: - pll_idx = pll; - } - - writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), - &src->gpr1); - - return 0; -} - -static void entry_to_target_mode(u32 mode) -{ - writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL); - writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL); - while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ; -} - -/* - * Program the pll according to the input parameters. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - * freq - expected output frequency for PHY0 - * freq1 - expected output frequency for PHY1 - * dfs_nr - number of DFS modules for current PLL - * dfs - array with the activation dfs field, mfn and mfi - * plldv_prediv - divider of clkfreq_ref - * plldv_mfd - loop multiplication factor divider - * pllfd_mfn - numerator loop multiplication factor divider - * Please consult the PLLDIG chapter of platform manual - * before to use this function. - *) - */ -static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, - u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv, - u32 plldv_mfd, u32 pllfd_mfn) -{ - u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco; - - /* - * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter. - */ - fvco = - (refclk_freq / plldv_prediv) * (plldv_mfd + - pllfd_mfn / (float)20480); - - /* - * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult - * the platform DataSheet in order to determine the allowed values. - */ - - if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) { - return -1; - } - - if (select_pll_source_clk(pll, refclk_freq) < 0) { - return -1; - } - - rfdphi = fvco / freq0; - - rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1; - - writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) | - PLLDIG_PLLDV_RFDPHI_SET(rfdphi) | - PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) | - PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); - - writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | - PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); - - /* switch on the pll in current mode */ - writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* Only ARM_PLL, ENET_PLL and DDR_PLL */ - if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { - /* DFS clk enable programming */ - writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll)); - - writel(DFS_DLLPRG1_CPICTRL_SET(0x5) | - DFS_DLLPRG1_VSETTLCTRL_SET(0x1) | - DFS_DLLPRG1_CALBYPEN_SET(0x0) | - DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) | - DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll)); - - for (i = 0; i < dfs_nr; i++) { - if (dfs[i][0]) { - writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) | - DFS_DVPORTn_MFN_SET(dfs[i][1]), - DFS_DVPORTn(pll, i)); - dfs_on |= (dfs[i][0] << i); - } - } - - writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET, - DFS_CTRL(pll)); - writel(readl(DFS_PORTRESET(pll)) & - ~DFS_PORTRESET_PORTRESET_SET(dfs_on), - DFS_PORTRESET(pll)); - while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ; - } - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - return 0; - -} - -static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source) -{ - /* select the clock source */ - writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac)); -} - -static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) -{ - /* set the divider */ - writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider), - CGM_ACn_DCm(cgm_addr, ac, dc)); -} - -static void setup_sys_clocks(void) -{ - - /* set ARM PLL DFS 1 as SYSCLK */ - writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) | - MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */ - writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK - (0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) | - MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET) - | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET), - MC_ME_RUNn_SEC_CC_I(0)); - - /* setup the sys clock divider for CORE_CLK (1000MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)); - - /* setup the sys clock divider for CORE2_CLK (500MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1)); - /* setup the sys clock divider for SYS3_CLK (266 MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); - - /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void setup_aux_clocks(void) -{ - /* - * setup the aux clock divider for PERI_CLK - * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) - */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); - - /* setup the aux clock divider for LIN_CLK (40MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); - - /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); - - /* setup the aux clock divider for ENET_CLK (50MHz) */ - aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9); - - /* setup the aux clock divider for SDHC_CLK (50 MHz). */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); - - /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); - /* setup the aux clock divider for DDR4_CLK (133,25MHz) */ - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void enable_modules_clock(void) -{ - /* PIT0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); - /* PIT1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); - /* LINFLEX0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); - /* LINFLEX1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); - /* ENET */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); - /* SDHC */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); - /* IIC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); - /* IIC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); - /* IIC2 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); - /* MMDC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); - /* MMDC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162); - - entry_to_target_mode(MC_ME_MCTL_RUN0); -} - -void clock_init(void) -{ - unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN, - ARM_PLL_PHI1_DFS1_MFI}, - {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN, - ARM_PLL_PHI1_DFS2_MFI}, - {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN, - ARM_PLL_PHI1_DFS3_MFI} - }; - - unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN, - ENET_PLL_PHI1_DFS1_MFI}, - {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN, - ENET_PLL_PHI1_DFS2_MFI}, - {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN, - ENET_PLL_PHI1_DFS3_MFI}, - {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN, - ENET_PLL_PHI1_DFS4_MFI} - }; - - unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN, - DDR_PLL_PHI1_DFS1_MFI}, - {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN, - DDR_PLL_PHI1_DFS2_MFI}, - {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN, - DDR_PLL_PHI1_DFS3_MFI} - }; - - writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 | - MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0)); - - /* turn on FXOSC */ - writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON | - MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ, - ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs, - ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN); - - setup_sys_clocks(); - - program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ, - PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL, - PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD, - PERIPH_PLL_PLLDV_MFN); - - program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ, - ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs, - ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD, - ENET_PLL_PLLDV_MFN); - - program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ, - DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs, - DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN); - - program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ, - VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL, - VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD, - VIDEO_PLL_PLLDV_MFN); - - setup_aux_clocks(); - - enable_modules_clock(); - -} diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c deleted file mode 100644 index b3775d3763..0000000000 --- a/board/freescale/s32v234evb/lpddr2.c +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/mmdc.h> - -volatile int mscr_offset_ck0; - -void lpddr2_config_iomux(uint8_t module) -{ - int i; - - switch (module) { - case DDR0: - mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); - - for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_A0; i <= _DDR0_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_D0; i <= _DDR0_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - case DDR1: - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); - - for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_A0; i <= _DDR1_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_D0; i <= _DDR1_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - } -} - -void config_mmdc(uint8_t module) -{ - unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; - - writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); - - writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); - writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); - writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); - writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); - writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); - writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); - writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); - writel(_MDCTL, mmdc_addr + MMDC_MDCTL); - - writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); - - while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { - } - - writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Perform ZQ calibration */ - writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); - writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); - while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { - } - - /* Enable MMDC with CS0 */ - writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); - - /* Complete the initialization sequence as defined by JEDEC */ - writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Set the amount of DRAM */ - /* Set DQS settings based on board type */ - - switch (module) { - case MMDC0: - writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - case MMDC1: - writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - } - - writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); - writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); - writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); - writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); - writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); - -} diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c deleted file mode 100644 index 304f5acf3b..0000000000 --- a/board/freescale/s32v234evb/s32v234evb.c +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -void setup_iomux_ddr(void) -{ - lpddr2_config_iomux(DDR0); - lpddr2_config_iomux(DDR1); - -} - -void ddr_phy_init(void) -{ -} - -void ddr_ctrl_init(void) -{ - config_mmdc(0); - config_mmdc(1); -} - -int dram_init(void) -{ - setup_iomux_ddr(); - - ddr_ctrl_init(); - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static void setup_iomux_uart(void) -{ - /* Muxing for linflex */ - /* Replace the magic values after bringup */ - - /* set TXD - MSCR[12] PA12 */ - writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); - - /* set RXD - MSCR[11] - PA11 */ - writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); - - /* set RXD - IMCR[200] - 200 */ - writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); -} - -static void setup_iomux_enet(void) -{ -} - -static void setup_iomux_i2c(void) -{ -} - -#ifdef CONFIG_SYS_USE_NAND -void setup_iomux_nfc(void) -{ -} -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {USDHC_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(struct bd_info * bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); - - /* Set iomux PADS for USDHC */ - - /* PK6 pad: uSDHC clk */ - writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); - writel(0x3, SIUL2_MSCRn(902)); - - /* PK7 pad: uSDHC CMD */ - writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); - writel(0x3, SIUL2_MSCRn(901)); - - /* PK8 pad: uSDHC DAT0 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); - writel(0x3, SIUL2_MSCRn(903)); - - /* PK9 pad: uSDHC DAT1 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); - writel(0x3, SIUL2_MSCRn(904)); - - /* PK10 pad: uSDHC DAT2 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); - writel(0x3, SIUL2_MSCRn(905)); - - /* PK11 pad: uSDHC DAT3 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); - writel(0x3, SIUL2_MSCRn(906)); - - /* PK15 pad: uSDHC DAT4 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); - writel(0x3, SIUL2_MSCRn(907)); - - /* PL0 pad: uSDHC DAT5 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); - writel(0x3, SIUL2_MSCRn(908)); - - /* PL1 pad: uSDHC DAT6 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); - writel(0x3, SIUL2_MSCRn(909)); - - /* PL2 pad: uSDHC DAT7 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); - writel(0x3, SIUL2_MSCRn(910)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -static void mscm_init(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - int i; - - for (i = 0; i < MSCM_IRSPRC_NUM; i++) - writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - clock_init(); - mscm_init(); - - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); -#ifdef CONFIG_SYS_USE_NAND - setup_iomux_nfc(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: s32v234evb\n"); - - return 0; -} diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg deleted file mode 100644 index d7f7220063..0000000000 --- a/board/freescale/s32v234evb/s32v234evb.cfg +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -/* - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 -BOOT_FROM sd - - -/* - * Boot Device : one of qspi, sd: - * qspi: flash_offset: 0x1000 - * sd/mmc: flash_offset: 0x1000 - */ - - -#ifdef CONFIG_IMX_HAB -SECURE_BOOT -#endif diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 5a435c2695..f65d8eed54 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T2080QDS || TARGET_T2081QDS +if TARGET_T2080QDS config SYS_BOARD default "t208xqds" diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 587903a623..55b1e7390a 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o -obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index aaa3490aaa..705387af3c 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -42,13 +42,6 @@ #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 #define EMI2 7 -#elif defined(CONFIG_TARGET_T2081QDS) -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT5 5 -#define EMI1_SLOT6 6 -#define EMI1_SLOT7 7 -#define EMI2 8 #endif #define PCCR1_SGMIIA_KX_MASK 0x00008000 @@ -72,24 +65,12 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", -#elif defined(CONFIG_TARGET_T2081QDS) - "T2081QDS_MDIO_RGMII1", - "T2081QDS_MDIO_RGMII2", - "T2081QDS_MDIO_SLOT1", - "T2081QDS_MDIO_SLOT2", - "T2081QDS_MDIO_SLOT3", - "T2081QDS_MDIO_SLOT5", - "T2081QDS_MDIO_SLOT6", - "T2081QDS_MDIO_SLOT7", - "T2081QDS_MDIO_10GC", #endif }; /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ #if defined(CONFIG_TARGET_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#elif defined(CONFIG_TARGET_T2081QDS) -static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; #endif static const char *t208xqds_mdio_name_for_muxval(u8 muxval) @@ -316,35 +297,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; -#elif defined(CONFIG_TARGET_T2081QDS) - case FM1_DTSEC1: - case FM1_DTSEC2: - case FM1_DTSEC5: - case FM1_DTSEC6: - case FM1_DTSEC9: - case FM1_DTSEC10: - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } else if (mdio_mux[port] == EMI1_SLOT5) { - sprintf(alias, "phy_sgmii_s5_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - } else if (mdio_mux[port] == EMI1_SLOT6) { - sprintf(alias, "phy_sgmii_s6_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot6"); - } else if (mdio_mux[port] == EMI1_SLOT7) { - sprintf(alias, "phy_sgmii_s7_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot7"); - } - break; #endif default: break; @@ -495,30 +447,6 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0x6b: - lane_to_slot[4] = 1; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xca: - case 0xcb: - lane_to_slot[1] = 7; - lane_to_slot[2] = 6; - lane_to_slot[3] = 5; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xf2: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - lane_to_slot[5] = 4; - lane_to_slot[6] = 3; - lane_to_slot[7] = 7; - break; #endif default: break; @@ -570,10 +498,6 @@ int board_eth_init(struct bd_info *bis) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); -#if defined(CONFIG_TARGET_T2081QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); -#endif t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ @@ -689,19 +613,6 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0xca: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - /* SGMII in Slot5 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - /* SGMII in Slot6 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - /* SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - break; #endif case 0xf2: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ @@ -745,23 +656,6 @@ int board_eth_init(struct bd_info *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; -#if defined(CONFIG_TARGET_T2081QDS) - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 6: - mdio_mux[i] = EMI1_SLOT6; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 7: - mdio_mux[i] = EMI1_SLOT7; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; -#endif } break; case PHY_INTERFACE_MODE_RGMII: diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 36bb399293..fd3217f24d 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -209,76 +209,6 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0x1a); break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0x50: - case 0x51: - /* SD1(A:D) => SLOT2 XAUI - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x98); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0x6a: - case 0x6b: - /* SD1(A:D) => XFI SFP Module - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x80); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0x6c: - case 0x6d: - /* SD1(A:B) => XFI SFP Module - * SD1(C:D) => SLOT2 SGMII - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0xe8); - QIXIS_WRITE(brdcfg[13], 0x0); - break; - case 0xaa: - case 0xab: - /* SD1(A:D) => SLOT2 PCIe3 x4 - * SD1(F:H) => SLOT1 SGMI4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0xf8); - QIXIS_WRITE(brdcfg[13], 0x0); - break; - case 0xca: - case 0xcb: - /* SD1(A) => SLOT2 PCIe3 x1 - * SD1(B) => SLOT7 SGMII - * SD1(C) => SLOT6 SGMII - * SD1(D) => SLOT5 SGMII - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x80); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0xde: - case 0xdf: - /* SD1(A:D) => SLOT2 PCIe3 x4 - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F) => SLOT4 PCIe1 x1 - * SD1(G) => SLOT3 PCIe2 x1 - * SD1(H) => SLOT7 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x98); - QIXIS_WRITE(brdcfg[13], 0x25); - break; - case 0xf2: - /* SD1(A) => SLOT2 PCIe3 x1 - * SD1(B:D) => SLOT7 SGMII - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F) => SLOT4 PCIe1 x1 - * SD1(G) => SLOT3 PCIe2 x1 - * SD1(H) => SLOT7 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x81); - QIXIS_WRITE(brdcfg[13], 0xa5); - break; #endif default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 7dfe104561..dd6d5e69de 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -6,11 +6,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o -obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o -obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o -obj-$(CONFIG_STRIDER_CON) += osd.o -obj-$(CONFIG_STRIDER_CON_DP) += osd.o obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c deleted file mode 100644 index 06cdc05825..0000000000 --- a/board/gdsys/common/adv7611.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <i2c.h> - -#define ADV7611_I2C_ADDR 0x4c -#define ADV7611_RDINFO 0x2051 - -/* - * ADV7611 I2C Addresses in u-boot notation - */ -enum { - CP_I2C_ADDR = 0x22, - DPLL_I2C_ADDR = 0x26, - KSV_I2C_ADDR = 0x32, - HDMI_I2C_ADDR = 0x34, - EDID_I2C_ADDR = 0x36, - INFOFRAME_I2C_ADDR = 0x3e, - CEC_I2C_ADDR = 0x40, - IO_I2C_ADDR = ADV7611_I2C_ADDR, -}; - -/* - * Global Control Registers - */ -enum { - IO_RD_INFO_MSB = 0xea, - IO_RD_INFO_LSB = 0xeb, - IO_CEC_ADDR = 0xf4, - IO_INFOFRAME_ADDR = 0xf5, - IO_DPLL_ADDR = 0xf8, - IO_KSV_ADDR = 0xf9, - IO_EDID_ADDR = 0xfa, - IO_HDMI_ADDR = 0xfb, - IO_CP_ADDR = 0xfd, -}; - -int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C; - -int adv7611_probe(unsigned int screen) -{ - int old_bus = i2c_get_bus_num(); - unsigned int rd_info; - int res = 0; - - i2c_set_bus_num(adv7611_i2c[screen]); - - rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8) - | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB); - - if (rd_info != ADV7611_RDINFO) { - res = -1; - goto out; - } - - /* - * set I2C addresses to default values - */ - i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1); - - /* - * do magic initialization sequence from - * "ADV7611 Register Settings Recommendations Revision 1.5" - * with most registers undocumented - */ - i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00); - i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03); - i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08); - i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f); - i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70); - i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda); - i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01); - i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98); - i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44); - - /* - * IO_REG_02, default 0xf0 - * - * INP_COLOR_SPACE (IO, Address 0x02[7:4]) - * default: 0b1111 auto - * set to : 0b0001 force RGB (range 0 to 255) input - * - * RGB_OUT (IO, Address 0x02[1]) - * default: 0 YPbPr color space output - * set to : 1 RGB color space output - */ - i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12); - - /* - * IO_REG_03, default 0x00 - * - * OP_FORMAT_SEL (IO, Address 0x03[7:0]) - * default: 0x00 8-bit SDR ITU-656 mode - * set to : 0x40 24-bit 4:4:4 SDR mode - */ - i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40); - - /* - * IO_REG_05, default 0x2c - * - * AVCODE_INSERT_EN (IO, Address 0x05[2]) - * default: 1 insert AV codes into data stream - * set to : 0 do not insert AV codes into data stream - */ - i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28); - - /* - * IO_REG_0C, default 0x62 - * - * POWER_DOWN (IO, Address 0x0C[5]) - * default: 1 chip is powered down - * set to : 0 chip is operational - */ - i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42); - - /* - * IO_REG_15, default 0xbe - * - * TRI_SYNCS (IO, Address 0x15[3) - * TRI_LLC (IO, Address 0x15[2]) - * TRI_PIX (IO, Address 0x15[1]) - * default: 1 video output pins are tristate - * set to : 0 video output pins are active - */ - i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0); - - /* - * HDMI_REGISTER_02H, default 0xff - * - * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0]) - * default: 1 disable termination - * set to : 0 enable termination - * Future options are: - * - use the chips automatic termination control - * - set this manually on cable detect - * but at the moment this seems a safe default. - */ - i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe); - - /* - * HDMI_CP_CNTRL_1, default 0x01 - * - * HDMI_FRUN_EN (CP, Address 0xBA[0]) - * default: 1 Enable the free run feature in HDMI mode - * set to : 0 Disable the free run feature in HDMI mode - */ - i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00); - - /* - * INT1_CONFIGURATION, default 0x20 - * - * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6]) - * default: 00 Interrupt signal is active for 4 Xtal periods - * set to : 11 Active until cleared - * - * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0]) - * default: 00 Open drain - * set to : 10 Drives high when active - */ - i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2); - -out: - i2c_set_bus_num(old_bus); - - return res; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h deleted file mode 100644 index 7b4e27c6bc..0000000000 --- a/board/gdsys/common/adv7611.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _ADV7611_H_ -#define _ADV7611_H_ - -int adv7611_probe(unsigned int screen); - -#endif diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c deleted file mode 100644 index 5e42467651..0000000000 --- a/board/gdsys/common/ch7301.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -/* Chrontel CH7301C DVI Transmitter */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <asm/io.h> -#include <errno.h> -#include <i2c.h> - -#define CH7301_I2C_ADDR 0x75 - -enum { - CH7301_CM = 0x1c, /* Clock Mode Register */ - CH7301_IC = 0x1d, /* Input Clock Register */ - CH7301_GPIO = 0x1e, /* GPIO Control Register */ - CH7301_IDF = 0x1f, /* Input Data Format Register */ - CH7301_CD = 0x20, /* Connection Detect Register */ - CH7301_DC = 0x21, /* DAC Control Register */ - CH7301_HPD = 0x23, /* Hot Plug Detection Register */ - CH7301_TCTL = 0x31, /* DVI Control Input Register */ - CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ - CH7301_TPD = 0x34, /* DVI PLL Divide Register */ - CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ - CH7301_TPF = 0x36, /* DVI PLL Filter Register */ - CH7301_TCT = 0x37, /* DVI Clock Test Register */ - CH7301_TSTP = 0x48, /* Test Pattern Register */ - CH7301_PM = 0x49, /* Power Management register */ - CH7301_VID = 0x4a, /* Version ID Register */ - CH7301_DID = 0x4b, /* Device ID Register */ - CH7301_DSP = 0x56, /* DVI Sync polarity Register */ -}; - -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; - -int ch7301_probe(unsigned screen, bool power) -{ - u8 value; - - i2c_set_bus_num(ch7301_i2c[screen]); - if (i2c_probe(CH7301_I2C_ADDR)) - return -1; - - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - if (value != 0x17) - return -1; - - if (power) { - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); - } else { - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01); - } - - return 0; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h deleted file mode 100644 index e0e8a9e9d4..0000000000 --- a/board/gdsys/common/ch7301.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _CH7301_H_ -#define _CH7301_H_ - -int ch7301_probe(unsigned screen, bool power); - -#endif diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c deleted file mode 100644 index 27c875cbec..0000000000 --- a/board/gdsys/common/fanctrl.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <i2c.h> - -enum { - FAN_CONFIG = 0x03, - FAN_TACHLIM_LSB = 0x48, - FAN_TACHLIM_MSB = 0x49, - FAN_PWM_FREQ = 0x4D, -}; - -void init_fan_controller(u8 addr) -{ - int val; - - /* set PWM Frequency to 2.5% resolution */ - i2c_reg_write(addr, FAN_PWM_FREQ, 20); - - /* set Tachometer Limit */ - i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10); - i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a); - - /* enable Tach input */ - val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; - i2c_reg_write(addr, FAN_CONFIG, val); -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h deleted file mode 100644 index ab7e58def5..0000000000 --- a/board/gdsys/common/fanctrl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _FANCTRL_H_ -#define _FANCTRL_H_ - -void init_fan_controller(u8 addr); - -#endif diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c deleted file mode 100644 index 6147fbfc87..0000000000 --- a/board/gdsys/common/mclink.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <asm/io.h> -#include <errno.h> - -#include <gdsys_fpga.h> -#include <linux/delay.h> - -enum { - MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7, - MCINT_TX_ERROR_EV = 1 << 9, - MCINT_TX_BUFFER_FREE = 1 << 10, - MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11, - MCINT_RX_ERROR_EV = 1 << 13, - MCINT_RX_CONTENT_AVAILABLE = 1 << 14, - MCINT_RX_PACKET_RECEIVED_EV = 1 << 15, -}; - -int mclink_probe(void) -{ - unsigned int k; - int slaves = 0; - - for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) { - int timeout = 0; - unsigned int ctr = 0; - u16 mc_status; - - FPGA_GET_REG(k, mc_status, &mc_status); - - if (!(mc_status & (1 << 15))) - break; - - FPGA_SET_REG(k, mc_control, 0x8000); - - FPGA_GET_REG(k, mc_status, &mc_status); - while (!(mc_status & (1 << 14))) { - udelay(100); - if (ctr++ > 500) { - timeout = 1; - break; - } - FPGA_GET_REG(k, mc_status, &mc_status); - } - if (timeout) - break; - - printf("waited %d us for mclink %d to come up\n", ctr * 100, k); - - slaves++; - } - - return slaves; -} - -int mclink_send(u8 slave, u16 addr, u16 data) -{ - unsigned int ctr = 0; - u16 int_status; - u16 rx_cmd_status; - u16 rx_cmd; - - /* reset interrupt status */ - FPGA_GET_REG(0, mc_int, &int_status); - FPGA_SET_REG(0, mc_int, int_status); - - /* send */ - FPGA_SET_REG(0, mc_tx_address, addr); - FPGA_SET_REG(0, mc_tx_data, data); - FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); - FPGA_SET_REG(0, mc_control, 0x8001); - - /* wait for reply */ - FPGA_GET_REG(0, mc_int, &int_status); - while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { - udelay(100); - if (ctr++ > 3) - return -ETIMEDOUT; - FPGA_GET_REG(0, mc_int, &int_status); - } - - FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); - rx_cmd = (rx_cmd_status >> 12) & 0x03; - if (rx_cmd != 0) - printf("mclink_send: received cmd %d, expected %d\n", rx_cmd, - 0); - - return 0; -} - -int mclink_receive(u8 slave, u16 addr, u16 *data) -{ - u16 rx_cmd_status; - u16 rx_cmd; - u16 int_status; - unsigned int ctr = 0; - - /* send read request */ - FPGA_SET_REG(0, mc_tx_address, addr); - FPGA_SET_REG(0, mc_tx_cmd, - ((slave & 0x03) << 14) | (1 << 12) | (1 << 0)); - FPGA_SET_REG(0, mc_control, 0x8001); - - - /* wait for reply */ - FPGA_GET_REG(0, mc_int, &int_status); - while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { - udelay(100); - if (ctr++ > 3) - return -ETIMEDOUT; - FPGA_GET_REG(0, mc_int, &int_status); - } - - /* check reply */ - FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); - if ((rx_cmd_status >> 14) != slave) { - printf("mclink_receive: reply from slave %d, expected %d\n", - rx_cmd_status >> 14, slave); - return -EINVAL; - } - - rx_cmd = (rx_cmd_status >> 12) & 0x03; - if (rx_cmd != 1) { - printf("mclink_send: received cmd %d, expected %d\n", - rx_cmd, 1); - return -EIO; - } - - FPGA_GET_REG(0, mc_rx_data, data); - - return 0; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h deleted file mode 100644 index 4dc4058892..0000000000 --- a/board/gdsys/common/mclink.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _MCLINK_H_ -#define _MCLINK_H_ - -int mclink_probe(void); -int mclink_send(u8 slave, u16 addr, u16 data); -int mclink_receive(u8 slave, u16 addr, u16 *data); - -#endif diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c deleted file mode 100644 index 516f4e8edc..0000000000 --- a/board/gdsys/common/phy.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include <common.h> -#include <log.h> - -#include <miiphy.h> - -enum { - MIICMD_SET, - MIICMD_MODIFY, - MIICMD_VERIFY_VALUE, - MIICMD_WAIT_FOR_VALUE, -}; - -struct mii_setupcmd { - u8 token; - u8 reg; - u16 data; - u16 mask; - u32 timeout; -}; - -/* - * verify we are talking to a 88e1518 - */ -struct mii_setupcmd verify_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, - { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, -}; - -/* - * workaround for erratum mentioned in 88E1518 release notes - */ -struct mii_setupcmd fixup_88e1518[] = { - { MIICMD_SET, 22, 0x00ff }, - { MIICMD_SET, 17, 0x214b }, - { MIICMD_SET, 16, 0x2144 }, - { MIICMD_SET, 17, 0x0c28 }, - { MIICMD_SET, 16, 0x2146 }, - { MIICMD_SET, 17, 0xb233 }, - { MIICMD_SET, 16, 0x214d }, - { MIICMD_SET, 17, 0xcc0c }, - { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * default initialization: - * - set RGMII receive timing to "receive clock transition when data stable" - * - set RGMII transmit timing to "transmit clock internally delayed" - * - set RGMII output impedance target to 78,8 Ohm - * - run output impedance calibration - * - set autonegotiation advertise to 1000FD only - */ -struct mii_setupcmd default_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, - { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, - { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, - { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, -}; - -/* - * turn off CLK125 for PHY daughterboard - */ -struct mii_setupcmd ch1fix_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * perform copper software reset - */ -struct mii_setupcmd swreset_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, -}; - -/* - * special one for 88E1514: - * Force SGMII to Copper mode - */ -struct mii_setupcmd mii_to_copper_88e1514[] = { - { MIICMD_SET, 22, 0x0012 }, - { MIICMD_MODIFY, 20, 0x0001, 0x0007 }, - { MIICMD_MODIFY, 20, 0x8000, 0x8000 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * turn off SGMII auto-negotiation - */ -struct mii_setupcmd sgmii_autoneg_off_88e1518[] = { - { MIICMD_SET, 22, 0x0001 }, - { MIICMD_MODIFY, 0, 0x0000, 0x1000 }, - { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * invert LED2 polarity - */ -struct mii_setupcmd invert_led2_88e1514[] = { - { MIICMD_SET, 22, 0x0003 }, - { MIICMD_MODIFY, 17, 0x0030, 0x0010 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -static int process_setupcmd(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd) -{ - int res; - u8 reg = setupcmd->reg; - u16 data = setupcmd->data; - u16 mask = setupcmd->mask; - u32 timeout = setupcmd->timeout; - u16 orig_data; - unsigned long start; - - debug("mii %s:%u reg %2u ", bus, addr, reg); - - switch (setupcmd->token) { - case MIICMD_MODIFY: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - debug("is %04x. (value %04x mask %04x) ", orig_data, data, - mask); - data = (orig_data & ~mask) | (data & mask); - /* fallthrough */ - case MIICMD_SET: - debug("=> %04x\n", data); - res = miiphy_write(bus, addr, reg, data); - break; - case MIICMD_VERIFY_VALUE: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - if ((orig_data & mask) != (data & mask)) - res = -1; - debug("(value %04x mask %04x) == %04x? %s\n", data, mask, - orig_data, res ? "FAIL" : "PASS"); - break; - case MIICMD_WAIT_FOR_VALUE: - res = -1; - start = get_timer(0); - while ((res != 0) && (get_timer(start) < timeout)) { - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - continue; - if ((orig_data & mask) != (data & mask)) - res = -1; - } - debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, - mask, orig_data, res ? "FAIL" : "PASS", - get_timer(start)); - break; - default: - res = -1; - break; - } - - return res; -} - -static int process_setup(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd, unsigned int count) -{ - int res = 0; - unsigned int k; - - for (k = 0; k < count; ++k) { - res = process_setupcmd(bus, addr, &setupcmd[k]); - if (res) { - printf("mii cmd %u on bus %s addr %u failed, aborting setup\n", - setupcmd[k].token, bus, addr); - break; - } - } - - return res; -} - -int setup_88e1518(const char *bus, unsigned char addr) -{ - int res; - - res = process_setup(bus, addr, - verify_88e1518, ARRAY_SIZE(verify_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - default_88e1518, ARRAY_SIZE(default_88e1518)); - if (res) - return res; - - if (addr) { - res = process_setup(bus, addr, - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); - if (res) - return res; - } - - res = process_setup(bus, addr, - swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); - if (res) - return res; - - return 0; -} - -int setup_88e1514(const char *bus, unsigned char addr) -{ - int res; - - res = process_setup(bus, addr, - verify_88e1518, ARRAY_SIZE(verify_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - mii_to_copper_88e1514, - ARRAY_SIZE(mii_to_copper_88e1514)); - if (res) - return res; - - res = process_setup(bus, addr, - sgmii_autoneg_off_88e1518, - ARRAY_SIZE(sgmii_autoneg_off_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - invert_led2_88e1514, - ARRAY_SIZE(invert_led2_88e1514)); - if (res) - return res; - - res = process_setup(bus, addr, - default_88e1518, ARRAY_SIZE(default_88e1518)); - if (res) - return res; - - if (addr) { - res = process_setup(bus, addr, - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); - if (res) - return res; - } - - res = process_setup(bus, addr, - swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); - if (res) - return res; - - return 0; -} diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h deleted file mode 100644 index e0aa661b9c..0000000000 --- a/board/gdsys/common/phy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _PHY_H_ -#define _PHY_H_ - -int setup_88e1514(const char *bus, unsigned char addr); -int setup_88e1518(const char *bus, unsigned char addr); - -#endif diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 30811889fb..c3fd0518bc 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -1,3 +1,5 @@ +if TARGET_GAZERBEAM + config GDSYS_LEGACY_OSD_CMDS bool help @@ -33,46 +35,6 @@ config SYS_FPGA1_SIZE help The base address of the second FPGA's register map. -if TARGET_HRCON - -config SYS_BOARD - default "mpc8308" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "hrcon" - -config GDSYS_LEGACY_OSD_CMDS - default y - -config GDSYS_LEGACY_DRIVERS - default y - -endif - -if TARGET_STRIDER - -config SYS_BOARD - default "mpc8308" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "strider" - -config GDSYS_LEGACY_OSD_CMDS - default y - -config GDSYS_LEGACY_DRIVERS - default y - -endif - -if TARGET_GAZERBEAM - config SYS_BOARD default "mpc8308" @@ -90,9 +52,6 @@ config SYS_FPGA1_SIZE config GDSYS_LEGACY_OSD_CMDS default y -endif - -if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM choice prompt "FPGA flavor selection" diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index ed1b6fa106..dc0b389f73 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -2,13 +2,5 @@ MPC8308 BOARD M: Dirk Eibach <dirk.eibach@gdsys.cc> S: Maintained F: board/gdsys/mpc8308/ -F: include/configs/hrcon.h -F: configs/hrcon_defconfig -F: configs/hrcon_dh_defconfig -F: include/configs/strider.h -F: configs/strider_defconfig -F: configs/strider_cpu_defconfig -F: configs/strider_cpu_dp_defconfig -F: configs/strider_con_defconfig -F: configs/strider_con_dp_defconfig +F: include/configs/gazerbeam.h F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index 9af5fe04d1..f86d997bc7 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -4,6 +4,4 @@ # Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc obj-y := mpc8308.o sdram.o -obj-$(CONFIG_TARGET_HRCON) += hrcon.o -obj-$(CONFIG_TARGET_STRIDER) += strider.o obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c deleted file mode 100644 index b5c681c2d1..0000000000 --- a/board/gdsys/mpc8308/hrcon.c +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include <common.h> -#include <env.h> -#include <flash.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <spi.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <pci.h> -#include <mpc83xx.h> -#include <fsl_esdhc.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_mpc83xx_serdes.h> - -#include "mpc8308.h" - -#include <gdsys_fpga.h> - -#include "../common/ioep-fpga.h" -#include "../common/osd.h" -#include "../common/mclink.h" -#include "../common/phy.h" -#include "../common/fanctrl.h" - -#include <pca953x.h> -#include <pca9698.h> - -#include <miiphy.h> - -#define MAX_MUX_CHANNELS 2 - -enum { - MCFPGA_DONE = BIT(0), - MCFPGA_INIT_N = BIT(1), - MCFPGA_PROGRAM_N = BIT(2), - MCFPGA_UPDATE_ENABLE_N = BIT(3), - MCFPGA_RESET_N = BIT(4), -}; - -enum { - GPIO_MDC = 1 << 14, - GPIO_MDIO = 1 << 15, -}; - -uint mclink_fpgacount; -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -struct { - u8 bus; - u8 addr; -} hrcon_fans[] = CONFIG_HRCON_FANS; - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - int res; - - switch (fpga) { - case 0: - out_le16(reg, data); - break; - default: - res = mclink_send(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_send reg %02lx data %04x returned %d\n", - regoff, data, res); - return res; - } - break; - } - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - int res; - - switch (fpga) { - case 0: - *data = in_le16(reg); - break; - default: - if (fpga > mclink_fpgacount) - return -EINVAL; - res = mclink_receive(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_receive reg %02lx returned %d\n", - regoff, res); - return res; - } - } - - return 0; -} - -int checkboard(void) -{ - char *s = env_get("serial#"); - bool hw_type_cat = pca9698_get_value(0x20, 20); - - puts("Board: "); - - printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); - - if (s) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -int last_stage_init(void) -{ - int slaves; - uint k; - uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; - u16 fpga_features; - bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present; - - FPGA_GET_REG(0, fpga_features, &fpga_features); - - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 10, 1); - pca9698_direction_output(0x20, 11, 1); - - ch0_rgmii2_present = !pca9698_get_value(0x20, 30); - - /* wait for FPGA done, then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - uint ctr = 0; - - if (i2c_probe(mclink_controllers[k])) - continue; - - while (!(pca953x_get_val(mclink_controllers[k]) - & MCFPGA_DONE)) { - mdelay(100); - if (ctr++ > 5) { - printf("no done for mclink_controller %u\n", k); - break; - } - } - - pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); - udelay(10); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, - MCFPGA_RESET_N); - } - - if (hw_type_cat) { - uint mux_ch; - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { - if ((mux_ch == 1) && !ch0_rgmii2_present) - continue; - - setup_88e1514(bb_miiphy_buses[0].name, mux_ch); - } - } - - /* give slave-PLLs and Parade DP501 some time to be up and running */ - mdelay(500); - - mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; - slaves = mclink_probe(); - mclink_fpgacount = 0; - - ioep_fpga_print_info(0); - osd_probe(0); -#ifdef CONFIG_SYS_OSD_DH - osd_probe(4); -#endif - - if (slaves <= 0) - return 0; - - mclink_fpgacount = slaves; - - for (k = 1; k <= slaves; ++k) { - FPGA_GET_REG(k, fpga_features, &fpga_features); - - ioep_fpga_print_info(k); - osd_probe(k); -#ifdef CONFIG_SYS_OSD_DH - osd_probe(k + 4); -#endif - if (hw_type_cat) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[k].name, - MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - setup_88e1514(bb_miiphy_buses[k].name, 0); - } - } - - for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) { - i2c_set_bus_num(hrcon_fans[k].bus); - init_fan_controller(hrcon_fans[k].addr); - } - - return 0; -} - -/* - * provide access to fpga gpios and controls (for I2C bitbang) - * (these may look all too simple but make iocon.h much more readable) - */ -void fpga_gpio_set(uint bus, int pin) -{ - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); -} - -void fpga_gpio_clear(uint bus, int pin) -{ - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); -} - -int fpga_gpio_get(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val); - - return val & pin; -} - -void fpga_control_set(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); -} - -void fpga_control_clear(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); -} - -void mpc8308_init(void) -{ - pca9698_direction_output(0x20, 4, 1); -} - -void mpc8308_set_fpga_reset(uint state) -{ - pca9698_set_value(0x20, 4, state ? 0 : 1); -} - -void mpc8308_setup_hw(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * set "startup-finished"-gpios - */ - setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); - setbits_gpio0_out(BIT(31 - 12)); -} - -int mpc8308_get_fpga_done(uint fpga) -{ - return pca9698_get_value(0x20, 19); -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - - /* Enable cache snooping in eSDHC system configuration register */ - out_be32(&sysconf->sdhccr, 0x02000000); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *pcie_reg[] = { pcie_regions_0 }; - - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(1, pcie_reg); -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif - -/* - * FPGA MII bitbang implementation - */ - -struct fpga_mii { - uint fpga; - int mdio; -} fpga_mii[] = { - { 0, 1}, - { 1, 1}, - { 2, 1}, - { 3, 1}, -}; - -static int mii_dummy_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int mii_mdio_active(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (fpga_mii->mdio) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - return 0; -} - -static int mii_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - - return 0; -} - -static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - fpga_mii->mdio = v; - - return 0; -} - -static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - u16 gpio; - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); - - *v = ((gpio & GPIO_MDIO) != 0); - - return 0; -} - -static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); - - return 0; -} - -static int mii_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "board0", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[0], - }, - { - .name = "board1", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[1], - }, - { - .name = "board2", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[2], - }, - { - .name = "board3", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[3], - }, -}; - -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c deleted file mode 100644 index 91fec74fb0..0000000000 --- a/board/gdsys/mpc8308/strider.c +++ /dev/null @@ -1,559 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include <common.h> -#include <env.h> -#include <flash.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <spi.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <pci.h> -#include <mpc83xx.h> -#include <fsl_esdhc.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_mpc83xx_serdes.h> - -#include "mpc8308.h" - -#include <gdsys_fpga.h> - -#include "../common/adv7611.h" -#include "../common/ch7301.h" -#include "../common/dp501.h" -#include "../common/ioep-fpga.h" -#include "../common/mclink.h" -#include "../common/osd.h" -#include "../common/phy.h" -#include "../common/fanctrl.h" - -#include <pca953x.h> -#include <pca9698.h> - -#include <miiphy.h> - -#define MAX_MUX_CHANNELS 2 - -enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, -}; - -enum { - GPIO_MDC = 1 << 14, - GPIO_MDIO = 1 << 15, -}; - -uint mclink_fpgacount; -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -struct { - u8 bus; - u8 addr; -} strider_fans[] = CONFIG_STRIDER_FANS; - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - int res; - - switch (fpga) { - case 0: - out_le16(reg, data); - break; - default: - res = mclink_send(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_send reg %02lx data %04x returned %d\n", - regoff, data, res); - return res; - } - break; - } - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - int res; - - switch (fpga) { - case 0: - *data = in_le16(reg); - break; - default: - if (fpga > mclink_fpgacount) - return -EINVAL; - res = mclink_receive(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_receive reg %02lx returned %d\n", - regoff, res); - return res; - } - } - - return 0; -} - -int checkboard(void) -{ - char *s = env_get("serial#"); - bool hw_type_cat = pca9698_get_value(0x20, 18); - - puts("Board: "); - - printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); - - if (s) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -int last_stage_init(void) -{ - int slaves; - uint k; - uint mux_ch; - uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; -#ifdef CONFIG_STRIDER_CPU - uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; -#endif - bool hw_type_cat = pca9698_get_value(0x20, 18); -#ifdef CONFIG_STRIDER_CON_DP - bool is_dh = pca9698_get_value(0x20, 25); -#endif - bool ch0_sgmii2_present; - - /* Turn on Analog Devices ADV7611 */ - pca9698_direction_output(0x20, 8, 0); - - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 10, 1); - pca9698_direction_output(0x20, 11, 1); - - ch0_sgmii2_present = !pca9698_get_value(0x20, 37); - - /* wait for FPGA done, then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { - uint ctr = 0; - uchar *mclink_controllers = mclink_controllers_dvi; - -#ifdef CONFIG_STRIDER_CPU - if (i2c_probe(mclink_controllers[k])) { - mclink_controllers = mclink_controllers_dp; - if (i2c_probe(mclink_controllers[k])) - continue; - } -#else - if (i2c_probe(mclink_controllers[k])) - continue; -#endif - while (!(pca953x_get_val(mclink_controllers[k]) - & MCFPGA_DONE)) { - mdelay(100); - if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); - break; - } - } - - pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); - udelay(10); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, - MCFPGA_RESET_N); - } - - if (hw_type_cat) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { - if ((mux_ch == 1) && !ch0_sgmii2_present) - continue; - - setup_88e1514(bb_miiphy_buses[0].name, mux_ch); - } - } - - /* give slave-PLLs and Parade DP501 some time to be up and running */ - mdelay(500); - - mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; - slaves = mclink_probe(); - mclink_fpgacount = 0; - - ioep_fpga_print_info(0); - - if (!adv7611_probe(0)) - printf(" Advantiv ADV7611 HDMI Receiver\n"); - -#ifdef CONFIG_STRIDER_CON - if (ioep_fpga_has_osd(0)) - osd_probe(0); -#endif - -#ifdef CONFIG_STRIDER_CON_DP - if (ioep_fpga_has_osd(0)) { - osd_probe(0); - if (is_dh) - osd_probe(4); - } -#endif - -#ifdef CONFIG_STRIDER_CPU - ch7301_probe(0, false); - dp501_probe(0, false); -#endif - - if (slaves <= 0) - return 0; - - mclink_fpgacount = slaves; - -#ifdef CONFIG_STRIDER_CPU - /* get ADV7611 out of reset, power up DP501, give some time to wakeup */ - for (k = 1; k <= slaves; ++k) - FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ - - mdelay(500); -#endif - - for (k = 1; k <= slaves; ++k) { - ioep_fpga_print_info(k); -#ifdef CONFIG_STRIDER_CON - if (ioep_fpga_has_osd(k)) - osd_probe(k); -#endif -#ifdef CONFIG_STRIDER_CON_DP - if (ioep_fpga_has_osd(k)) { - osd_probe(k); - if (is_dh) - osd_probe(k + 4); - } -#endif -#ifdef CONFIG_STRIDER_CPU - if (!adv7611_probe(k)) - printf(" Advantiv ADV7611 HDMI Receiver\n"); - ch7301_probe(k, false); - dp501_probe(k, false); -#endif - if (hw_type_cat) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[k].name, - MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - setup_88e1514(bb_miiphy_buses[k].name, 0); - } - } - - for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { - i2c_set_bus_num(strider_fans[k].bus); - init_fan_controller(strider_fans[k].addr); - } - - return 0; -} - -/* - * provide access to fpga gpios (for I2C bitbang) - * (these may look all too simple but make iocon.h much more readable) - */ -void fpga_gpio_set(uint bus, int pin) -{ - FPGA_SET_REG(bus, gpio.set, pin); -} - -void fpga_gpio_clear(uint bus, int pin) -{ - FPGA_SET_REG(bus, gpio.clear, pin); -} - -int fpga_gpio_get(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus, gpio.read, &val); - - return val & pin; -} - -#ifdef CONFIG_STRIDER_CON_DP -void fpga_control_set(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus, control, &val); - FPGA_SET_REG(bus, control, val | pin); -} - -void fpga_control_clear(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus, control, &val); - FPGA_SET_REG(bus, control, val & ~pin); -} -#endif - -void mpc8308_init(void) -{ - pca9698_direction_output(0x20, 26, 1); -} - -void mpc8308_set_fpga_reset(uint state) -{ - pca9698_set_value(0x20, 26, state ? 0 : 1); -} - -void mpc8308_setup_hw(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * set "startup-finished"-gpios - */ - setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); - setbits_gpio0_out(BIT(31 - 12)); -} - -int mpc8308_get_fpga_done(uint fpga) -{ - return pca9698_get_value(0x20, 20); -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - - /* Enable cache snooping in eSDHC system configuration register */ - out_be32(&sysconf->sdhccr, 0x02000000); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *pcie_reg[] = { pcie_regions_0 }; - - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(1, pcie_reg); -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif - -/* - * FPGA MII bitbang implementation - */ - -struct fpga_mii { - uint fpga; - int mdio; -} fpga_mii[] = { - { 0, 1}, - { 1, 1}, - { 2, 1}, - { 3, 1}, -}; - -static int mii_dummy_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int mii_mdio_active(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (fpga_mii->mdio) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - return 0; -} - -static int mii_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - - return 0; -} - -static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - fpga_mii->mdio = v; - - return 0; -} - -static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - u16 gpio; - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); - - *v = ((gpio & GPIO_MDIO) != 0); - - return 0; -} - -static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); - - return 0; -} - -static int mii_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "board0", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[0], - }, - { - .name = "board1", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[1], - }, - { - .name = "board2", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[2], - }, - { - .name = "board3", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[3], - }, -}; - -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig deleted file mode 100644 index f5154271d1..0000000000 --- a/board/gdsys/p1022/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -config GDSYS_LEGACY_DRIVERS - bool - help - Enable the gdsys legacy drivers under board/gdsys/common. If this - option is not set, all relevant DM drivers must be configured for the - device in question. - -if TARGET_CONTROLCENTERD - -config SYS_BOARD - default "p1022" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "controlcenterd" - -config GDSYS_LEGACY_DRIVERS - default y - -endif diff --git a/board/gdsys/p1022/MAINTAINERS b/board/gdsys/p1022/MAINTAINERS deleted file mode 100644 index 99f1200c09..0000000000 --- a/board/gdsys/p1022/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -P1022 BOARD -M: Dirk Eibach <dirk.eibach@gdsys.cc> -S: Maintained -F: board/gdsys/p1022/ -F: include/configs/controlcenterd.h -F: configs/controlcenterd_36BIT_SDCARD_defconfig -F: configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig -F: configs/controlcenterd_TRAILBLAZER_defconfig -F: configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig diff --git a/board/gdsys/p1022/Makefile b/board/gdsys/p1022/Makefile deleted file mode 100644 index 83a008d198..0000000000 --- a/board/gdsys/p1022/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2010 Freescale Semiconductor, Inc. - -obj-y += law.o -obj-y += ddr.o -obj-y += tlb.o -obj-y += sdhc_boot.o -obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o -obj-$(CONFIG_FSL_DIU_FB) += diu.o diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c deleted file mode 100644 index 87b346aa9c..0000000000 --- a/board/gdsys/p1022/controlcenterd-id.c +++ /dev/null @@ -1,1244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc - */ - -/* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */ - -#ifdef CCDM_ID_DEBUG -#define DEBUG -#endif - -#include <common.h> -#include <bootstage.h> -#include <command.h> -#include <dm.h> -#include <env.h> -#include <hang.h> -#include <log.h> -#include <malloc.h> -#include <fs.h> -#include <i2c.h> -#include <mmc.h> -#include <tpm-v1.h> -#include <linux/delay.h> -#include <u-boot/crc.h> -#include <u-boot/sha1.h> -#include <asm/byteorder.h> -#include <asm/unaligned.h> -#include <pca9698.h> - -#undef CCDM_FIRST_STAGE -#undef CCDM_SECOND_STAGE -#undef CCDM_AUTO_FIRST_STAGE - -#ifdef CONFIG_DEVELOP -#define CCDM_DEVELOP -#endif - -#ifdef CONFIG_TRAILBLAZER -#define CCDM_FIRST_STAGE -#undef CCDM_SECOND_STAGE -#else -#undef CCDM_FIRST_STAGE -#define CCDM_SECOND_STAGE -#endif - -#if defined(CCDM_DEVELOP) && defined(CCDM_SECOND_STAGE) && \ - !defined(CCCM_FIRST_STAGE) -#define CCDM_AUTO_FIRST_STAGE -#endif - -/* CCDM specific contants */ -enum { - /* NV indices */ - NV_COMMON_DATA_INDEX = 0x40000001, - /* magics for key blob chains */ - MAGIC_KEY_PROGRAM = 0x68726500, - MAGIC_HMAC = 0x68616300, - MAGIC_END_OF_CHAIN = 0x00000000, - /* sizes */ - NV_COMMON_DATA_MIN_SIZE = 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t), -}; - -/* other constants */ -enum { - ESDHC_BOOT_IMAGE_SIG_OFS = 0x40, - ESDHC_BOOT_IMAGE_SIZE_OFS = 0x48, - ESDHC_BOOT_IMAGE_ADDR_OFS = 0x50, - ESDHC_BOOT_IMAGE_TARGET_OFS = 0x58, - ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60, -}; - -enum { - I2C_SOC_0 = 0, - I2C_SOC_1 = 1, -}; - -struct key_program { - uint32_t magic; - uint32_t code_crc; - uint32_t code_size; - uint8_t code[]; -}; - -struct h_reg { - bool valid; - uint8_t digest[20]; -}; - - -enum access_mode { - HREG_NONE = 0, - HREG_RD = 1, - HREG_WR = 2, - HREG_RDWR = 3, -}; - -/* register constants */ -enum { - FIX_HREG_DEVICE_ID_HASH = 0, - FIX_HREG_SELF_HASH = 1, - FIX_HREG_STAGE2_HASH = 2, - FIX_HREG_VENDOR = 3, - COUNT_FIX_HREGS -}; - - -/* hre opcodes */ -enum { - /* opcodes w/o data */ - HRE_NOP = 0x00, - HRE_SYNC = HRE_NOP, - HRE_CHECK0 = 0x01, - /* opcodes w/o data, w/ sync dst */ - /* opcodes w/ data */ - HRE_LOAD = 0x81, - /* opcodes w/data, w/sync dst */ - HRE_XOR = 0xC1, - HRE_AND = 0xC2, - HRE_OR = 0xC3, - HRE_EXTEND = 0xC4, - HRE_LOADKEY = 0xC5, -}; - -/* hre errors */ -enum { - HRE_E_OK = 0, - HRE_E_TPM_FAILURE, - HRE_E_INVALID_HREG, -}; - -static uint64_t device_id; -static uint64_t device_cl; -static uint64_t device_type; - -static uint32_t platform_key_handle; - -static void(*bl2_entry)(void); - -static struct h_reg pcr_hregs[24]; -static struct h_reg fix_hregs[COUNT_FIX_HREGS]; -static struct h_reg var_hregs[8]; -static uint32_t hre_tpm_err; -static int hre_err = HRE_E_OK; - -#define IS_PCR_HREG(spec) ((spec) & 0x20) -#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08) -#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10) -#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7)) - -static int get_tpm(struct udevice **devp) -{ - int rc; - - rc = uclass_first_device_err(UCLASS_TPM, devp); - if (rc) { - printf("Could not find TPM (ret=%d)\n", rc); - return CMD_RET_FAILURE; - } - - return 0; -} - -static const uint8_t vendor[] = "Guntermann & Drunck"; - -/** - * @brief read a bunch of data from MMC into memory. - * - * @param mmc pointer to the mmc structure to use. - * @param src offset where the data starts on MMC/SD device (in bytes). - * @param dst pointer to the location where the read data should be stored. - * @param size number of bytes to read from the MMC/SD device. - * @return number of bytes read or -1 on error. - */ -static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) -{ - int result = 0; - u32 blk_len, ofs; - ulong block_no, n, cnt; - u8 *tmp_buf = NULL; - - if (size <= 0) - goto end; - - blk_len = mmc->read_bl_len; - tmp_buf = malloc(blk_len); - if (!tmp_buf) - goto failure; - block_no = src / blk_len; - ofs = src % blk_len; - - if (ofs) { - n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, - tmp_buf); - if (!n) - goto failure; - result = min(size, (int)(blk_len - ofs)); - memcpy(dst, tmp_buf + ofs, result); - dst += result; - size -= result; - } - cnt = size / blk_len; - if (cnt) { - n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt, - dst); - if (n != cnt) - goto failure; - size -= cnt * blk_len; - result += cnt * blk_len; - dst += cnt * blk_len; - block_no += cnt; - } - if (size) { - n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, - tmp_buf); - if (!n) - goto failure; - memcpy(dst, tmp_buf, size); - result += size; - } - goto end; -failure: - result = -1; -end: - if (tmp_buf) - free(tmp_buf); - return result; -} - -/** - * @brief returns a location where the 2nd stage bootloader can be(/ is) placed. - * - * @return pointer to the location for/of the 2nd stage bootloader - */ -static u8 *get_2nd_stage_bl_location(ulong target_addr) -{ - ulong addr; -#ifdef CCDM_SECOND_STAGE - addr = env_get_ulong("loadaddr", 16, CONFIG_LOADADDR); -#else - addr = target_addr; -#endif - return (u8 *)(addr); -} - - -#ifdef CCDM_SECOND_STAGE -/** - * @brief returns a location where the image can be(/ is) placed. - * - * @return pointer to the location for/of the image - */ -static u8 *get_image_location(void) -{ - ulong addr; - /* TODO use other area? */ - addr = env_get_ulong("loadaddr", 16, CONFIG_LOADADDR); - return (u8 *)(addr); -} -#endif - -/** - * @brief get the size of a given (TPM) NV area - * @param index NV index of the area to get size for - * @param size pointer to the size - * @return 0 on success, != 0 on error - */ -static int get_tpm_nv_size(struct udevice *tpm, uint32_t index, uint32_t *size) -{ - uint32_t err; - uint8_t info[72]; - uint8_t *ptr; - uint16_t v16; - - err = tpm1_get_capability(tpm, TPM_CAP_NV_INDEX, index, info, - sizeof(info)); - if (err) { - printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n", - index, err); - return 1; - } - - /* skip tag and nvIndex */ - ptr = info + 6; - /* skip 2 pcr info fields */ - v16 = get_unaligned_be16(ptr); - ptr += 2 + v16 + 1 + 20; - v16 = get_unaligned_be16(ptr); - ptr += 2 + v16 + 1 + 20; - /* skip permission and flags */ - ptr += 6 + 3; - - *size = get_unaligned_be32(ptr); - return 0; -} - -/** - * @brief search for a key by usage auth and pub key hash. - * @param auth usage auth of the key to search for - * @param pubkey_digest (SHA1) hash of the pub key structure of the key - * @param[out] handle the handle of the key iff found - * @return 0 if key was found in TPM; != 0 if not. - */ -static int find_key(struct udevice *tpm, const uint8_t auth[20], - const uint8_t pubkey_digest[20], uint32_t *handle) -{ - uint16_t key_count; - uint32_t key_handles[10]; - uint8_t buf[288]; - uint8_t *ptr; - uint32_t err; - uint8_t digest[20]; - size_t buf_len; - unsigned int i; - - /* fetch list of already loaded keys in the TPM */ - err = tpm1_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf, - sizeof(buf)); - if (err) - return -1; - key_count = get_unaligned_be16(buf); - ptr = buf + 2; - for (i = 0; i < key_count; ++i, ptr += 4) - key_handles[i] = get_unaligned_be32(ptr); - - /* now search a(/ the) key which we can access with the given auth */ - for (i = 0; i < key_count; ++i) { - buf_len = sizeof(buf); - err = tpm1_get_pub_key_oiap(tpm, key_handles[i], auth, buf, - &buf_len); - if (err && err != TPM_AUTHFAIL) - return -1; - if (err) - continue; - sha1_csum(buf, buf_len, digest); - if (!memcmp(digest, pubkey_digest, 20)) { - *handle = key_handles[i]; - return 0; - } - } - return 1; -} - -/** - * @brief read CCDM common data from TPM NV - * @return 0 if CCDM common data was found and read, !=0 if something failed. - */ -static int read_common_data(struct udevice *tpm) -{ - uint32_t size; - uint32_t err; - uint8_t buf[256]; - sha1_context ctx; - - if (get_tpm_nv_size(tpm, NV_COMMON_DATA_INDEX, &size) || - size < NV_COMMON_DATA_MIN_SIZE) - return 1; - err = tpm1_nv_read_value(tpm, NV_COMMON_DATA_INDEX, buf, - min(sizeof(buf), size)); - if (err) { - printf("tpm_nv_read_value() failed: %u\n", err); - return 1; - } - - device_id = get_unaligned_be64(buf); - device_cl = get_unaligned_be64(buf + 8); - device_type = get_unaligned_be64(buf + 16); - - sha1_starts(&ctx); - sha1_update(&ctx, buf, 24); - sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest); - fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true; - - platform_key_handle = get_unaligned_be32(buf + 24); - - return 0; -} - -/** - * @brief compute hash of bootloader itself. - * @param[out] dst hash register where the hash should be stored - * @return 0 on success, != 0 on failure. - * - * @note MUST be called at a time where the boot loader is accessible at the - * configured location (; so take care when code is reallocated). - */ -static int compute_self_hash(struct h_reg *dst) -{ - sha1_csum((const uint8_t *)CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_LEN, dst->digest); - dst->valid = true; - return 0; -} - -int ccdm_compute_self_hash(void) -{ - if (!fix_hregs[FIX_HREG_SELF_HASH].valid) - compute_self_hash(&fix_hregs[FIX_HREG_SELF_HASH]); - return 0; -} - -/** - * @brief compute the hash of the 2nd stage boot loader (on SD card) - * @param[out] dst hash register to store the computed hash - * @return 0 on success, != 0 on failure - * - * Determines the size and location of the 2nd stage boot loader on SD card, - * loads the 2nd stage boot loader and computes the (SHA1) hash value. - * Within the 1st stage boot loader, the 2nd stage boot loader is loaded at - * the desired memory location and the variable @a bl2_entry is set. - * - * @note This sets the variable @a bl2_entry to the entry point when the - * 2nd stage boot loader is loaded at its configured memory location. - */ -static int compute_second_stage_hash(struct h_reg *dst) -{ - int result = 0; - u32 code_len, code_offset, target_addr, exec_entry; - struct mmc *mmc; - u8 *load_addr = NULL; - u8 buf[128]; - - mmc = find_mmc_device(0); - if (!mmc) - goto failure; - mmc_init(mmc); - - if (ccdm_mmc_read(mmc, 0, buf, sizeof(buf)) < 0) - goto failure; - - code_offset = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ADDR_OFS); - code_len = *(u32 *)(buf + ESDHC_BOOT_IMAGE_SIZE_OFS); - target_addr = *(u32 *)(buf + ESDHC_BOOT_IMAGE_TARGET_OFS); - exec_entry = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ENTRY_OFS); - - load_addr = get_2nd_stage_bl_location(target_addr); - if (load_addr == (u8 *)target_addr) - bl2_entry = (void(*)(void))exec_entry; - - if (ccdm_mmc_read(mmc, code_offset, load_addr, code_len) < 0) - goto failure; - - sha1_csum(load_addr, code_len, dst->digest); - dst->valid = true; - - goto end; -failure: - result = 1; - bl2_entry = NULL; -end: - return result; -} - -/** - * @brief get pointer to hash register by specification - * @param spec specification of a hash register - * @return pointer to hash register or NULL if @a spec does not qualify a - * valid hash register; NULL else. - */ -static struct h_reg *get_hreg(uint8_t spec) -{ - uint8_t idx; - - idx = HREG_IDX(spec); - if (IS_FIX_HREG(spec)) { - if (idx < ARRAY_SIZE(fix_hregs)) - return fix_hregs + idx; - hre_err = HRE_E_INVALID_HREG; - } else if (IS_PCR_HREG(spec)) { - if (idx < ARRAY_SIZE(pcr_hregs)) - return pcr_hregs + idx; - hre_err = HRE_E_INVALID_HREG; - } else if (IS_VAR_HREG(spec)) { - if (idx < ARRAY_SIZE(var_hregs)) - return var_hregs + idx; - hre_err = HRE_E_INVALID_HREG; - } - return NULL; -} - -/** - * @brief get pointer of a hash register by specification and usage. - * @param spec specification of a hash register - * @param mode access mode (read or write or read/write) - * @return pointer to hash register if found and valid; NULL else. - * - * This func uses @a get_reg() to determine the hash register for a given spec. - * If a register is found it is validated according to the desired access mode. - * The value of automatic registers (PCR register and fixed registers) is - * loaded or computed on read access. - */ -static struct h_reg *access_hreg(struct udevice *tpm, uint8_t spec, - enum access_mode mode) -{ - struct h_reg *result; - - result = get_hreg(spec); - if (!result) - return NULL; - - if (mode & HREG_WR) { - if (IS_FIX_HREG(spec)) { - hre_err = HRE_E_INVALID_HREG; - return NULL; - } - } - if (mode & HREG_RD) { - if (!result->valid) { - if (IS_PCR_HREG(spec)) { - hre_tpm_err = tpm1_pcr_read(tpm, HREG_IDX(spec), - result->digest, 20); - result->valid = (hre_tpm_err == TPM_SUCCESS); - } else if (IS_FIX_HREG(spec)) { - switch (HREG_IDX(spec)) { - case FIX_HREG_DEVICE_ID_HASH: - read_common_data(tpm); - break; - case FIX_HREG_SELF_HASH: - ccdm_compute_self_hash(); - break; - case FIX_HREG_STAGE2_HASH: - compute_second_stage_hash(result); - break; - case FIX_HREG_VENDOR: - memcpy(result->digest, vendor, 20); - result->valid = true; - break; - } - } else { - result->valid = true; - } - } - if (!result->valid) { - hre_err = HRE_E_INVALID_HREG; - return NULL; - } - } - - return result; -} - -static void *compute_and(void *_dst, const void *_src, size_t n) -{ - uint8_t *dst = _dst; - const uint8_t *src = _src; - size_t i; - - for (i = n; i-- > 0; ) - *dst++ &= *src++; - - return _dst; -} - -static void *compute_or(void *_dst, const void *_src, size_t n) -{ - uint8_t *dst = _dst; - const uint8_t *src = _src; - size_t i; - - for (i = n; i-- > 0; ) - *dst++ |= *src++; - - return _dst; -} - -static void *compute_xor(void *_dst, const void *_src, size_t n) -{ - uint8_t *dst = _dst; - const uint8_t *src = _src; - size_t i; - - for (i = n; i-- > 0; ) - *dst++ ^= *src++; - - return _dst; -} - -static void *compute_extend(void *_dst, const void *_src, size_t n) -{ - uint8_t digest[20]; - sha1_context ctx; - - sha1_starts(&ctx); - sha1_update(&ctx, _dst, n); - sha1_update(&ctx, _src, n); - sha1_finish(&ctx, digest); - memcpy(_dst, digest, min(n, sizeof(digest))); - - return _dst; -} - -static int hre_op_loadkey(struct udevice *tpm, struct h_reg *src_reg, - struct h_reg *dst_reg, const void *key, - size_t key_size) -{ - uint32_t parent_handle; - uint32_t key_handle; - - if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid) - return -1; - if (find_key(tpm, src_reg->digest, dst_reg->digest, &parent_handle)) - return -1; - hre_tpm_err = tpm1_load_key2_oiap(tpm, parent_handle, key, key_size, - src_reg->digest, &key_handle); - if (hre_tpm_err) { - hre_err = HRE_E_TPM_FAILURE; - return -1; - } - /* TODO remember key handle somehow? */ - - return 0; -} - -/** - * @brief executes the next opcode on the hash register engine. - * @param[in,out] ip pointer to the opcode (instruction pointer) - * @param[in,out] code_size (remaining) size of the code - * @return new instruction pointer on success, NULL on error. - */ -static const uint8_t *hre_execute_op(struct udevice *tpm, const uint8_t **ip, - size_t *code_size) -{ - bool dst_modified = false; - uint32_t ins; - uint8_t opcode; - uint8_t src_spec; - uint8_t dst_spec; - uint16_t data_size; - struct h_reg *src_reg, *dst_reg; - uint8_t buf[20]; - const uint8_t *src_buf, *data; - uint8_t *ptr; - int i; - void * (*bin_func)(void *, const void *, size_t); - - if (*code_size < 4) - return NULL; - - ins = get_unaligned_be32(*ip); - opcode = **ip; - data = *ip + 4; - src_spec = (ins >> 18) & 0x3f; - dst_spec = (ins >> 12) & 0x3f; - data_size = (ins & 0x7ff); - - debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins, - opcode, src_spec, dst_spec, data_size); - - if ((opcode & 0x80) && (data_size + 4) > *code_size) - return NULL; - - src_reg = access_hreg(tpm, src_spec, HREG_RD); - if (hre_err || hre_tpm_err) - return NULL; - dst_reg = access_hreg(tpm, dst_spec, - (opcode & 0x40) ? HREG_RDWR : HREG_WR); - if (hre_err || hre_tpm_err) - return NULL; - - switch (opcode) { - case HRE_NOP: - goto end; - case HRE_CHECK0: - if (src_reg) { - for (i = 0; i < 20; ++i) { - if (src_reg->digest[i]) - return NULL; - } - } - break; - case HRE_LOAD: - bin_func = memcpy; - goto do_bin_func; - case HRE_XOR: - bin_func = compute_xor; - goto do_bin_func; - case HRE_AND: - bin_func = compute_and; - goto do_bin_func; - case HRE_OR: - bin_func = compute_or; - goto do_bin_func; - case HRE_EXTEND: - bin_func = compute_extend; -do_bin_func: - if (!dst_reg) - return NULL; - if (src_reg) { - src_buf = src_reg->digest; - } else { - if (!data_size) { - memset(buf, 0, 20); - src_buf = buf; - } else if (data_size == 1) { - memset(buf, *data, 20); - src_buf = buf; - } else if (data_size >= 20) { - src_buf = data; - } else { - src_buf = buf; - for (ptr = (uint8_t *)src_buf, i = 20; i > 0; - i -= data_size, ptr += data_size) - memcpy(ptr, data, - min_t(size_t, i, data_size)); - } - } - bin_func(dst_reg->digest, src_buf, 20); - dst_reg->valid = true; - dst_modified = true; - break; - case HRE_LOADKEY: - if (hre_op_loadkey(tpm, src_reg, dst_reg, data, data_size)) - return NULL; - break; - default: - return NULL; - } - - if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) { - hre_tpm_err = tpm1_extend(tpm, HREG_IDX(dst_spec), - dst_reg->digest, dst_reg->digest); - if (hre_tpm_err) { - hre_err = HRE_E_TPM_FAILURE; - return NULL; - } - } -end: - *ip += 4; - *code_size -= 4; - if (opcode & 0x80) { - *ip += data_size; - *code_size -= data_size; - } - - return *ip; -} - -/** - * @brief runs a program on the hash register engine. - * @param code pointer to the (HRE) code. - * @param code_size size of the code (in bytes). - * @return 0 on success, != 0 on failure. - */ -static int hre_run_program(struct udevice *tpm, const uint8_t *code, - size_t code_size) -{ - size_t code_left; - const uint8_t *ip = code; - - code_left = code_size; - hre_tpm_err = 0; - hre_err = HRE_E_OK; - while (code_left > 0) - if (!hre_execute_op(tpm, &ip, &code_left)) - return -1; - - return hre_err; -} - -static int check_hmac(struct key_program *hmac, - const uint8_t *data, size_t data_size) -{ - uint8_t key[20], computed_hmac[20]; - uint32_t type; - - type = get_unaligned_be32(hmac->code); - if (type != 0) - return 1; - memset(key, 0, sizeof(key)); - compute_extend(key, pcr_hregs[1].digest, 20); - compute_extend(key, pcr_hregs[2].digest, 20); - compute_extend(key, pcr_hregs[3].digest, 20); - compute_extend(key, pcr_hregs[4].digest, 20); - - sha1_hmac(key, sizeof(key), data, data_size, computed_hmac); - - return memcmp(computed_hmac, hmac->code + 4, 20); -} - -static int verify_program(struct key_program *prg) -{ - uint32_t crc; - crc = crc32(0, prg->code, prg->code_size); - - if (crc != prg->code_crc) { - printf("HRC crc mismatch: %08x != %08x\n", - crc, prg->code_crc); - return 1; - } - return 0; -} - -#if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE) -static struct key_program *load_sd_key_program(void) -{ - u32 code_len, code_offset; - struct mmc *mmc; - u8 buf[128]; - struct key_program *result = NULL, *hmac = NULL; - struct key_program header; - - mmc = find_mmc_device(0); - if (!mmc) - return NULL; - mmc_init(mmc); - - if (ccdm_mmc_read(mmc, 0, buf, sizeof(buf)) <= 0) - goto failure; - - code_offset = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ADDR_OFS); - code_len = *(u32 *)(buf + ESDHC_BOOT_IMAGE_SIZE_OFS); - - code_offset += code_len; - /* TODO: the following needs to be the size of the 2nd stage env */ - code_offset += CONFIG_ENV_SIZE; - - if (ccdm_mmc_read(mmc, code_offset, buf, 4*3) < 0) - goto failure; - - header.magic = get_unaligned_be32(buf); - header.code_crc = get_unaligned_be32(buf + 4); - header.code_size = get_unaligned_be32(buf + 8); - - if (header.magic != MAGIC_KEY_PROGRAM) - goto failure; - - result = malloc(sizeof(struct key_program) + header.code_size); - if (!result) - goto failure; - *result = header; - - printf("load key program chunk from SD card (%u bytes) ", - header.code_size); - code_offset += 12; - if (ccdm_mmc_read(mmc, code_offset, result->code, header.code_size) - < 0) - goto failure; - code_offset += header.code_size; - puts("\n"); - - if (verify_program(result)) - goto failure; - - if (ccdm_mmc_read(mmc, code_offset, buf, 4*3) < 0) - goto failure; - - header.magic = get_unaligned_be32(buf); - header.code_crc = get_unaligned_be32(buf + 4); - header.code_size = get_unaligned_be32(buf + 8); - - if (header.magic == MAGIC_HMAC) { - puts("check integrity\n"); - hmac = malloc(sizeof(struct key_program) + header.code_size); - if (!hmac) - goto failure; - *hmac = header; - code_offset += 12; - if (ccdm_mmc_read(mmc, code_offset, hmac->code, - hmac->code_size) < 0) - goto failure; - if (verify_program(hmac)) - goto failure; - if (check_hmac(hmac, result->code, result->code_size)) { - puts("key program integrity could not be verified\n"); - goto failure; - } - puts("key program verified\n"); - } - - goto end; -failure: - if (result) - free(result); - result = NULL; -end: - if (hmac) - free(hmac); - - return result; -} -#endif - -#ifdef CCDM_SECOND_STAGE -/** - * @brief load a key program from file system. - * @param ifname interface of the file system - * @param dev_part_str device part of the file system - * @param fs_type tyep of the file system - * @param path path of the file to load. - * @return the loaded structure or NULL on failure. - */ -static struct key_program *load_key_chunk(const char *ifname, - const char *dev_part_str, int fs_type, - const char *path) -{ - struct key_program *result = NULL; - struct key_program header; - uint32_t crc; - uint8_t buf[12]; - loff_t i; - - if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) - goto failure; - if (fs_read(path, (ulong)buf, 0, 12, &i) < 0) - goto failure; - if (i < 12) - goto failure; - header.magic = get_unaligned_be32(buf); - header.code_crc = get_unaligned_be32(buf + 4); - header.code_size = get_unaligned_be32(buf + 8); - - if (header.magic != MAGIC_HMAC && header.magic != MAGIC_KEY_PROGRAM) - goto failure; - - result = malloc(sizeof(struct key_program) + header.code_size); - if (!result) - goto failure; - if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) - goto failure; - if (fs_read(path, (ulong)result, 0, - sizeof(struct key_program) + header.code_size, &i) < 0) - goto failure; - if (i <= 0) - goto failure; - *result = header; - - crc = crc32(0, result->code, result->code_size); - - if (crc != result->code_crc) { - printf("%s: HRC crc mismatch: %08x != %08x\n", - path, crc, result->code_crc); - goto failure; - } - goto end; -failure: - if (result) { - free(result); - result = NULL; - } -end: - return result; -} -#endif - -#if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE) -static const uint8_t prg_stage1_prepare[] = { - 0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */ - 0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */ - 0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */ - 0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */ - 0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */ - 0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */ - 0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */ - 0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */ - 0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */ - 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */ -}; - -static int first_stage_actions(struct udevice *tpm) -{ - int result = 0; - struct key_program *sd_prg = NULL; - - puts("CCDM S1: start actions\n"); -#ifndef CCDM_SECOND_STAGE - if (tpm1_continue_self_test(tpm)) - goto failure; -#else - tpm1_continue_self_test(tpm); -#endif - mdelay(37); - - if (hre_run_program(tpm, prg_stage1_prepare, - sizeof(prg_stage1_prepare))) - goto failure; - - sd_prg = load_sd_key_program(); - if (sd_prg) { - if (hre_run_program(tpm, sd_prg->code, sd_prg->code_size)) - goto failure; - puts("SD code run successfully\n"); - } else { - puts("no key program found on SD\n"); - goto failure; - } - goto end; -failure: - result = 1; -end: - if (sd_prg) - free(sd_prg); - printf("CCDM S1: actions done (%d)\n", result); - return result; -} -#endif - -#ifdef CCDM_FIRST_STAGE -static int first_stage_init(void) -{ - struct udevice *tpm; - int ret; - - puts("CCDM S1\n"); - ret = get_tpm(&tpm); - if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR)) - return 1; - ret = first_stage_actions(tpm); -#ifndef CCDM_SECOND_STAGE - if (!ret) { - if (bl2_entry) - (*bl2_entry)(); - ret = 1; - } -#endif - return ret; -} -#endif - -#ifdef CCDM_SECOND_STAGE -static const uint8_t prg_stage2_prepare[] = { - 0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */ - 0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */ - 0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */ - 0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */ - 0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */ -}; - -static const uint8_t prg_stage2_success[] = { - 0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */ - 0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */ - 0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */ - 0xe4, 0xd2, 0x81, 0xe0, /* data */ -}; - -static const uint8_t prg_stage_fail[] = { - 0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */ - 0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */ - 0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */ - 0xea, 0xdf, 0x14, 0x4b, /* data */ - 0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */ - 0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */ -}; - -static int second_stage_init(void) -{ - static const char mac_suffix[] = ".mac"; - bool did_first_stage_run = true; - int result = 0; - char *cptr, *mmcdev = NULL; - struct key_program *hmac_blob = NULL; - const char *image_path = "/ccdm.itb"; - char *mac_path = NULL; - ulong image_addr; - loff_t image_size; - struct udevice *tpm; - uint32_t err; - int ret; - - printf("CCDM S2\n"); - ret = get_tpm(&tpm); - if (ret || tpm_init(tpm)) - return 1; - err = tpm1_startup(tpm, TPM_ST_CLEAR); - if (err != TPM_INVALID_POSTINIT) - did_first_stage_run = false; - -#ifdef CCDM_AUTO_FIRST_STAGE - if (!did_first_stage_run && first_stage_actions(tpm)) - goto failure; -#else - if (!did_first_stage_run) - goto failure; -#endif - - if (hre_run_program(tpm, prg_stage2_prepare, - sizeof(prg_stage2_prepare))) - goto failure; - - /* run "prepboot" from env to get "mmcdev" set */ - cptr = env_get("prepboot"); - if (cptr && !run_command(cptr, 0)) - mmcdev = env_get("mmcdev"); - if (!mmcdev) - goto failure; - - cptr = env_get("ramdiskimage"); - if (cptr) - image_path = cptr; - - mac_path = malloc(strlen(image_path) + strlen(mac_suffix) + 1); - if (mac_path == NULL) - goto failure; - strcpy(mac_path, image_path); - strcat(mac_path, mac_suffix); - - /* read image from mmcdev (ccdm.itb) */ - image_addr = (ulong)get_image_location(); - if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT)) - goto failure; - if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0) - goto failure; - if (image_size <= 0) - goto failure; - printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size); - - hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path); - if (!hmac_blob) { - puts("failed to load mac file\n"); - goto failure; - } - if (verify_program(hmac_blob)) { - puts("corrupted mac file\n"); - goto failure; - } - if (check_hmac(hmac_blob, (u8 *)image_addr, image_size)) { - puts("image integrity could not be verified\n"); - goto failure; - } - puts("CCDM image OK\n"); - - hre_run_program(tpm, prg_stage2_success, sizeof(prg_stage2_success)); - - goto end; -failure: - result = 1; - hre_run_program(tpm, prg_stage_fail, sizeof(prg_stage_fail)); -end: - if (hmac_blob) - free(hmac_blob); - if (mac_path) - free(mac_path); - - return result; -} -#endif - -int show_self_hash(void) -{ - struct h_reg *hash_ptr; -#ifdef CCDM_SECOND_STAGE - struct h_reg hash; - - hash_ptr = &hash; - if (compute_self_hash(hash_ptr)) - return 1; -#else - hash_ptr = &fix_hregs[FIX_HREG_SELF_HASH]; -#endif - puts("self hash: "); - if (hash_ptr && hash_ptr->valid) - print_buffer(0, hash_ptr->digest, 1, 20, 20); - else - puts("INVALID\n"); - - return 0; -} - -/** - * @brief let the system hang. - * - * Called on error. - * Will stop the boot process; display a message and signal the error condition - * by blinking the "status" and the "finder" LED of the controller board. - * - * @note the develop version runs the blink cycle 2 times and then returns. - * The release version never returns. - */ -static void ccdm_hang(void) -{ - static const u64 f0 = 0x0ba3bb8ba2e880; /* blink code "finder" LED */ - static const u64 s0 = 0x00f0f0f0f0f0f0; /* blink code "status" LED */ - u64 f, s; - int i; -#ifdef CCDM_DEVELOP - int j; -#endif - - I2C_SET_BUS(I2C_SOC_0); - pca9698_direction_output(0x22, 0, 0); /* Finder */ - pca9698_direction_output(0x22, 4, 0); /* Status */ - - puts("### ERROR ### Please RESET the board ###\n"); - bootstage_error(BOOTSTAGE_ID_NEED_RESET); -#ifdef CCDM_DEVELOP - puts("*** ERROR ******** THIS WOULD HANG ******** ERROR ***\n"); - puts("** but we continue since this is a DEVELOP version **\n"); - puts("*** ERROR ******** THIS WOULD HANG ******** ERROR ***\n"); - for (j = 2; j-- > 0;) { - putc('#'); -#else - for (;;) { -#endif - f = f0; - s = s0; - for (i = 54; i-- > 0;) { - pca9698_set_value(0x22, 0, !(f & 1)); - pca9698_set_value(0x22, 4, (s & 1)); - f >>= 1; - s >>= 1; - mdelay(120); - } - } - puts("\ncontinue...\n"); -} - -int startup_ccdm_id_module(void) -{ - int result = 0; - unsigned int orig_i2c_bus; - - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(I2C_SOC_1); - - /* goto end; */ - -#ifdef CCDM_DEVELOP - show_self_hash(); -#endif -#ifdef CCDM_FIRST_STAGE - result = first_stage_init(); - if (result) { - puts("1st stage init failed\n"); - goto failure; - } -#endif -#ifdef CCDM_SECOND_STAGE - result = second_stage_init(); - if (result) { - puts("2nd stage init failed\n"); - goto failure; - } -#endif - - goto end; -failure: - result = 1; -end: - i2c_set_bus_num(orig_i2c_bus); - if (result) - ccdm_hang(); - - return result; -} diff --git a/board/gdsys/p1022/controlcenterd-id.h b/board/gdsys/p1022/controlcenterd-id.h deleted file mode 100644 index 289a4b14b6..0000000000 --- a/board/gdsys/p1022/controlcenterd-id.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc - */ - -#ifndef __CONTROLCENTER_ID_H -#define __CONTROLCENTER_ID_H - -int ccdm_compute_self_hash(void); -int startup_ccdm_id_module(void); - -int show_self_hash(void); - -#endif /* __CONTROLCENTER_ID_H */ diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c deleted file mode 100644 index d31cba3d06..0000000000 --- a/board/gdsys/p1022/controlcenterd.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2013 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <image.h> -#include <init.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <asm/fsl_law.h> -#include <netdev.h> -#include <i2c.h> -#include <pca9698.h> -#include <watchdog.h> -#include "../common/dp501.h" -#include "controlcenterd-id.h" - -enum { - HWVER_100 = 0, - HWVER_110 = 1, - HWVER_120 = 2, -}; - -struct ihs_fpga { - u32 reflection_low; /* 0x0000 */ - u32 versions; /* 0x0004 */ - u32 fpga_version; /* 0x0008 */ - u32 fpga_features; /* 0x000c */ - u32 reserved[4]; /* 0x0010 */ - u32 control; /* 0x0020 */ -}; - -#ifndef CONFIG_TRAILBLAZER -static struct pci_device_id hydra_supported[] = { - { 0x6d5e, 0xcdc0 }, - {} -}; - -static void hydra_initialize(void); -#endif - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); - - /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */ - clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, 0x00001000); - - /* Set pmuxcr to enable GPIO 3_11-3_13 */ - setbits_be32(&gur->pmuxcr, 0x00000010); - - /* Set pmuxcr to enable GPIO 2_31,3_9+10 */ - setbits_be32(&gur->pmuxcr, 0x00000020); - - /* Set pmuxcr to enable GPIO 2_28-2_30 */ - setbits_be32(&gur->pmuxcr, 0x000000c0); - - /* Set pmuxcr to enable GPIO 3_20-3_22 */ - setbits_be32(&gur->pmuxcr2, 0x03000000); - - /* Set pmuxcr to enable IRQ0-2 */ - clrbits_be32(&gur->pmuxcr, 0x00000300); - - /* Set pmuxcr to disable IRQ3-11 */ - setbits_be32(&gur->pmuxcr, 0x000000F0); - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - - /* Set the pin muxing to enable ETSEC2. */ - clrbits_be32(&gur->pmuxcr2, 0x001F8000); - -#ifdef CONFIG_TRAILBLAZER - /* - * GPIO3_10 SPERRTRIGGER - */ - setbits_be32(&pgpio->gpdir, 0x00200000); - clrbits_be32(&pgpio->gpdat, 0x00200000); - udelay(100); - setbits_be32(&pgpio->gpdat, 0x00200000); - udelay(100); - clrbits_be32(&pgpio->gpdat, 0x00200000); -#endif - - /* - * GPIO3_11 CPU-TO-FPGA-RESET# - */ - setbits_be32(&pgpio->gpdir, 0x00100000); - clrbits_be32(&pgpio->gpdat, 0x00100000); - - /* - * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER# - */ - setbits_be32(&pgpio->gpdir, 0x00000400); - - return 0; -} - -int checkboard(void) -{ - printf("Board: ControlCenter DIGITAL\n"); - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -/* - * A list of PCI and SATA slots - */ -enum slot_id { - SLOT_PCIE1 = 1, - SLOT_PCIE2, - SLOT_PCIE3, - SLOT_PCIE4, - SLOT_PCIE5, - SLOT_SATA1, - SLOT_SATA2 -}; - -/* - * This array maps the slot identifiers to their names on the P1022DS board. - */ -static const char * const slot_names[] = { - [SLOT_PCIE1] = "Slot 1", - [SLOT_PCIE2] = "Slot 2", - [SLOT_PCIE3] = "Slot 3", - [SLOT_PCIE4] = "Slot 4", - [SLOT_PCIE5] = "Mini-PCIe", - [SLOT_SATA1] = "SATA 1", - [SLOT_SATA2] = "SATA 2", -}; - -/* - * This array maps a given SERDES configuration and SERDES device to the PCI or - * SATA slot that it connects to. This mapping is hard-coded in the FPGA. - */ -static u8 serdes_dev_slot[][SATA2 + 1] = { - [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, - [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, - [PCIE2] = SLOT_PCIE5 }, - [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, - [PCIE2] = SLOT_PCIE3, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, - [PCIE2] = SLOT_PCIE3 }, - [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, - [PCIE2] = SLOT_PCIE3, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x1c] = { [PCIE1] = SLOT_PCIE1, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, - [0x1f] = { [PCIE1] = SLOT_PCIE1 }, -}; - - -/* - * Returns the name of the slot to which the PCIe or SATA controller is - * connected - */ -const char *board_serdes_name(enum srds_prtcl device) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 pordevsr = in_be32(&gur->pordevsr); - unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - enum slot_id slot = serdes_dev_slot[srds_cfg][device]; - const char *name = slot_names[slot]; - - if (name) - return name; - else - return "Nothing"; -} - -void hw_watchdog_reset(void) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); - - clrbits_be32(&pgpio->gpdat, 0x00000400); - setbits_be32(&pgpio->gpdat, 0x00000400); -} - -#ifdef CONFIG_TRAILBLAZER -int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - return run_command(env_get("bootcmd"), flag); -} - -int board_early_init_r(void) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); - - /* - * GPIO3_12 PPC_SYSTEMREADY# - */ - setbits_be32(&pgpio->gpdir, 0x00080000); - setbits_be32(&pgpio->gpodr, 0x00080000); - clrbits_be32(&pgpio->gpdat, 0x00080000); - - return ccdm_compute_self_hash(); -} - -int last_stage_init(void) -{ - startup_ccdm_id_module(); - return 0; -} - -#else -void pci_init_board(void) -{ - fsl_pcie_init_board(0); - - hydra_initialize(); -} - -int board_early_init_r(void) -{ - unsigned int k = 0; - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); - - /* wait for FPGA configuration to finish */ - while (!pca9698_get_value(0x22, 11) && (k++ < 30)) - udelay(100000); - - if (k > 30) { - puts("FPGA configuration timed out.\n"); - } else { - /* clear FPGA reset */ - udelay(1000); - setbits_be32(&pgpio->gpdat, 0x00100000); - } - - /* give time for PCIe link training */ - udelay(100000); - - /* - * GPIO3_12 PPC_SYSTEMREADY# - */ - setbits_be32(&pgpio->gpdir, 0x00080000); - setbits_be32(&pgpio->gpodr, 0x00080000); - clrbits_be32(&pgpio->gpdat, 0x00080000); - - return 0; -} - -int last_stage_init(void) -{ - /* Turn on Parade DP501 */ - pca9698_direction_output(0x22, 7, 1); - udelay(500000); - - dp501_powerup(0x08); - - startup_ccdm_id_module(); - - return 0; -} - -/* - * Initialize on-board and/or PCI Ethernet devices - * - * Returns: - * <0, error - * 0, no ethernet devices found - * >0, number of ethernet devices initialized - */ -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - unsigned int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif - -static void hydra_initialize(void) -{ - unsigned int i; - pci_dev_t devno; - - /* Find and probe all the matching PCI devices */ - for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) { - u32 val; - struct ihs_fpga *fpga; - u32 versions; - u32 fpga_version; - u32 fpga_features; - - unsigned hardware_version; - unsigned feature_uart_channels; - unsigned feature_sb_channels; - - /* Try to enable I/O accesses and bus-mastering */ - val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config_dword(devno, PCI_COMMAND, val); - - /* Make sure it worked */ - pci_read_config_dword(devno, PCI_COMMAND, &val); - if (!(val & PCI_COMMAND_MEMORY)) { - puts("Can't enable I/O memory\n"); - continue; - } - if (!(val & PCI_COMMAND_MASTER)) { - puts("Can't enable bus-mastering\n"); - continue; - } - - /* read FPGA details */ - fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); - - /* disable sideband clocks */ - writel(1, &fpga->control); - - versions = readl(&fpga->versions); - fpga_version = readl(&fpga->fpga_version); - fpga_features = readl(&fpga->fpga_features); - - hardware_version = versions & 0xf; - feature_uart_channels = (fpga_features >> 6) & 0x1f; - feature_sb_channels = fpga_features & 0x1f; - - printf("FPGA%d: ", i); - - switch (hardware_version) { - case HWVER_100: - printf("HW-Ver 1.00\n"); - break; - - case HWVER_110: - printf("HW-Ver 1.10\n"); - break; - - case HWVER_120: - printf("HW-Ver 1.20\n"); - break; - - default: - printf("HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d uart channel(s)", feature_uart_channels); - printf(" %d sideband channel(s)\n", feature_sb_channels); - } -} -#endif diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c deleted file mode 100644 index eb06d22471..0000000000 --- a/board/gdsys/p1022/ddr.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - */ - -#include <common.h> -#include <i2c.h> -#include <log.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* set odt_rd_cfg and odt_wr_cfg. */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - } - - popts->clk_adjust = 5; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - - /* Per AN4039, enable ZQ calibration. */ - popts->zq_en = 1; -} - -#ifdef CONFIG_SPD_EEPROM -/* - * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses - */ -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) -{ - int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); - - if (ret) { - if (i2c_address == -#ifdef SPD_EEPROM_ADDRESS - SPD_EEPROM_ADDRESS -#elif defined(SPD_EEPROM_ADDRESS1) - SPD_EEPROM_ADDRESS1 -#endif - ) { - printf("DDR: failed to read SPD from address %u\n", - i2c_address); - } else { - debug("DDR: failed to read SPD from address %u\n", - i2c_address); - } - memset(spd, 0, sizeof(generic_spd_eeprom_t)); - } -} -#endif diff --git a/board/gdsys/p1022/diu.c b/board/gdsys/p1022/diu.c deleted file mode 100644 index 9a5d3c11e1..0000000000 --- a/board/gdsys/p1022/diu.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Authors: Timur Tabi <timur@freescale.com> - * - * FSL DIU Framebuffer driver - */ - -#include <common.h> -#include <clock_legacy.h> -#include <command.h> -#include <log.h> -#include <linux/ctype.h> -#include <asm/io.h> -#include <stdio_dev.h> -#include <video_fb.h> -#include <fsl_diu_fb.h> - -#define PMUXCR_ELBCDIU_MASK 0xc0000000 -#define PMUXCR_ELBCDIU_NOR16 0x80000000 -#define PMUXCR_ELBCDIU_DIU 0x40000000 - -/* - * DIU Area Descriptor - * - * Note that we need to byte-swap the value before it's written to the AD - * register. So even though the registers don't look like they're in the same - * bit positions as they are on the MPC8610, the same value is written to the - * AD register on the MPC8610 and on the P1022. - */ -#define AD_BYTE_F 0x10000000 -#define AD_ALPHA_C_SHIFT 25 -#define AD_BLUE_C_SHIFT 23 -#define AD_GREEN_C_SHIFT 21 -#define AD_RED_C_SHIFT 19 -#define AD_PIXEL_S_SHIFT 16 -#define AD_COMP_3_SHIFT 12 -#define AD_COMP_2_SHIFT 8 -#define AD_COMP_1_SHIFT 4 -#define AD_COMP_0_SHIFT 0 - -/* - * Variables used by the DIU/LBC switching code. It's safe to makes these - * global, because the DIU requires DDR, so we'll only run this code after - * relocation. - */ -static u32 pmuxcr; - -void diu_set_pixel_clock(unsigned int pixclock) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - unsigned long speed_ccb, temp; - u32 pixval; - - speed_ccb = get_bus_freq(0); - temp = 1000000000 / pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %u\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; - out_be32(&gur->clkdvdr, temp); /* turn off clock */ - out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 pixel_format; - - pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | - (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | - (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | - (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | - (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); - - printf("DIU: Switching to %ux%u\n", xres, yres); - - /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ - clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); - pmuxcr = in_be32(&gur->pmuxcr); - - return fsl_diu_init(xres, yres, pixel_format, 0); -} diff --git a/board/gdsys/p1022/law.c b/board/gdsys/p1022/law.c deleted file mode 100644 index 5214109943..0000000000 --- a/board/gdsys/p1022/law.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_ELBC_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c deleted file mode 100644 index 6a4a6ef6af..0000000000 --- a/board/gdsys/p1022/sdhc_boot.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mmc.h> -#include <malloc.h> - -/* - * The environment variables are written to just after the u-boot image - * on SDCard, so we must read the MBR to get the start address and code - * length of the u-boot image, then calculate the address of the env. - */ -#define ESDHC_BOOT_IMAGE_SIZE 0x48 -#define ESDHC_BOOT_IMAGE_ADDR 0x50 - -int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) -{ - u8 *tmp_buf; - u32 blklen, code_offset, code_len, n; - - blklen = mmc->read_bl_len; - tmp_buf = malloc(blklen); - if (!tmp_buf) - return 1; - - /* read out the first block, get the config data information */ - n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); - if (!n) { - free(tmp_buf); - return 1; - } - - /* Get the Source Address, from offset 0x50 */ - code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR); - - /* Get the code size from offset 0x48 */ - code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); - - *env_addr = code_offset + code_len; - - free(tmp_buf); - - return 0; -} diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c deleted file mode 100644 index 00139ac5e3..0000000000 --- a/board/gdsys/p1022/tlb.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* *I*G* - eLBC */ - SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_TRAILBLAZER) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), -#else - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), - -#ifdef CONFIG_SYS_RAMBOOT - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 6, BOOKE_PAGESZ_1G, 1), -#endif -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig deleted file mode 100644 index 2a67337293..0000000000 --- a/board/laird/wb45n/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WB45N - -config SYS_BOARD - default "wb45n" - -config SYS_VENDOR - default "laird" - -config SYS_CONFIG_NAME - default "wb45n" - -endif diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS deleted file mode 100644 index 60bb563201..0000000000 --- a/board/laird/wb45n/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WB45N CPU MODULE -M: Ben Whitten <ben.whitten@lairdtech.com> -S: Maintained -F: board/laird/wb45n/ -F: include/configs/wb45n.h -F: configs/wb45n_defconfig diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile deleted file mode 100644 index 2971c6c952..0000000000 --- a/board/laird/wb45n/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += wb45n.o diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c deleted file mode 100644 index 5e1ef8a49a..0000000000 --- a/board/laird/wb45n/wb45n.c +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/at91sam9x5_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <net.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ -static void wb45n_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - csa = readl(&matrix->ebicsa); - /* Enable CS3 */ - csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; - /* NAND flash on D0 */ - csa &= ~AT91_MATRIX_NFD0_ON_D16; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); - - at91_periph_clk_enable(ATMEL_ID_PIOCD); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - /* Disable Flash Write Protect Line */ - at91_set_gpio_output(AT91_PIN_PD10, 1); - - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ -} - -static void wb45n_gpio_hw_init(void) -{ - - /* Configure wifi gpio CHIP_PWD_L */ - at91_set_gpio_output(AT91_PIN_PA28, 0); - - /* Setup USB pins */ - at91_set_gpio_input(AT91_PIN_PB11, 0); - at91_set_gpio_output(AT91_PIN_PB12, 0); - - /* IRQ pin, pullup, deglitch */ - at91_set_gpio_input(AT91_PIN_PB18, 1); - at91_set_gpio_deglitch(AT91_PIN_PB18, 1); -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; - - if (has_emac0()) - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); - - return rc; -} - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - wb45n_gpio_hw_init(); - - wb45n_nand_hw_init(); - - at91_macb_hw_init(); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#if defined(CONFIG_SPL_BUILD) -#include <spl.h> -#include <nand.h> - -void at91_spl_board_init(void) -{ - /* Setup GPIO first */ - wb45n_gpio_hw_init(); - - /* Bring up NAND */ - wb45n_nand_hw_init(); -} - -void matrix_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - csa = readl(&matrix->ebicsa); - /* Pull ups on D0 - D16 */ - csa &= ~AT91_MATRIX_EBI_DBPU_OFF; - csa |= AT91_MATRIX_EBI_DBPD_OFF; - /* Normal drive strength */ - csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; - /* Multi-port off */ - csa &= ~AT91_MATRIX_MP_ON; - writel(csa, &matrix->ebicsa); -} - -#include <asm/arch/atmel_mpddrc.h> -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | - ATMEL_MPDDRC_CR_DQMS_SHARED); - - ddr2->rtr = 0x411; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct atmel_mpddrc_config ddr2; - unsigned long csa; - - ddr2_conf(&ddr2); - - /* enable DDR2 clock */ - at91_system_clk_enable(AT91_PMC_DDR); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - writel(csa, &matrix->ebicsa); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); -} -#endif diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig deleted file mode 100644 index 2e7090ec34..0000000000 --- a/board/laird/wb50n/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WB50N - -config SYS_BOARD - default "wb50n" - -config SYS_VENDOR - default "laird" - -config SYS_CONFIG_NAME - default "wb50n" - -endif diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS deleted file mode 100644 index 3d38fc4e9f..0000000000 --- a/board/laird/wb50n/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WB50N CPU MODULE -M: Ben Whitten <ben.whitten@lairdtech.com> -S: Maintained -F: board/laird/wb50n/ -F: include/configs/wb50n.h -F: configs/wb50n_defconfig diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile deleted file mode 100644 index f4c3831db4..0000000000 --- a/board/laird/wb50n/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += wb50n.o diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c deleted file mode 100644 index 8fa989a2a4..0000000000 --- a/board/laird/wb50n/wb50n.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/at91_sfr.h> -#include <asm/arch/sama5d3_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <env.h> -#include <micrel.h> -#include <net.h> -#include <netdev.h> -#include <spl.h> -#include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/at91_wdt.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -void wb50n_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - at91_periph_clk_enable(ATMEL_ID_SMC); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), - &smc->cs[3].cycle); - writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | - AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | - AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | - AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - - /* Disable Flash Write Protect Line */ - at91_set_pio_output(AT91_PIO_PORTE, 14, 1); -} - -int board_early_init_f(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - at91_seriald_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - wb50n_nand_hw_init(); - - at91_macb_hw_init(); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); - /* tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); - /* rx/tx clock delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; - - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); - - return rc; -} - -#ifdef CONFIG_BOARD_LATE_INIT -#include <linux/ctype.h> -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - const char *LAIRD_NAME = "lrd_name"; - char name[32], *p; - - strcpy(name, get_cpu_name()); - for (p = name; *p != '\0'; *p = tolower(*p), p++) - ; - strcat(name, "-wb50n"); - env_set(LAIRD_NAME, name); - -#endif - - return 0; -} -#endif - -/* SPL */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ - wb50n_nand_hw_init(); -} - -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_NDQS_DISABLED | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | - ATMEL_MPDDRC_CR_UNAL_SUPPORTED); - - ddr2->rtr = 0x411; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct atmel_mpddrc_config ddr2; - - ddr2_conf(&ddr2); - - configure_ddrcfg_input_buffers(true); - - /* enable MPDDR clock */ - at91_periph_clk_enable(ATMEL_ID_MPDDRC); - at91_system_clk_enable(AT91_PMC_DDR); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); -} - -void at91_pmc_init(void) -{ - u32 tmp; - - tmp = AT91_PMC_PLLAR_29 | - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | - AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); - at91_plla_init(tmp); - - at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); - - tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; - at91_mck_init(tmp); -} -#endif diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig deleted file mode 100644 index 98ec0c457a..0000000000 --- a/board/mini-box/picosam9g45/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PICOSAM9G45 - -config SYS_BOARD - default "picosam9g45" - -config SYS_VENDOR - default "mini-box" - -config SYS_CONFIG_NAME - default "picosam9g45" - -endif diff --git a/board/mini-box/picosam9g45/MAINTAINERS b/board/mini-box/picosam9g45/MAINTAINERS deleted file mode 100644 index a8cf01d703..0000000000 --- a/board/mini-box/picosam9g45/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PICOSAM9G45 BOARD -M: Erik van Luijk <evanluijk@interact.nl> -S: Maintained -F: board/mini-box/picosam9g45/ -F: include/configs/picosam9g45.h -F: configs/picosam9g45_defconfig diff --git a/board/mini-box/picosam9g45/Makefile b/board/mini-box/picosam9g45/Makefile deleted file mode 100644 index 6e98997a7c..0000000000 --- a/board/mini-box/picosam9g45/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board -# (C) Copytight 2015 Inter Act B.V. -# -# Based on: -# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop <stelian@popies.net> -# Lead Tech Design <www.leadtechdesign.com> - -obj-y += picosam9g45.o -obj-y += led.o diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c deleted file mode 100644 index 8ce8b6bbea..0000000000 --- a/board/mini-box/picosam9g45/led.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - */ - -#include <common.h> -#include <status_led.h> -#include <asm/io.h> -#include <asm/arch/at91sam9g45.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> - -void coloured_LED_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIODE); - - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - - at91_set_gpio_value(CONFIG_GREEN_LED, 1); -} diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c deleted file mode 100644 index 5d6cb24966..0000000000 --- a/board/mini-box/picosam9g45/picosam9g45.c +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - */ - -#include <common.h> -#include <init.h> -#include <vsprintf.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/at91sam9g45_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <lcd.h> -#include <linux/mtd/rawnand.h> -#include <atmel_lcdc.h> -#include <atmel_mci.h> -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <net.h> -#endif -#include <netdev.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -#if defined(CONFIG_SPL_BUILD) -#include <spl.h> - -void at91_spl_board_init(void) -{ -#ifdef CONFIG_SYS_USE_MMC - at91_mci_hw_init(); -#endif -} - -#include <asm/arch/atmel_mpddrc.h> -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_14 | - ATMEL_MPDDRC_CR_DQMS_SHARED | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3); - - ddr2->rtr = 0x24b; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ - 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ - 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct atmel_mpddrc_config ddr2; - unsigned long csa; - - ddr2_conf(&ddr2); - - at91_system_clk_enable(AT91_PMC_DDR); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&mat->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; - writel(csa, &mat->ebicsa); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); - ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2); -} -#endif - -#ifdef CONFIG_CMD_USB -static void picosam9g45_usb_hw_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIODE); - - at91_set_gpio_output(AT91_PIN_PD1, 0); - at91_set_gpio_output(AT91_PIN_PD3, 0); -} -#endif - -#ifdef CONFIG_MACB -static void picosam9g45_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->puer); - - /* And the pins. */ - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_LCD - -vidinfo_t panel_info = { - .vl_col = 480, - .vl_row = 272, - .vl_clk = 9000000, - .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | - ATMEL_LCDC_INVFRAME_NORMAL, - .vl_bpix = 3, - .vl_tft = 1, - .vl_hsync_len = 45, - .vl_left_margin = 1, - .vl_right_margin = 1, - .vl_vsync_len = 1, - .vl_upper_margin = 40, - .vl_lower_margin = 1, - .mmio = ATMEL_BASE_LCDC, -}; - - -void lcd_enable(void) -{ - at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ -} - -void lcd_disable(void) -{ - at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ -} - -static void picosam9g45_lcd_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ - at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ - at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ - - at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ - at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ - at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ - at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ - at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - - at91_periph_clk_enable(ATMEL_ID_LCDC); - - gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; -} - -#ifdef CONFIG_LCD_INFO -#include <nand.h> -#include <version.h> - -void lcd_show_board_info(void) -{ - ulong dram_size; - int i; - char temp[32]; - - lcd_printf("%s\n", U_BOOT_VERSION); - lcd_printf("(C) 2015 Inter Act B.V.\n"); - lcd_printf("support@interact.nl\n"); - lcd_printf("%s CPU at %s MHz\n", - ATMEL_CPU_NAME, - strmhz(temp, get_cpu_clk_rate())); - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - lcd_printf(" %ld MB SDRAM\n", dram_size >> 20); -} -#endif /* CONFIG_LCD_INFO */ -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(struct bd_info *bis) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI0); -} -#endif - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_CMD_USB - picosam9g45_usb_hw_init(); -#endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); -#endif -#ifdef CONFIG_MACB - picosam9g45_macb_hw_init(); -#endif -#ifdef CONFIG_LCD - picosam9g45_lcd_hw_init(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); -#endif - return rc; -} - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 2; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 0); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 0); - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 1); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 1); - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig deleted file mode 100644 index f4da68b5ba..0000000000 --- a/board/phytec/pfla02/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_PFLA02 - -config SYS_BOARD - default "pfla02" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "pfla02" - -config SPL_DRAM_1_BANK - bool "DRAM on just one bank" - help - activate, if the module has just one bank - of RAM - -endif diff --git a/board/phytec/pfla02/MAINTAINERS b/board/phytec/pfla02/MAINTAINERS deleted file mode 100644 index 4b069a90cd..0000000000 --- a/board/phytec/pfla02/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PHYTEC PHYFLEX -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/phytec/pfla02/ -F: include/configs/pfla02.h -F: configs/pfla02_defconfig diff --git a/board/phytec/pfla02/Makefile b/board/phytec/pfla02/Makefile deleted file mode 100644 index c50f315d91..0000000000 --- a/board/phytec/pfla02/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := pfla02.o diff --git a/board/phytec/pfla02/README b/board/phytec/pfla02/README deleted file mode 100644 index 0f46ab8623..0000000000 --- a/board/phytec/pfla02/README +++ /dev/null @@ -1,24 +0,0 @@ -Board information ------------------ - -The evaluation board "pbab01" is thought to be used -together with the SOM. - -More information on the board can be found on manufacturer's -website: - -http://www.phytec.de/produkt/system-on-modules/phyflex-imx-6/ - -Building U-Boot -------------------------------- - -$ make pfla02_defconfig -$ make - -This generates the artifacts SPL and u-boot.img. -The SOM can boot from NAND or from SD-Card, having the SPI-NOR -as second option. -The dip switch "SW3" on the board let choose the boot device. - -SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI -SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c deleted file mode 100644 index 076ce6711e..0000000000 --- a/board/phytec/pfla02/pfla02.c +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Stefano Babic <sbabic@denx.de> - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/spi.h> -#include <env.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <mmc.h> -#include <i2c.h> -#include <fsl_esdhc_imx.h> -#include <nand.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/sys_proto.h> -#include <asm/sections.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14) -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define GREEN_LED IMX_GPIO_NR(2, 31) -#define RED_LED IMX_GPIO_NR(1, 30) -#define IMX6Q_DRIVE_STRENGTH 0x30 - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const ecspi3_pads[] = { - IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const gpios_pads[] = { - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) -/* NAND */ -static iomux_v3_cfg_t const nfc_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)), -}; -#endif - -static struct i2c_pads_info i2c_pad_info = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC3_BASE_ADDR, - .max_bus_width = 4}, - {.esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 4}, -}; - -#if !defined(CONFIG_SPL_BUILD) -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; -#endif - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - ret = 1; - break; - case USDHC3_BASE_ADDR: - ret = 1; - break; - } - - return ret; -} - -#ifndef CONFIG_SPL_BUILD -int board_mmc_init(struct bd_info *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 1: - SETUP_IOMUX_PADS(usdhc2_pads); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart4_pads); -} - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); - - gpio_direction_output(ENET_PHY_RESET_GPIO, 0); - mdelay(10); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); - mdelay(30); -} - -static void setup_spi(void) -{ - gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0"); - gpio_direction_output(IMX_GPIO_NR(4, 24), 1); - - SETUP_IOMUX_PADS(ecspi3_pads); - - enable_spi_clk(true, 2); -} - -static void setup_gpios(void) -{ - SETUP_IOMUX_PADS(gpios_pads); -} - -#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(nfc_pads); - - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -/* - * Board revision is coded in 4 GPIOs - */ -u32 get_board_rev(void) -{ - u32 rev; - int i; - - for (i = 0, rev = 0; i < 4; i++) - rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i); - - return 16 - rev; -} - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - if (bus != 2 || (cs != 0)) - return -EINVAL; - - return IMX_GPIO_NR(4, 24); -} - -int board_eth_init(struct bd_info *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info); -#endif - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - - setup_gpios(); - -#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) - setup_gpmi_nand(); -#endif - return 0; -} - - -#ifdef CONFIG_CMD_BMODE -/* - * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 - * see Table 8-11 and Table 5-9 - * BOOT_CFG1[7] = 1 (boot from NAND) - * BOOT_CFG1[5] = 0 - raw NAND - * BOOT_CFG1[4] = 0 - default pad settings - * BOOT_CFG1[3:2] = 00 - devices = 1 - * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 - * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 - * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 - * BOOT_CFG2[0] = 0 - Reset time 12ms - */ -static const struct boot_mode board_boot_modes[] = { - /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ - {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)}, - {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ - char buf[10]; -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - snprintf(buf, sizeof(buf), "%d", get_board_rev()); - env_set("board_rev", buf); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#include <asm/arch/mx6-ddr.h> -#include <spl.h> -#include <linux/libfdt.h> - -#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) -static void phyflex_err006282_workaround(void) -{ - /* - * Boards beginning with 1362.2 have the SD4_DAT3 pin connected - * to the CMIC. If this pin isn't toggled within 10s the boards - * reset. The pin is unconnected on older boards, so we do not - * need a check for older boards before applying this fixup. - */ - - gpio_direction_output(MX6_PHYFLEX_ERR006282, 0); - mdelay(2); - gpio_direction_output(MX6_PHYFLEX_ERR006282, 1); - mdelay(2); - gpio_set_value(MX6_PHYFLEX_ERR006282, 0); - - gpio_direction_input(MX6_PHYFLEX_ERR006282); -} - -static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000030, - .dram_sdodt0 = 0x00000030, - .dram_sdodt1 = 0x00000030, - - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_sdqs2 = 0x00000028, - .dram_sdqs3 = 0x00000028, - .dram_sdqs4 = 0x00000028, - .dram_sdqs5 = 0x00000028, - .dram_sdqs6 = 0x00000028, - .dram_sdqs7 = 0x00000028, - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_dqm2 = 0x00000028, - .dram_dqm3 = 0x00000028, - .dram_dqm4 = 0x00000028, - .dram_dqm5 = 0x00000028, - .dram_dqm6 = 0x00000028, - .dram_dqm7 = 0x00000028, -}; - -static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = IMX6Q_DRIVE_STRENGTH, - .grp_ctlds = IMX6Q_DRIVE_STRENGTH, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_b2ds = 0x00000028, - .grp_b3ds = 0x00000028, - .grp_b4ds = 0x00000028, - .grp_b5ds = 0x00000028, - .grp_b6ds = 0x00000028, - .grp_b7ds = 0x00000028, -}; - -static const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00110011, - .p0_mpwldectrl1 = 0x00240024, - .p1_mpwldectrl0 = 0x00260038, - .p1_mpwldectrl1 = 0x002C0038, - .p0_mpdgctrl0 = 0x03400350, - .p0_mpdgctrl1 = 0x03440340, - .p1_mpdgctrl0 = 0x034C0354, - .p1_mpdgctrl1 = 0x035C033C, - .p0_mprddlctl = 0x322A2A2A, - .p1_mprddlctl = 0x302C2834, - .p0_mpwrdlctl = 0x34303834, - .p1_mpwrdlctl = 0x422A3E36, -}; - -/* Index in RAM Chip array */ -enum { - RAM_MT64K, - RAM_MT128K, - RAM_MT256K -}; - -static struct mx6_ddr3_cfg mt41k_xx[] = { -/* MT41K64M16JT-125 (1Gb density) */ - { - .mem_speed = 1600, - .density = 1, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - }, - -/* MT41K256M16JT-125 (2Gb density) */ - { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - }, - -/* MT41K256M16JT-125 (4Gb density) */ - { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - } -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo, - struct mx6_ddr3_cfg *mem_ddr) -{ - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr); -} - -int board_mmc_init(struct bd_info *bis) -{ - if (spl_boot_device() == BOOT_DEVICE_SPI) - printf("MMC SEtup, Boot SPI"); - - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - printf("Boot device %x\n", spl_boot_list[0]); - switch (spl_boot_list[0]) { - case BOOT_DEVICE_SPI: - spl_boot_list[1] = BOOT_DEVICE_UART; - break; - case BOOT_DEVICE_MMC1: - spl_boot_list[1] = BOOT_DEVICE_SPI; - spl_boot_list[2] = BOOT_DEVICE_UART; - break; - default: - printf("Boot device %x\n", spl_boot_list[0]); - } -} - -/* - * This is used because get_ram_size() does not - * take care of cache, resulting a wrong size - * pfla02 has just 1, 2 or 4 GB option - * Function checks for mirrors in the first CS - */ -#define RAM_TEST_PATTERN 0xaa5555aa -#define MIN_BANK_SIZE (512 * 1024 * 1024) - -static unsigned int pfla02_detect_chiptype(void) -{ - u32 *p, *p1; - unsigned int offset = MIN_BANK_SIZE; - int i; - - for (i = 0; i < 2; i++) { - p = (u32 *)PHYS_SDRAM; - p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset); - - *p1 = 0; - *p = RAM_TEST_PATTERN; - - /* - * This is required to detect mirroring - * else we read back values from cache - */ - flush_dcache_all(); - - if (*p == *p1) - return i; - } - return RAM_MT256K; -} - -void board_init_f(ulong dummy) -{ - unsigned int ramchip; - - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 512 MB */ - /* single chip select */ -#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) - .ncs = 1, -#else - .ncs = 2, -#endif - .cs1_mirror = 1, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - -#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) - /* Enable NAND */ - setup_gpmi_nand(); -#endif - - /* setup clock gating */ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - /* setup AXI */ - gpr_init(); - - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - setup_spi(); - - setup_gpios(); - - /* DDR initialization */ - spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); - ramchip = pfla02_detect_chiptype(); - debug("Detected chip %d\n", ramchip); -#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) - switch (ramchip) { - case RAM_MT64K: - sysinfo.cs_density = 6; - break; - case RAM_MT128K: - sysinfo.cs_density = 10; - break; - case RAM_MT256K: - sysinfo.cs_density = 18; - break; - } -#endif - spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - phyflex_err006282_workaround(); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig deleted file mode 100644 index ab4a29255c..0000000000 --- a/board/sandisk/sansa_fuze_plus/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_SANSA_FUZE_PLUS - -config SYS_BOARD - default "sansa_fuze_plus" - -config SYS_VENDOR - default "sandisk" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "sansa_fuze_plus" - -endif diff --git a/board/sandisk/sansa_fuze_plus/MAINTAINERS b/board/sandisk/sansa_fuze_plus/MAINTAINERS deleted file mode 100644 index ccfd399708..0000000000 --- a/board/sandisk/sansa_fuze_plus/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SANSA_FUZE_PLUS BOARD -M: Marek Vasut <marek.vasut@gmail.com> -S: Maintained -F: board/sandisk/sansa_fuze_plus/ -F: include/configs/sansa_fuze_plus.h -F: configs/sansa_fuze_plus_defconfig diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile deleted file mode 100644 index 5ac545dda3..0000000000 --- a/board/sandisk/sansa_fuze_plus/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := sfp.o -else -obj-y := spl_boot.o -endif diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c deleted file mode 100644 index f46b02e38e..0000000000 --- a/board/sandisk/sansa_fuze_plus/sfp.c +++ /dev/null @@ -1,391 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SanDisk Sansa Fuze Plus board - * - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * Hardware investigation done by: - * - * Amaury Pouly <amaury.pouly@gmail.com> - */ - -#include <common.h> -#include <errno.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int xfi3_mmc_cd(int id) -{ - switch (id) { - case 0: - /* The SSP_DETECT is inverted on this board. */ - return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); - case 1: - /* Internal eMMC always present */ - return 1; - default: - return 0; - } -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - /* MicroSD slot */ - gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); - gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0); - ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); - if (ret) - return ret; - - /* Internal eMMC */ - gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); - ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); - - return ret; -} -#endif - -#ifdef CONFIG_VIDEO_MXS -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -const iomux_cfg_t iomux_lcd_gpio[] = { - MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD, -}; - -const iomux_cfg_t iomux_lcd_lcd[] = { - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, -}; - -static int mxsfb_read_register(uint32_t reg, uint32_t *value) -{ - iomux_cfg_t mux; - uint32_t val = 0; - int i; - - /* Mangle the register offset. */ - reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10); - - /* - * The SmartLCD interface on MX233 can only do WRITE operation - * via the LCDIF controller. Implement the READ operation by - * fiddling with bits. - */ - mxs_iomux_setup_multiple_pads(iomux_lcd_gpio, - ARRAY_SIZE(iomux_lcd_gpio)); - - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_output(mux, 0); - } - - udelay(2); - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0); - udelay(1); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_output(mux, (reg >> i) & 1); - } - udelay(1); - - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); - udelay(3); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_input(mux); - } - udelay(2); - - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - udelay(3); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); - udelay(2); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - val |= !!gpio_get_value(mux) << i; - } - udelay(1); - - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); - udelay(1); - - mxs_iomux_setup_multiple_pads(iomux_lcd_lcd, - ARRAY_SIZE(iomux_lcd_lcd)); - - /* Demangle the register value. */ - *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00); - - writel(val, 0x2000); - return 0; -} - -static int mxsfb_write_byte(uint32_t payload, const unsigned int data) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - const unsigned int timeout = 0x10000; - - /* What is going on here I do not know. FIXME */ - payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10); - - if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout)) - return -ETIMEDOUT; - - writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | - (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), - ®s->hw_lcdif_transfer_count); - - writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, - ®s->hw_lcdif_ctrl_clr); - - if (data) - writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); - - writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); - - if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, - timeout)) - return -ETIMEDOUT; - - writel(payload, ®s->hw_lcdif_data); - return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout); -} - -static void mxsfb_write_register(uint32_t reg, uint32_t data) -{ - mxsfb_write_byte(reg, 0); - mxsfb_write_byte(data, 1); -} - -static const struct { - uint8_t reg; - uint8_t delay; - uint16_t val; -} lcd_regs[] = { - { 0xe5, 0 , 0x78f0 }, - { 0xe3, 0 , 0x3008 }, - { 0xe7, 0 , 0x0012 }, - { 0xef, 0 , 0x1231 }, - { 0x00, 0 , 0x0001 }, - { 0x01, 0 , 0x0100 }, - { 0x02, 0 , 0x0700 }, - { 0x03, 0 , 0x1030 }, - { 0x04, 0 , 0x0000 }, - { 0x08, 0 , 0x0207 }, - { 0x09, 0 , 0x0000 }, - { 0x0a, 0 , 0x0000 }, - { 0x0c, 0 , 0x0000 }, - { 0x0d, 0 , 0x0000 }, - { 0x0f, 0 , 0x0000 }, - { 0x10, 0 , 0x0000 }, - { 0x11, 0 , 0x0007 }, - { 0x12, 0 , 0x0000 }, - { 0x13, 20 , 0x0000 }, - /* Wait 20 mS here. */ - { 0x10, 0 , 0x1290 }, - { 0x11, 50 , 0x0007 }, - /* Wait 50 mS here. */ - { 0x12, 50 , 0x0019 }, - /* Wait 50 mS here. */ - { 0x13, 0 , 0x1700 }, - { 0x29, 50 , 0x0014 }, - /* Wait 50 mS here. */ - { 0x20, 0 , 0x0000 }, - { 0x21, 0 , 0x0000 }, - { 0x30, 0 , 0x0504 }, - { 0x31, 0 , 0x0007 }, - { 0x32, 0 , 0x0006 }, - { 0x35, 0 , 0x0106 }, - { 0x36, 0 , 0x0202 }, - { 0x37, 0 , 0x0504 }, - { 0x38, 0 , 0x0500 }, - { 0x39, 0 , 0x0706 }, - { 0x3c, 0 , 0x0204 }, - { 0x3d, 0 , 0x0202 }, - { 0x50, 0 , 0x0000 }, - { 0x51, 0 , 0x00ef }, - { 0x52, 0 , 0x0000 }, - { 0x53, 0 , 0x013f }, - { 0x60, 0 , 0xa700 }, - { 0x61, 0 , 0x0001 }, - { 0x6a, 0 , 0x0000 }, - { 0x2b, 50 , 0x000d }, - /* Wait 50 mS here. */ - { 0x90, 0 , 0x0011 }, - { 0x92, 0 , 0x0600 }, - { 0x93, 0 , 0x0003 }, - { 0x95, 0 , 0x0110 }, - { 0x97, 0 , 0x0000 }, - { 0x98, 0 , 0x0000 }, - { 0x07, 0 , 0x0173 }, -}; - -void board_mxsfb_system_setup(void) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - uint32_t id; - int i; - - /* Switch the LCDIF into System-Mode */ - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | - LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); - - /* To program the LCD, switch to 18bit bus + 18bit data. */ - clrsetbits_le32(®s->hw_lcdif_ctrl, - LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, - LCDIF_CTRL_WORD_LENGTH_18BIT | - LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); - - mxsfb_read_register(0, &id); - writel(id, 0x2004); - - /* Restart the SmartLCD controller */ - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_clr); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - - /* Program the SmartLCD controller */ - writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); - - writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) | - (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) | - (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) | - (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET), - ®s->hw_lcdif_timing); - - /* - * ILI9325 init and configuration sequence. - */ - for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { - mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); - if (lcd_regs[i].delay) - mdelay(lcd_regs[i].delay); - } - /* Turn on Framebuffer Upload Mode */ - mxsfb_write_byte(0x22, 0); - - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, - ®s->hw_lcdif_ctrl_set); - - /* Operate the framebuffer in 16bit mode. */ - clrsetbits_le32(®s->hw_lcdif_ctrl, - LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, - LCDIF_CTRL_WORD_LENGTH_16BIT | - LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); -} -#endif - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Turn on PWM backlight */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - usb_eth_initialize(bis); - return 0; -} diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c deleted file mode 100644 index 633c77408d..0000000000 --- a/board/sandisk/sansa_fuze_plus/spl_boot.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SanDisk Sansa Fuze Plus setup - * - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP, - - MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, - MX23_PAD_GPMI_WRN__SSP2_SCK | - (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), - MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP, - - /* PWM -- FIXME */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* mDDR configuration values */ - const uint32_t regs[] = { - 0x01010001, 0x00010000, 0x01000000, 0x00000001, - 0x00010101, 0x00000001, 0x00010000, 0x01000001, - 0x01010000, 0x00000001, 0x07000200, 0x04070203, - 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, - 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, - 0x03061323, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000000, 0x00000020, 0x00000000, - 0x001023cd, 0x20410010, 0x00006665, 0x00000000, - 0x00000101, 0x00000001, 0x00000000, 0x00000000, - }; - memcpy(dram_vals, regs, sizeof(regs)); -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig deleted file mode 100644 index 2461d0cc50..0000000000 --- a/board/schulercontrol/sc_sps_1/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_SC_SPS_1 - -config SYS_BOARD - default "sc_sps_1" - -config SYS_VENDOR - default "schulercontrol" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "sc_sps_1" - -endif diff --git a/board/schulercontrol/sc_sps_1/MAINTAINERS b/board/schulercontrol/sc_sps_1/MAINTAINERS deleted file mode 100644 index 74849cdfaf..0000000000 --- a/board/schulercontrol/sc_sps_1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SC_SPS_1 BOARD -M: Marek Vasut <marek.vasut@gmail.com> -S: Maintained -F: board/schulercontrol/sc_sps_1/ -F: include/configs/sc_sps_1.h -F: configs/sc_sps_1_defconfig diff --git a/board/schulercontrol/sc_sps_1/Makefile b/board/schulercontrol/sc_sps_1/Makefile deleted file mode 100644 index 4fb32de6e8..0000000000 --- a/board/schulercontrol/sc_sps_1/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2012 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := sc_sps_1.o -else -obj-y := spl_boot.o -endif diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c deleted file mode 100644 index 3a04b1a634..0000000000 --- a/board/schulercontrol/sc_sps_1/sc_sps_1.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SchulerControl GmbH, SC_SPS_1 module - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | - MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); - gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1); -#endif - - return 0; -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - int ret; - - ret = cpu_eth_init(bis); - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK, - CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - return ret; -} - -#endif diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c deleted file mode 100644 index 68758eb997..0000000000 --- a/board/schulercontrol/sc_sps_1/spl_boot.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SchulerControl GmbH, SC_SPS_1 module setup - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* -- Strick 3 -- */ - - /* FEC Ethernet */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - - MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */ - - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* -- Strick 4 -- */ - - /* EMI */ - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - - /* -- Strick 5 -- */ - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - - /* SPI2 (for flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - - /* -- Strick 6 -- */ - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* AUART0 */ - MX28_PAD_AUART0_TX__AUART0_TX, - MX28_PAD_AUART0_RX__AUART0_RX, - - /* MEGA interface */ - - /* Debug UART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* LED */ - MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED, - MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED, - MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED, -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[0x74 >> 2] = 0x0f02010a; -} diff --git a/board/seco/Kconfig b/board/seco/Kconfig deleted file mode 100644 index 12dd965ad5..0000000000 --- a/board/seco/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if TARGET_SECOMX6 - -choice - prompt "SECO i.MX6 Board variant" - optional - -config SECOMX6_Q7 - bool "Q7" - -config SECOMX6_UQ7 - bool "uQ7" - -config SECOMX6_USBC - bool "uSBC" - -endchoice - -choice - prompt "SECO i.MX6 SoC variant" - optional - -config SECOMX6Q - bool "i.MX6Q" - depends on MX6Q - -config SECOMX6DL - bool "i.MX6DL" - depends on MX6DL - -config SECOMX6S - bool "i.MX6S" - depends on MX6S - -endchoice - -choice - prompt "DDR size" - -config SECOMX6_512MB - bool "512MB" - -config SECOMX6_1GB - bool "1GB" - -config SECOMX6_2GB - bool "2GB" - -config SECOMX6_4GB - bool "4GB" - -endchoice - -config IMX_CONFIG - default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB - -config SYS_BOARD - default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q - -config SYS_VENDOR - default "seco" - -config SYS_CONFIG_NAME - default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q - -endif diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile deleted file mode 100644 index 4220e89bc5..0000000000 --- a/board/seco/common/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-$(CONFIG_TARGET_SECOMX6) += mx6.o diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c deleted file mode 100644 index 51832b9d08..0000000000 --- a/board/seco/common/mx6.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2015 ECA Sinters - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <micrel.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <i2c.h> - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -void seco_mx6_setup_uart_iomux(void) -{ - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -void seco_mx6_setup_enet_iomux(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -int seco_mx6_rgmii_rework(struct phy_device *phydev) -{ - /* control data pad skew - devaddr = 0x02, register = 0x04 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* rx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* tx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - - /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); - return 0; -} - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | \ - PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -void seco_mx6_setup_usdhc_iomux(int id) -{ - switch (id) { - case 3: - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, - ARRAY_SIZE(usdhc3_pads)); - break; - - case 4: - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, - ARRAY_SIZE(usdhc4_pads)); - break; - - default: - printf("Warning: invalid usdhc id (%d)\n", id); - break; - } -} diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h deleted file mode 100644 index a05db673e2..0000000000 --- a/board/seco/common/mx6.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __SECO_COMMON_MX6_H -#define __SECO_COMMON_MX6_H - -void seco_mx6_setup_uart_iomux(void); -void seco_mx6_setup_enet_iomux(void); -int seco_mx6_rgmii_rework(struct phy_device *phydev); -void seco_mx6_setup_usdhc_iomux(int id); - -#endif /* __SECO_COMMON_MX6_H */ diff --git a/board/seco/mx6quq7/MAINTAINERS b/board/seco/mx6quq7/MAINTAINERS deleted file mode 100644 index 60fd4caab8..0000000000 --- a/board/seco/mx6quq7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX6QUQ7 BOARD -M: Boris Brezillon <boris.brezillon@free-electrons.com> -S: Maintained -F: board/seco/mx6quq7/ -F: include/configs/secomx6quq7.h -F: configs/secomx6quq7_defconfig diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile deleted file mode 100644 index c7aea8c851..0000000000 --- a/board/seco/mx6quq7/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2015 ECA Sinters - -obj-y := mx6quq7.o diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg deleted file mode 100644 index 68d13cc92b..0000000000 --- a/board/seco/mx6quq7/mx6quq7-2g.cfg +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013 Seco USA Inc - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* DDR IO TYPE */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* DATA STROBE */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 - -/* DATA */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 -/* ADDRESS */ -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028 -DATA 4, MX6_IOM_DRAM_CAS, 0x00000028 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000028 - -/* CONTROL */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028 - -/* CLOCK */ -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 - -/* - * DDR3 SETTINGS - * Read Data Bit Delay - */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - - -/* Write Leveling */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F - -/* DQS gating, read delay, write delay calibration values */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C - -/* Read calibration */ -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45 - -/* write calibration */ -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C - -/* Complete calibration by forced measurement: */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* - * MMDC init: - * in DDR3, 64-bit mode, only MMDC0 is init - */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 - -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB - -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 - -/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 - -/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 - -/* Initialize DDR3 on CS_0 and CS_1 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 - -/* P0 01c */ -/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 - -/*ZQ - Calibrationi */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 - -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF - -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c deleted file mode 100644 index a061d7d8af..0000000000 --- a/board/seco/mx6quq7/mx6quq7.c +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2015 ECA Sinters - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> - */ - -#include <init.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <malloc.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <i2c.h> - -#include "../common/mx6.h" - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -int board_early_init_f(void) -{ - seco_mx6_setup_uart_iomux(); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - seco_mx6_rgmii_rework(phydev); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret = 0; - - seco_mx6_setup_enet_iomux(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return -ENOMEM; - - /* scan phy 4,5,6,7 */ - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - free(bus); - return -ENOMEM; - } - - printf("using phy at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - free(phydev); - free(bus); - printf("FEC MXC: %s:failed\n", __func__); - } -#endif - - return ret; -} - -#define USDHC4_CD_GPIO IMX_GPIO_NR(2, 6) - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR, 0, 4}, - {USDHC4_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC3_BASE_ADDR: - ret = 1; /* Assume eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - u32 index = 0; - int ret; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 eMMC on Board - * mmc1 Ext SD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - seco_mx6_setup_usdhc_iomux(3); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 1: - seco_mx6_setup_usdhc_iomux(4); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - - default: - printf("Warning: %d exceed maximum number of SD ports %d\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | - MUX_PAD_CTRL(NO_PAD_CTRL)); - - gpio_direction_output(IMX_GPIO_NR(2, 4), 0); - - /* Set Low */ - gpio_set_value(IMX_GPIO_NR(2, 4), 0); - udelay(1000); - - /* Set High */ - gpio_set_value(IMX_GPIO_NR(2, 4), 1); - - return 0; -} - -int checkboard(void) -{ - puts("Board: SECO uQ7\n"); - - return 0; -} diff --git a/board/technexion/tao3530/Kconfig b/board/technexion/tao3530/Kconfig deleted file mode 100644 index 27bc91f8ca..0000000000 --- a/board/technexion/tao3530/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TAO3530 - -config SYS_BOARD - default "tao3530" - -config SYS_VENDOR - default "technexion" - -config SYS_CONFIG_NAME - default "tao3530" - -endif diff --git a/board/technexion/tao3530/MAINTAINERS b/board/technexion/tao3530/MAINTAINERS deleted file mode 100644 index ad02b46f70..0000000000 --- a/board/technexion/tao3530/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -TAO3530 BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/technexion/tao3530/ -F: include/configs/tao3530.h -F: configs/omap3_ha_defconfig - -TAO3530 BOARD -M: Tapani Utriainen <linuxfae@technexion.com> -S: Maintained -F: configs/tao3530_defconfig diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile deleted file mode 100644 index 0297daf64e..0000000000 --- a/board/technexion/tao3530/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := tao3530.o diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c deleted file mode 100644 index 0c9dca31e6..0000000000 --- a/board/technexion/tao3530/tao3530.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Maintainer : - * Tapani Utriainen <linuxfae@technexion.com> - */ -#include <common.h> -#include <bootstage.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <twl4030.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <asm/mach-types.h> - -#include <usb.h> -#include <asm/ehci-omap.h> - -#include "tao3530.h" - -DECLARE_GLOBAL_DATA_PTR; - -int tao3530_revision(void) -{ - int ret = 0; - - /* char *label argument is unused in gpio_request() */ - ret = gpio_request(65, ""); - if (ret) { - puts("Error: GPIO 65 not available\n"); - goto out; - } - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); - - ret = gpio_request(1, ""); - if (ret) { - puts("Error: GPIO 1 not available\n"); - goto out2; - } - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); - - ret = gpio_direction_input(65); - if (ret) { - puts("Error: GPIO 65 not available for input\n"); - goto out3; - } - - ret = gpio_direction_input(1); - if (ret) { - puts("Error: GPIO 1 not available for input\n"); - goto out3; - } - - ret = gpio_get_value(65) << 1 | gpio_get_value(1); - -out3: - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0)); - gpio_free(1); -out2: - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); - gpio_free(65); -out: - - return ret; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ -#if defined(CONFIG_SYS_BOARD_OMAP3_HA) - /* - * Switch baseboard LED to red upon power-on - */ - MUX_OMAP3_HA(); - - /* Request a gpio before using it */ - gpio_request(111, ""); - /* Sets the gpio as output and its value to 1, switch LED to red */ - gpio_direction_output(111, 1); -#endif - - if (tao3530_revision() < 3) { - /* 256MB / Bank */ - timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - } else { - /* 128MB / Bank */ - timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */ - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - } - - timings->mr = MICRON_V_MR_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; -} -#endif - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; - struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; - - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - - /* Configure GPIOs to output */ - /* GPIO23 */ - writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); - writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); - - /* Set GPIOs */ - writel(GPIO10 | GPIO8 | GPIO2 | GPIO1, - &gpio6_base->setdataout); - writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); - - switch (tao3530_revision()) { - case 0: - puts("TAO-3530 REV Reserve 1\n"); - break; - case 1: - puts("TAO-3530 REV Reserve 2\n"); - break; - case 2: - puts("TAO-3530 REV Cx\n"); - break; - case 3: - puts("TAO-3530 REV Ax/Bx\n"); - break; - default: - puts("Unknown board revision\n"); - } - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_TAO3530(); -#if defined(CONFIG_SYS_BOARD_OMAP3_HA) - MUX_OMAP3_HA(); -#endif -} - -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - omap_mmc_init(0, 0, 0, -1, -1); - - return 0; -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) -/* Call usb_stop() before starting the kernel */ -void show_boot_progress(int val) -{ - if (val == BOOTSTAGE_ID_RUN_OS) - usb_stop(); -} - -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif /* CONFIG_USB_EHCI_HCD */ diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h deleted file mode 100644 index f5ffce871d..0000000000 --- a/board/technexion/tao3530/tao3530.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright TechNexion 2010 - * Edward Lin <linuxfae@technexion.com> - */ -#ifndef _TAO3530_H_ -#define _TAO3530_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, -#if defined(CONFIG_SYS_BOARD_OMAP3_HA) - "HEAD acoustics OMAP3-HA", -#else - "OMAP3 TAO-3530 board", -#endif - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_TAO3530() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \ - /* - CAM_RESET*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ - /*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ - /*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \ - /* MMC2 WLAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ - /*LocalBus LAN Reset*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \ - /*LocalBus LAN IRQ*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - /*Modem Interface */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \ - /* USB EHCI (port 2) */\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \ - /* - VIO_1V8*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) - -#define MUX_OMAP3_HA() \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */ - -#endif diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig deleted file mode 100644 index d0dc2e1b73..0000000000 --- a/board/technologic/ts4600/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TS4600 - -config SYS_BOARD - default "ts4600" - -config SYS_VENDOR - default "technologic" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "ts4600" - -endif diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS deleted file mode 100644 index 6f683b5995..0000000000 --- a/board/technologic/ts4600/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TS4600 BOARD -M: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> -S: Maintained -F: board/technologic/ts4600/ -F: include/configs/ts4600.h -F: configs/ts4600_defconfig diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile deleted file mode 100644 index ddf4a8ee1e..0000000000 --- a/board/technologic/ts4600/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016 Savoir-faire Linux - -ifndef CONFIG_SPL_BUILD -obj-y := ts4600.o -else -obj-y := iomux.o -endif diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c deleted file mode 100644 index 9bd3eacb0b..0000000000 --- a/board/technologic/ts4600/iomux.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> - * - * Based on work from TS7680 code by: - * Kris Bahnsen <kris@embeddedarm.com> - * Mark Featherston <mark@embeddedarm.com> - * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 - * - * Derived from MX28EVK code by - * Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* MMC0 slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - -}; - -#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa - -#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ - ADDR_PINS << 8 | APREBIT) - -#define HW_DRAM_CTL39 (0x9c >> 2) -#define TFAW 0xb -#define TDLL 0xc8 - -#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL) - -#define HW_DRAM_CTL41 (0xa4 >> 2) -#define TPDEX 0x2 -#define TRCD_INT 0x4 -#define TRC 0xd - -#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC) - -#define HW_DRAM_CTL42 (0xa8 >> 2) -#define TRAS_MAX 0x36a6 -#define TRAS_MIN 0xa - -#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN) - -#define HW_DRAM_CTL43 (0xac >> 2) -#define TRP 0x4 -#define TRFC 0x27 -#define TREF 0x2a0 - -#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; - dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG; - dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG; - dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG; - dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c deleted file mode 100644 index b9cce821d9..0000000000 --- a/board/technologic/ts4600/ts4600.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> - * - * Based on work from TS7680 code by: - * Kris Bahnsen <kris@embeddedarm.com> - * Mark Featherston <mark@embeddedarm.com> - * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 - * - * Derived from MX28EVK code by - * Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clocks at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -static int ts4600_mmc_cd(int id) -{ - return 1; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28); - - /* Power-on SD */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1); - udelay(1000); - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - /* SD card */ - ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd); - if(ret != 0) { - printf("SD controller initialized with %d\n", ret); - } - - return ret; -} -#endif - -int checkboard(void) -{ - puts("Board: TS4600\n"); - - return 0; -} diff --git a/board/technologic/ts4800/Kconfig b/board/technologic/ts4800/Kconfig deleted file mode 100644 index a28d5e41bd..0000000000 --- a/board/technologic/ts4800/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TS4800 - -config SYS_BOARD - default "ts4800" - -config SYS_VENDOR - default "technologic" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "ts4800" - -endif diff --git a/board/technologic/ts4800/MAINTAINERS b/board/technologic/ts4800/MAINTAINERS deleted file mode 100644 index e013ee42f8..0000000000 --- a/board/technologic/ts4800/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TS4800 BOARD -M: Lucile Quirion <lucile.quirion@savoirfairelinux.com> -S: Maintained -F: board/ts/ts4800/ -F: include/configs/ts4800.h -F: configs/ts4800_defconfig diff --git a/board/technologic/ts4800/Makefile b/board/technologic/ts4800/Makefile deleted file mode 100644 index ec33cf92ca..0000000000 --- a/board/technologic/ts4800/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2015 Savoir-faire Linux - -obj-y += ts4800.o diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c deleted file mode 100644 index a309e58b27..0000000000 --- a/board/technologic/ts4800/ts4800.c +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Savoir-faire Linux Inc. - * - * Derived from MX51EVK code by - * Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx51.h> -#include <env.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/mach-imx/mx5_video.h> -#include <mmc.h> -#include <input.h> -#include <fsl_esdhc_imx.h> -#include <mc13892.h> - -#include <malloc.h> -#include <netdev.h> -#include <phy.h> -#include "ts4800.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC2_BASE_ADDR}, -}; -#endif - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -u32 get_board_rev(void) -{ - u32 rev = get_cpu_rev(); - if (!gpio_get_value(IMX_GPIO_NR(1, 22))) - rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; - return rev; -} - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, - PAD_CTL_HYS | - PAD_CTL_PUS_22K_UP | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - MX51_PAD_EIM_EB3__FEC_RDATA1, - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS), - MX51_PAD_EIM_CS3__FEC_RDATA3, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_EIM_CS4__FEC_RX_ER, - /* PAD used on TS4800 */ - MX51_PAD_DI2_PIN2__FEC_MDC, - MX51_PAD_DISP2_DAT14__FEC_RDAT0, - MX51_PAD_DISP2_DAT10__FEC_COL, - MX51_PAD_DISP2_DAT11__FEC_RXCLK, - MX51_PAD_DISP2_DAT15__FEC_TDAT0, - MX51_PAD_DISP2_DAT6__FEC_TDAT1, - MX51_PAD_DISP2_DAT7__FEC_TDAT2, - MX51_PAD_DISP2_DAT8__FEC_TDAT3, - MX51_PAD_DISP2_DAT9__FEC_TX_EN, - MX51_PAD_DISP2_DAT13__FEC_TX_CLK, - MX51_PAD_DISP2_DAT12__FEC_RX_DV, - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, - NO_PAD_CTRL)); - gpio_direction_input(IMX_GPIO_NR(1, 0)); - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, - NO_PAD_CTRL)); - gpio_direction_input(IMX_GPIO_NR(1, 6)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); - else - ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | - PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), - NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -/* - * Read the MAC address from FEC's registers PALR PAUR. - * User is supposed to configure these registers when MAC address is known - * from another source (fuse), but on TS4800, MAC address is not fused and - * the bootrom configure these registers on startup. - */ -static int fec_get_mac_from_register(uint32_t base_addr) -{ - unsigned char ethaddr[6]; - u32 reg_mac[2]; - int i; - - reg_mac[0] = in_be32(base_addr + 0xE4); - reg_mac[1] = in_be32(base_addr + 0xE8); - - for(i = 0; i < 6; i++) - ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF; - - if (is_valid_ethaddr(ethaddr)) { - eth_env_set_enetaddr("ethaddr", ethaddr); - return 0; - } - - return -1; -} - -#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14) -int board_eth_init(struct bd_info *bd) -{ - int dev_id = -1; - int phy_id = 0xFF; - uint32_t addr = IMX_FEC_BASE; - - uint32_t base_mii; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - /* reset FEC phy */ - imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14); - gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0); - mdelay(1); - gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1); - mdelay(1); - - base_mii = addr; - debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); - bus = fec_get_miibus(base_mii, dev_id); - if (!bus) - return -ENOMEM; - - phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII); - if (!phydev) { - free(bus); - return -ENOMEM; - } - - if (fec_get_mac_from_register(addr)) - printf("eth_init: failed to get MAC address\n"); - - ret = fec_probe(bd, dev_id, addr, bus, phydev); - if (ret) { - free(phydev); - free(bus); - } - - return ret; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int checkboard(void) -{ - puts("Board: TS4800\n"); - - return 0; -} - -void hw_watchdog_reset(void) -{ - struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE); - /* feed the watchdog for another 10s */ - writew(0x2, &wtd->feed); -} - -void hw_watchdog_init(void) -{ - return; -} diff --git a/board/technologic/ts4800/ts4800.h b/board/technologic/ts4800/ts4800.h deleted file mode 100644 index 25644f523a..0000000000 --- a/board/technologic/ts4800/ts4800.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Savoir-faire Linux Inc. - */ - -#ifndef _TS4800_H -#define _TS4800_H - -#define TS4800_SYSCON_BASE 0xb0010000 - -struct ts4800_wtd_regs { - u16 feed; -}; - -#endif diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig deleted file mode 100644 index ad025a3228..0000000000 --- a/board/ti/am3517crane/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_AM3517_CRANE - -config SYS_BOARD - default "am3517crane" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "am3517_crane" - -endif diff --git a/board/ti/am3517crane/MAINTAINERS b/board/ti/am3517crane/MAINTAINERS deleted file mode 100644 index cbc3213ec5..0000000000 --- a/board/ti/am3517crane/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -AM3517CRANE BOARD -M: Nagendra T S <nagendra@mistralsolutions.com> -S: Maintained -F: board/ti/am3517crane/ -F: include/configs/am3517_crane.h -F: configs/am3517_crane_defconfig diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile deleted file mode 100644 index eab0400323..0000000000 --- a/board/ti/am3517crane/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Author: Srinath R <srinath@mistralsolutions.com> -# -# Based on logicpd/am3517evm/Makefile -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd - -obj-y := am3517crane.o diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c deleted file mode 100644 index b1017d6c9b..0000000000 --- a/board/ti/am3517crane/am3517crane.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * am3517crane.c - board file for AM3517 CraneBoard - * - * Author: Srinath.R <srinath@mistralsolutions.com> - * - * Based on logicpd/am3517evm/am3517evm.c - * - * Copyright (C) 2011 Mistral Solutions Pvt Ltd - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include <i2c.h> -#include "am3517crane.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Init i2c, ethernet, etc... (done here so udelay works) - */ -int misc_init_r(void) -{ -#ifdef CONFIG_SYS_I2C_OMAP24XX - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_AM3517CRANE(); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h deleted file mode 100644 index 1e6dece14b..0000000000 --- a/board/ti/am3517crane/am3517crane.h +++ /dev/null @@ -1,343 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517crane.h - Header file for the AM3517 CraneBoard. - * - * Author: Srinath R <srinath@mistralsolutions.com> - * - * Based on logicpd/am3517evm/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions Pvt Ltd - */ - -#ifndef _AM3517CRANE_H_ -#define _AM3517CRANE_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "CraneBoard", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_AM3517CRANE()\ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CKE0), (M0))\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_CKE0), (M0))\ - MUX_VAL(CP(SDRC_CKE1), (M0))\ - /*sdrc_strben_dly0*/\ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\ - /*sdrc_strben_dly1*/\ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (M7))\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A6), (M7))\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A9), (M7))\ - MUX_VAL(CP(GPMC_A10), (M7))\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_NCS2), (M7))\ - MUX_VAL(CP(GPMC_NCS3), (M7))\ - MUX_VAL(CP(GPMC_NCS4), (M7))\ - MUX_VAL(CP(GPMC_NCS5), (M7))\ - MUX_VAL(CP(GPMC_NCS6), (M7))\ - MUX_VAL(CP(GPMC_NCS7), (M7))\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NBE1), (M7))\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT1), (M7))\ - MUX_VAL(CP(GPMC_WAIT2), (M7))\ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\ - /*MMC1*/\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\ - /*MMC2*/\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\ - /*McBSP*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\ - \ - MUX_VAL(CP(MCBSP2_FSX), (M7))\ - MUX_VAL(CP(MCBSP2_CLKX), (M7))\ - MUX_VAL(CP(MCBSP2_DR), (M7))\ - MUX_VAL(CP(MCBSP2_DX), (M7))\ - \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\ - \ - MUX_VAL(CP(MCBSP4_CLKX), (M7))\ - MUX_VAL(CP(MCBSP4_DR), (M7))\ - MUX_VAL(CP(MCBSP4_DX), (M7))\ - MUX_VAL(CP(MCBSP4_FSX), (M7))\ - /*UART*/\ - MUX_VAL(CP(UART1_TX), (M7))\ - MUX_VAL(CP(UART1_RTS), (M7))\ - MUX_VAL(CP(UART1_CTS), (M7))\ - MUX_VAL(CP(UART1_RX), (M7))\ - \ - MUX_VAL(CP(UART2_CTS), (M7))\ - MUX_VAL(CP(UART2_RTS), (M7))\ - MUX_VAL(CP(UART2_TX), (M7))\ - MUX_VAL(CP(UART2_RX), (M7))\ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\ - /*I2C 1, 2, 3*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ - /*McSPI*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\ - \ - MUX_VAL(CP(MCSPI2_CLK), (M7))\ - MUX_VAL(CP(MCSPI2_SIMO), (M7))\ - MUX_VAL(CP(MCSPI2_SOMI), (M7))\ - MUX_VAL(CP(MCSPI2_CS0), (M7))\ - MUX_VAL(CP(MCSPI2_CS1), (M7))\ - /*CCDC*/\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\ - /*RMII*/\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\ - MUX_VAL(CP(RMII_MDIO_CLK), (M0))\ - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_RXER), (PTD | M0))\ - MUX_VAL(CP(RMII_TXD0), (PTD | M0))\ - MUX_VAL(CP(RMII_TXD1), (PTD | M0))\ - MUX_VAL(CP(RMII_TXEN), (PTD | M0))\ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\ - /*HECC*/\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\ - /*HSUSB*/\ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\ - /*HDQ*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\ - /*Control and debug*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\ - /*SYS_nRESWARM*/\ - MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ - /*JTAG*/\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\ - /*ETK (ES2 onwards)*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D10_ES2), (M7))\ - MUX_VAL(CP(ETK_D11_ES2), (M7))\ - MUX_VAL(CP(ETK_D12_ES2), (M7))\ - MUX_VAL(CP(ETK_D13_ES2), (M7))\ - MUX_VAL(CP(ETK_D14_ES2), (M7))\ - MUX_VAL(CP(ETK_D15_ES2), (M7))\ - /*Die to Die*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\ - -#endif /* _AM3517CRANE_H_ */ diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig deleted file mode 100644 index a0389f8fa1..0000000000 --- a/board/varisys/cyrus/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040 - -config SYS_BOARD - default "cyrus" - -config SYS_VENDOR - default "varisys" - -config SYS_CONFIG_NAME - default "cyrus" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/varisys/cyrus/MAINTAINERS b/board/varisys/cyrus/MAINTAINERS deleted file mode 100644 index 53b4a886bd..0000000000 --- a/board/varisys/cyrus/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -Cyrus BOARD -M: Andy Fleming <afleming@gmail.com> -S: Maintained -F: board/varisys/cyrus/ -F: include/configs/cyrus.h -F: configs/Cyrus_P5020_defconfig -F: configs/Cyrus_P5040_defconfig diff --git a/board/varisys/cyrus/Makefile b/board/varisys/cyrus/Makefile deleted file mode 100644 index 15b3fb2964..0000000000 --- a/board/varisys/cyrus/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += $(BOARD).o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o -obj-y += eth.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/varisys/cyrus/README b/board/varisys/cyrus/README deleted file mode 100644 index 9595dcb7cc..0000000000 --- a/board/varisys/cyrus/README +++ /dev/null @@ -1,19 +0,0 @@ -Rebuilding u-boot for Cyrus - -The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig. - -They currently disable size optimization in order to avoid a relocation -bug in some versions of GCC. As the output size is a constant, the size -optimization is not currently important. - -Cyrus boots off a microSD card in a slot on the motherboard. This requires -that the u-boot is built for the Pre-Boot Loader on the P5020/P5040. -In order to reflash u-boot, you must download u-boot.pbl, then write it -onto the card. To do that from u-boot: - -> tftp 1000000 u-boot.pbl -> mmc write 1000000 8 672 - -If you want to do this via a card reader in linux: - -> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8 diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c deleted file mode 100644 index c5d34df777..0000000000 --- a/board/varisys/cyrus/cyrus.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Based on corenet_ds.c - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <fdt_support.h> -#include <image.h> -#include <init.h> -#include <netdev.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> -#include <pci.h> - -#include "cyrus.h" -#include "../common/eeprom.h" - -#define GPIO_OPENDRAIN 0x30000000 -#define GPIO_DIR 0x3c000004 -#define GPIO_INITIAL 0x30000000 -#define GPIO_VGA_SWITCH 0x00001000 - -int checkboard(void) -{ - printf("Board: CYRUS\n"); - - return 0; -} - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - - /* - * Only use DDR1_MCK0/3 and DDR2_MCK0/3 - * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce - * the noise introduced by these unterminated and unused clock pairs. - */ - setbits_be32(&gur->ddrclkdr, 0x001B001B); - - /* Set GPIO reset lines to open-drain, tristate */ - setbits_be32(&pgpio->gpdat, GPIO_INITIAL); - setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); - - /* Set GPIO Direction */ - setbits_be32(&pgpio->gpdir, GPIO_DIR); - - return 0; -} - -int board_early_init_r(void) -{ - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - out_be32(&lbc->lbcr, 0); - /* 1 clock LALE cycle */ - out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); - - set_liodns(); - -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_qbman_portals(); -#endif - print_lbc_regs(); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); -#endif - - return 0; -} - -int mac_read_from_eeprom(void) -{ - init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN); - - return mac_read_from_eeprom_common(); -} diff --git a/board/varisys/cyrus/cyrus.h b/board/varisys/cyrus/cyrus.h deleted file mode 100644 index d8f8d6c8ec..0000000000 --- a/board/varisys/cyrus/cyrus.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __CYRUS_H -#define __CYRUS_H - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c deleted file mode 100644 index 184948094d..0000000000 --- a/board/varisys/cyrus/ddr.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Based on corenet_ds ddr code - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 1050, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 1250, 4, 6, 0xff, 2, 0}, - {1, 1335, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (!fsl_use_spd()) - panic("Cyrus only supports using SPD for DRAM\n"); - - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c deleted file mode 100644 index bc681079e2..0000000000 --- a/board/varisys/cyrus/eth.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Author Adrian Cox - * Based somewhat on board/freescale/corenet_ds/eth_hydra.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#ifdef CONFIG_FMAN_ENET - -#define FIRST_PORT_ADDR 3 -#define SECOND_PORT_ADDR 7 - -#ifdef CONFIG_ARCH_P5040 -#define FIRST_PORT FM1_DTSEC5 -#define SECOND_PORT FM2_DTSEC5 -#else -#define FIRST_PORT FM1_DTSEC4 -#define SECOND_PORT FM1_DTSEC5 -#endif - -#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT) - -static void cyrus_phy_tuning(int phy) -{ - /* - * Enable RGMII delay on Tx and Rx for CPU port - */ - printf("Tuning PHY @ %d\n", phy); - - /* sets address 0x104 or reg 260 for writing */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104); - /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0); - /* sets address 0x105 or reg 261 for writing */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105); - /* writes to address 0x105 , RXD[3..0] to -0. */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); - /* sets address 0x106 or reg 261 for writing */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106); - /* writes to address 0x106 , TXD[3..0] to -0.84ns */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); - /* force re-negotiation */ - miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340); -} -#endif - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - unsigned int i; - - printf("Initializing Fman\n"); - - - /* Register the real 1G MDIO bus */ - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - - fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); - fm_info_set_mdio(FIRST_PORT, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); - fm_info_set_mdio(SECOND_PORT, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - - /* Never disable DTSEC1 - it controls MDIO */ - for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - if (!IS_VALID_PORT(i)) - fm_disable_port(i); - } - -#ifdef CONFIG_ARCH_P5040 - for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - if (!IS_VALID_PORT(i)) - fm_disable_port(i); - } -#endif - - cpu_eth_init(bis); - - cyrus_phy_tuning(FIRST_PORT_ADDR); - cyrus_phy_tuning(SECOND_PORT_ADDR); -#endif - - return pci_eth_init(bis); -} diff --git a/board/varisys/cyrus/law.c b/board/varisys/cyrus/law.c deleted file mode 100644 index 8b1b118b55..0000000000 --- a/board/varisys/cyrus/law.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Author: Adrian Cox - * Based on corenet_ds law files. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/varisys/cyrus/pbi.cfg b/board/varisys/cyrus/pbi.cfg deleted file mode 100644 index 9b330ddcc4..0000000000 --- a/board/varisys/cyrus/pbi.cfg +++ /dev/null @@ -1,35 +0,0 @@ -# -# Copyright 2012 Freescale Semiconductor, Inc. -# -# Refer docs/README.pblimage for more details about how-to configure -# and create PBL boot image -# -# SPDX-License-Identifier: GPL-2.0+ -# - -#PBI commands -#Initialize CPC1 as 1MB SRAM -09010000 00200400 -09138000 00000000 -091380c0 00000100 -09010100 00000000 -09010104 fff0000b -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff00000 -09000d08 81000013 -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/varisys/cyrus/pci.c b/board/varisys/cyrus/pci.c deleted file mode 100644 index 429c398cb4..0000000000 --- a/board/varisys/cyrus/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/varisys/cyrus/rcw_p5020_v2.cfg b/board/varisys/cyrus/rcw_p5020_v2.cfg deleted file mode 100644 index 9188080605..0000000000 --- a/board/varisys/cyrus/rcw_p5020_v2.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for Cyrus P5020 -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0c540000 00000000 1e1e0000 00000000 -44808c00 ff002000 68000000 45000000 -00000000 00000000 00000000 0003000f -a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/rcw_p5040.cfg b/board/varisys/cyrus/rcw_p5040.cfg deleted file mode 100644 index 5284481568..0000000000 --- a/board/varisys/cyrus/rcw_p5040.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for Cyrus P5040 -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -90e00000 00000000 acac9800 00440000 -44808c00 ff29a000 68000000 61000000 -00000000 00000000 00000000 0003000f -a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/tlb.c b/board/varisys/cyrus/tlb.c deleted file mode 100644 index b1af3e04d6..0000000000 --- a/board/varisys/cyrus/tlb.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Author: Adrian Cox - * Based on corenet_ds tlb code - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* Local Bus */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_64K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig deleted file mode 100644 index a488ad8fb5..0000000000 --- a/configs/Cyrus_P5020_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_CYRUS_P5020=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_CONSOLE_MUX=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig deleted file mode 100644 index 476d63bab2..0000000000 --- a/configs/Cyrus_P5040_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_CYRUS_P5040=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_CONSOLE_MUX=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig deleted file mode 100644 index 74eccf5b6b..0000000000 --- a/configs/MPC8308RDB_defconfig +++ /dev/null @@ -1,152 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8308RDB=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="NAND" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW2=y -CONFIG_LBLAW2_BASE=0xF0000000 -CONFIG_LBLAW2_NAME="VSC7385" -CONFIG_LBLAW2_LENGTH_128_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="NAND" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_ERRORCHECKING_BOTH=y -CONFIG_BR1_MACHINE_FCM=y -CONFIG_OR1_SCY_1=y -CONFIG_OR1_CSCT_8_CYCLE=y -CONFIG_OR1_CST_ONE_CLOCK=y -CONFIG_OR1_CHT_TWO_CLOCK=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="VSC7385_BASE" -CONFIG_BR2_OR2_BASE=0xF0000000 -CONFIG_OR2_AM_128_KBYTES=y -CONFIG_OR2_SCY_15=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_XACS_EXTENDED=y -CONFIG_OR2_SETA_EXTERNAL=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_OR2_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y -CONFIG_SICR_GPIO_A_TSEC2=y -CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=5 -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE090000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig deleted file mode 100644 index 92f2093bb6..0000000000 --- a/configs/MPC8349ITXGP_defconfig +++ /dev/null @@ -1,189 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_CLK_FREQ=66666666 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349ITX=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="PCI1_MEM" -CONFIG_BAT1_BASE=0x80000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="PCI1_MMIO" -CONFIG_BAT2_BASE=0x90000000 -CONFIG_BAT2_LENGTH_256_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="PCI2_MEM" -CONFIG_BAT3_BASE=0xA0000000 -CONFIG_BAT3_LENGTH_256_MBYTES=y -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="PCI2_MMIO" -CONFIG_BAT4_BASE=0xB0000000 -CONFIG_BAT4_LENGTH_256_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_INHIBITED=y -CONFIG_BAT4_ICACHE_GUARDED=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_16_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="VSC7385" -CONFIG_LBLAW1_LENGTH_128_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xF0000000 -CONFIG_LBLAW3_NAME="CF" -CONFIG_LBLAW3_LENGTH_64_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_16_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="VSC7385" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_AM_128_KBYTES=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_SETA_EXTERNAL=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="LED" -CONFIG_BR2_OR2_BASE=0xF9000000 -CONFIG_OR2_AM_2_MBYTES=y -CONFIG_OR2_SCY_9=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR2_XACS_EXTENDED=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_OR2_EHTR_8_CYCLE=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="CF" -CONFIG_BR3_OR3_BASE=0xF0000000 -CONFIG_BR3_PORTSIZE_16BIT=y -CONFIG_BR3_MACHINE_UPMA=y -CONFIG_OR3_BI_BURSTINHIBIT=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" -CONFIG_BOOTDELAY=6 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200" -CONFIG_MISC_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig deleted file mode 100644 index cf1e90d619..0000000000 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ /dev/null @@ -1,197 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_CLK_FREQ=66666666 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349ITX=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="PCI1_MEM" -CONFIG_BAT1_BASE=0x80000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="PCI1_MMIO" -CONFIG_BAT2_BASE=0x90000000 -CONFIG_BAT2_LENGTH_256_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="PCI2_MEM" -CONFIG_BAT3_BASE=0xA0000000 -CONFIG_BAT3_LENGTH_256_MBYTES=y -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="PCI2_MMIO" -CONFIG_BAT4_BASE=0xB0000000 -CONFIG_BAT4_LENGTH_256_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_INHIBITED=y -CONFIG_BAT4_ICACHE_GUARDED=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_16_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="VSC7385" -CONFIG_LBLAW1_LENGTH_128_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xF0000000 -CONFIG_LBLAW3_NAME="CF" -CONFIG_LBLAW3_LENGTH_64_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_16_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="VSC7385" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_AM_128_KBYTES=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_SETA_EXTERNAL=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="LED" -CONFIG_BR2_OR2_BASE=0xF9000000 -CONFIG_OR2_AM_2_MBYTES=y -CONFIG_OR2_SCY_9=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR2_XACS_EXTENDED=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_OR2_EHTR_8_CYCLE=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="CF" -CONFIG_BR3_OR3_BASE=0xF0000000 -CONFIG_BR3_PORTSIZE_16BIT=y -CONFIG_BR3_MACHINE_UPMA=y -CONFIG_OR3_BI_BURSTINHIBIT=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" -CONFIG_MISC_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="MPC8349E-mITX> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_SATA_SIL3114=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig deleted file mode 100644 index 733e5d3599..0000000000 --- a/configs/MPC8349ITX_defconfig +++ /dev/null @@ -1,196 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFEF00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_CLK_FREQ=66666666 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349ITX=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="PCI1_MEM" -CONFIG_BAT1_BASE=0x80000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="PCI1_MMIO" -CONFIG_BAT2_BASE=0x90000000 -CONFIG_BAT2_LENGTH_256_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="PCI2_MEM" -CONFIG_BAT3_BASE=0xA0000000 -CONFIG_BAT3_LENGTH_256_MBYTES=y -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="PCI2_MMIO" -CONFIG_BAT4_BASE=0xB0000000 -CONFIG_BAT4_LENGTH_256_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_INHIBITED=y -CONFIG_BAT4_ICACHE_GUARDED=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_16_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="VSC7385" -CONFIG_LBLAW1_LENGTH_128_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xF0000000 -CONFIG_LBLAW3_NAME="CF" -CONFIG_LBLAW3_LENGTH_64_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_16_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="VSC7385" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_AM_128_KBYTES=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_SETA_EXTERNAL=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="LED" -CONFIG_BR2_OR2_BASE=0xF9000000 -CONFIG_OR2_AM_2_MBYTES=y -CONFIG_OR2_SCY_9=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR2_XACS_EXTENDED=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_OR2_EHTR_8_CYCLE=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="CF" -CONFIG_BR3_OR3_BASE=0xF0000000 -CONFIG_BR3_PORTSIZE_16BIT=y -CONFIG_BR3_MACHINE_UPMA=y -CONFIG_OR3_BI_BURSTINHIBIT=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" -CONFIG_MISC_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="MPC8349E-mITX> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFEF80000 -CONFIG_SATA_SIL3114=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig deleted file mode 100644 index 7e2e0e4b3b..0000000000 --- a/configs/MPC837XEMDS_HOST_defconfig +++ /dev/null @@ -1,190 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="FLASH" -CONFIG_BAT4_BASE=0xFE000000 -CONFIG_BAT4_LENGTH_32_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="STACK_IN_DCACHE" -CONFIG_BAT5_BASE=0xE6000000 -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="PCI_MEM" -CONFIG_BAT6_BASE=0x80000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_BAT7=y -CONFIG_BAT7_NAME="PCI_MMIO" -CONFIG_BAT7_BASE=0x90000000 -CONFIG_BAT7_LENGTH_256_MBYTES=y -CONFIG_BAT7_ACCESS_RW=y -CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y -CONFIG_BAT7_DCACHE_INHIBITED=y -CONFIG_BAT7_DCACHE_GUARDED=y -CONFIG_BAT7_USER_MODE_VALID=y -CONFIG_BAT7_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig deleted file mode 100644 index 3ba15a1eb7..0000000000 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ /dev/null @@ -1,143 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" -CONFIG_BOOTDELAY=6 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig deleted file mode 100644 index 5ca8760b36..0000000000 --- a/configs/MPC837XEMDS_defconfig +++ /dev/null @@ -1,166 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="FLASH" -CONFIG_BAT4_BASE=0xFE000000 -CONFIG_BAT4_LENGTH_32_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="STACK_IN_DCACHE" -CONFIG_BAT5_BASE=0xE6000000 -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig deleted file mode 100644 index b98e7e0653..0000000000 --- a/configs/T2081QDS_NAND_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2081QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig deleted file mode 100644 index 8244f38ad2..0000000000 --- a/configs/T2081QDS_SDCARD_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2081QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig deleted file mode 100644 index 903281d767..0000000000 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2081QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index 30b7bac838..0000000000 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2081QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig deleted file mode 100644 index 682d78c000..0000000000 --- a/configs/T2081QDS_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2081QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig deleted file mode 100644 index 94d5598bee..0000000000 --- a/configs/am3517_crane_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_TEXT_BASE=0x40200800 -CONFIG_TARGET_AM3517_CRANE=y -CONFIG_EMIF4=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=10 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -CONFIG_SYS_PROMPT="AM3517_CRANE # " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_HCD=y -CONFIG_USB_AM35X=y -CONFIG_USB_STORAGE=y -# CONFIG_REGEX is not set diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index d020bb0e46..35f90274a2 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -69,7 +70,6 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y -# CONFIG_BLK is not set CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig deleted file mode 100644 index edb8c2b477..0000000000 --- a/configs/apf27_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SPL_USE_ARCH_MEMCPY is not set -CONFIG_TARGET_APF27=y -CONFIG_SYS_TEXT_BASE=0xA0000800 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xA0000000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_IDENT_STRING=" apf27 patch 3.10" -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="run check_flash check_env;" -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="BIOS> " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_DNS2=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DNS=y -CONFIG_CMD_BSP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_SPARTAN3=y -CONFIG_MXC_GPIO=y -CONFIG_MMC_MXC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig deleted file mode 100644 index fd3094266a..0000000000 --- a/configs/bcm11130_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCM28155_AP=y -CONFIG_SYS_TEXT_BASE=0xae000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x2340000 -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_KONA=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Broadcom Corporation" -CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y -CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig deleted file mode 100644 index 441a55bf09..0000000000 --- a/configs/bcm11130_nand_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCM28155_AP=y -CONFIG_SYS_TEXT_BASE=0xae000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x2340000 -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_KONA=y -CONFIG_MTD=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Broadcom Corporation" -CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y -CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig deleted file mode 100644 index 021de69799..0000000000 --- a/configs/bcm23550_w1d_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_ICACHE_OFF=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -CONFIG_TARGET_BCM23550_W1D=y -CONFIG_SYS_TEXT_BASE=0x9f000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x2340000 -# CONFIG_ANDROID_BOOT_IMAGE is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x80000000 -CONFIG_FASTBOOT_BUF_SIZE=0x1D000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_KONA=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Broadcom Corporation" -CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 -CONFIG_USB_GADGET_BCM_UDC_OTG_PHY=y -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig deleted file mode 100644 index b4b9d3e261..0000000000 --- a/configs/bcm28155_ap_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -CONFIG_TARGET_BCM28155_AP=y -CONFIG_SYS_TEXT_BASE=0xae000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x2340000 -# CONFIG_ANDROID_BOOT_IMAGE is not set -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x80000000 -CONFIG_FASTBOOT_BUF_SIZE=0x7FF00000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_KONA=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Broadcom Corporation" -CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 -CONFIG_USB_GADGET_BCM_UDC_OTG_PHY=y -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig deleted file mode 100644 index e1e854f4fa..0000000000 --- a/configs/bcm28155_w1d_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -CONFIG_TARGET_BCM28155_AP=y -CONFIG_SYS_TEXT_BASE=0xae000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x2340000 -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_KONA=y -CONFIG_BCM_SF2_ETH=y -CONFIG_BCM_SF2_ETH_GMAC=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Broadcom Corporation" -CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y -CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig deleted file mode 100644 index b24edc36d7..0000000000 --- a/configs/bcm911360_entphn-ns_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig deleted file mode 100644 index daeb8691a6..0000000000 --- a/configs/bcm911360_entphn_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig deleted file mode 100644 index 7eda9a38e2..0000000000 --- a/configs/bcm911360k_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig deleted file mode 100644 index 06af5ce265..0000000000 --- a/configs/bcm958300k-ns_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig deleted file mode 100644 index 7eda9a38e2..0000000000 --- a/configs/bcm958300k_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig deleted file mode 100644 index 7eda9a38e2..0000000000 --- a/configs/bcm958305k_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMCYGNUS=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_PHY_BROADCOM=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig deleted file mode 100644 index 690a613d8d..0000000000 --- a/configs/bcm958622hr_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMNSP=y -CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" -# CONFIG_AUTOBOOT is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MX_CYCLIC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_HASH=y -CONFIG_HASH_VERIFY=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig deleted file mode 100644 index 74070f555b..0000000000 --- a/configs/bcm958712k_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMNS2=y -CONFIG_SYS_TEXT_BASE=0x85000000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_IDENT_STRING=" Broadcom Northstar 2" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=5 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SYS_PROMPT="u-boot> " -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_CONS_INDEX=4 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig deleted file mode 100644 index 26f74662f8..0000000000 --- a/configs/cgtqmx6eval_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 -CONFIG_MX6QDL=y -CONFIG_TARGET_CGTQMX6EVAL=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Congatec" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig deleted file mode 100644 index 41785d09d0..0000000000 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_IDENT_STRING=" controlcenterd 0.01" -CONFIG_MPC85xx=y -CONFIG_TARGET_CONTROLCENTERD=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP" -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_TPM=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_SATA=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_TPM_AUTH_SESSIONS=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_ADDR_MAP=y -CONFIG_TPM=y -CONFIG_OF_LIBFDT=y diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig deleted file mode 100644 index 777f5aee41..0000000000 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_IDENT_STRING=" controlcenterd 0.01" -CONFIG_MPC85xx=y -CONFIG_TARGET_CONTROLCENTERD=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_TPM=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_SATA=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_TPM_AUTH_SESSIONS=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_ADDR_MAP=y -CONFIG_TPM=y -CONFIG_OF_LIBFDT=y diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig deleted file mode 100644 index 9fc0f60d2d..0000000000 --- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf8fc0000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01" -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_CONTROLCENTERD=y -CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" -CONFIG_BOOTDELAY=-2 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -# CONFIG_MISC_INIT_R is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -# CONFIG_CMD_BOOTM is not set -CONFIG_CMD_EEPROM=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_TPM=y -# CONFIG_CMD_IRQ is not set -CONFIG_DOS_PARTITION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -# CONFIG_PCI is not set -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_TPM_AUTH_SESSIONS=y -CONFIG_TPM=y -CONFIG_SHA1=y diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig deleted file mode 100644 index 9ae0905d3f..0000000000 --- a/configs/controlcenterd_TRAILBLAZER_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf8fc0000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01" -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_CONTROLCENTERD=y -CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" -CONFIG_BOOTDELAY=-2 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -# CONFIG_MISC_INIT_R is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -# CONFIG_CMD_BOOTM is not set -CONFIG_CMD_EEPROM=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_TPM=y -# CONFIG_CMD_IRQ is not set -CONFIG_DOS_PARTITION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -# CONFIG_PCI is not set -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_TPM_AUTH_SESSIONS=y -CONFIG_TPM=y -CONFIG_SHA1=y diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig deleted file mode 100644 index f7b6bc6ded..0000000000 --- a/configs/dms-ba16-1g_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_ADVANTECH_DMS_BA16=y -CONFIG_SYS_DDR_1G=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOOTDELAY=1 -CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Advantech" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig deleted file mode 100644 index c708087454..0000000000 --- a/configs/dms-ba16_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_ADVANTECH_DMS_BA16=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOOTDELAY=1 -CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Advantech" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index a5fe9cd331..493c802d52 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -36,7 +36,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 2c27726fcd..b4dedc9e59 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -34,7 +34,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_ENV_ADDR=0x100000 CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index e412e3f593..77c094b766 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -30,7 +30,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_ENV_ADDR=0x3D0000 CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 916775e9ed..0aacb35e44 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xFFF84000 CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index b271822dcb..6e3e6325e9 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -37,7 +37,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index f7e934bcf8..a3fe98cabf 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig deleted file mode 100644 index 5ac6de62ae..0000000000 --- a/configs/hrcon_defconfig +++ /dev/null @@ -1,147 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" hrcon 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_HRCON=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig deleted file mode 100644 index ca938940e9..0000000000 --- a/configs/hrcon_dh_defconfig +++ /dev/null @@ -1,145 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" hrcon dh 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_HRCON=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" -CONFIG_BOOTDELAY=5 -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 1fbf03442d..57ccfe71fb 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig deleted file mode 100644 index 5686b5a1b9..0000000000 --- a/configs/kc1_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_TEXT_BASE=0x40300000 -CONFIG_OMAP44XX=y -CONFIG_TARGET_KC1=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2 -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SYS_PROMPT="kc1 # " -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x2000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_SYS_OMAP24_I2C_SPEED=400000 -CONFIG_MMC_OMAP_HS=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_OF_LIBFDT=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 8f6ca820a2..214a2bb9e7 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -41,7 +41,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_SCSI_AHCI=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig deleted file mode 100644 index 680f342b11..0000000000 --- a/configs/mx53evk_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX5=y -CONFIG_SYS_TEXT_BASE=0x77800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_TARGET_MX53EVK=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig deleted file mode 100644 index 57da844e8d..0000000000 --- a/configs/mx6dlarm2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig deleted file mode 100644 index c1f4fed2cb..0000000000 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig deleted file mode 100644 index 180d5f9baa..0000000000 --- a/configs/mx6qarm2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6Q=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,DDR_MB=2048" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig deleted file mode 100644 index d481f686be..0000000000 --- a/configs/mx6qarm2_lpddr2_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6Q=y -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_LPDDR2,DDR_MB=512" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index e89b6b9e14..3e031604ee 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_MVSATA_IDE=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index bec1707ddc..e4cf1c470e 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig deleted file mode 100644 index 393513ac07..0000000000 --- a/configs/omap3_ha_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_TEXT_BASE=0x40200800 -CONFIG_TARGET_TAO3530=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" -CONFIG_BOOTDELAY=3 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig deleted file mode 100644 index 4f8a524c1d..0000000000 --- a/configs/ot1200_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_OT1200=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_CMD_PCA953X=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=25000000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig deleted file mode 100644 index ec3bf90306..0000000000 --- a/configs/ot1200_spl_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_OT1200=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_CMD_PCA953X=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=25000000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig deleted file mode 100644 index fa8ed31e5b..0000000000 --- a/configs/pfla02_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 -CONFIG_MX6QDL=y -CONFIG_TARGET_PFLA02=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x110000 -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(nand);spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)" -CONFIG_CMD_UBI=y -# CONFIG_SPL_PARTITION_UUIDS is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_OF_LIBFDT=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig deleted file mode 100644 index 915c2ba812..0000000000 --- a/configs/picosam9g45_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_PICOSAM9G45=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot> " -# CONFIG_CMD_BDI is not set -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_AT91_GPIO=y -CONFIG_ATMEL_USART=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_WDT=y -CONFIG_WDT_AT91=y -CONFIG_OF_LIBFDT=y diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig deleted file mode 100644 index 47c38b8d34..0000000000 --- a/configs/platinum_picon_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x1000000 -CONFIG_MX6DL=y -CONFIG_TARGET_PLATINUM_PICON=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x1080000 -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_DMA=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="picon > " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig deleted file mode 100644 index 3ceb4e1020..0000000000 --- a/configs/platinum_titanium_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x1000000 -CONFIG_MX6Q=y -CONFIG_TARGET_PLATINUM_TITANIUM=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x1080000 -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_DMA=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="titanium > " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig deleted file mode 100644 index 656f63f76a..0000000000 --- a/configs/s32v234evb_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_S32V234EVB=y -CONFIG_SYS_TEXT_BASE=0x3E800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc7c00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_CACHE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_USDHC=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LINFLEXUART=y -CONFIG_OF_LIBFDT=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig deleted file mode 100644 index 69fc1b8b85..0000000000 --- a/configs/sansa_fuze_plus_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x40400000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_SANSA_FUZE_PLUS=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig deleted file mode 100644 index 6b50170951..0000000000 --- a/configs/sc_sps_1_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_SC_SPS_1=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig deleted file mode 100644 index cc56b2e2b6..0000000000 --- a/configs/secomx6quq7_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_MX6Q=y -CONFIG_TARGET_SECOMX6=y -CONFIG_SECOMX6_UQ7=y -CONFIG_SECOMX6Q=y -CONFIG_SECOMX6_2GB=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_OF_LIBFDT=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig deleted file mode 100644 index 0ec9e27810..0000000000 --- a/configs/strider_con_defconfig +++ /dev/null @@ -1,146 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" strider con 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_STRIDER=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig deleted file mode 100644 index 304f9caca7..0000000000 --- a/configs/strider_con_dp_defconfig +++ /dev/null @@ -1,146 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" strider con dp 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_STRIDER=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP" -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig deleted file mode 100644 index d1c388cfb8..0000000000 --- a/configs/strider_cpu_defconfig +++ /dev/null @@ -1,146 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" strider cpu 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_STRIDER=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig deleted file mode 100644 index 61c6240e94..0000000000 --- a/configs/strider_cpu_dp_defconfig +++ /dev/null @@ -1,146 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_SYS_MEMTEST_START=0x00001000 -CONFIG_SYS_MEMTEST_END=0x07f00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_IDENT_STRING=" strider cpu dp 0.01" -CONFIG_SYS_CLK_FREQ=33333333 -CONFIG_MPC83xx=y -CONFIG_TARGET_STRIDER=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="DDR" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="FPGA0" -CONFIG_LBLAW1_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_SICR_IEEE1588_A_GPIO=y -CONFIG_SICR_GTM_GPIO=y -CONFIG_SICR_ETSEC2_GPIO=y -CONFIG_SICR_GPIOSEL_IEEE1588=y -CONFIG_SICR_TMSOBI1_2_5_V=y -CONFIG_SICR_TMSOBI2_2_5_V=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_CMD_IOLOOP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP" -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_FPGAD=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE070000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig deleted file mode 100644 index 45d639e5e3..0000000000 --- a/configs/tao3530_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_TEXT_BASE=0x40200800 -CONFIG_TARGET_TAO3530=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="TAO-3530 # " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig deleted file mode 100644 index ffb091fa2d..0000000000 --- a/configs/titanium_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x1000000 -CONFIG_MX6Q=y -CONFIG_TARGET_TITANIUM=y -CONFIG_ENV_OFFSET_REDUND=0x1080000 -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Titanium > " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig deleted file mode 100644 index bae00c688b..0000000000 --- a/configs/tqma6s_wru4_mmc_defconfig +++ /dev/null @@ -1,82 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_MX6S=y -CONFIG_TARGET_TQMA6=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_WRU4=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" -CONFIG_DEFAULT_FDT_FILE="imx6s-wru4.dtb" -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_DM is not set -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_I2C_MXC=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=0 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS1=y -CONFIG_LED_STATUS_BIT1=1 -CONFIG_LED_STATUS_STATE1=2 -CONFIG_LED_STATUS2=y -CONFIG_LED_STATUS_BIT2=2 -CONFIG_LED_STATUS_STATE2=2 -CONFIG_LED_STATUS3=y -CONFIG_LED_STATUS_BIT3=3 -CONFIG_LED_STATUS_STATE3=2 -CONFIG_LED_STATUS4=y -CONFIG_LED_STATUS_BIT4=4 -CONFIG_LED_STATUS_STATE4=2 -CONFIG_LED_STATUS5=y -CONFIG_LED_STATUS_BIT5=5 -CONFIG_LED_STATUS_STATE5=2 -CONFIG_LED_STATUS_CMD=y -CONFIG_PCA9551_LED=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig deleted file mode 100644 index 6e511a1b13..0000000000 --- a/configs/tricorder_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x120000 -CONFIG_SPL_TEXT_BASE=0x40200000 -CONFIG_TARGET_TRICORDER=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2A0000 -CONFIG_BOOTDELAY=0 -CONFIG_SILENT_CONSOLE=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="OMAP3 Tricorder # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS1=y -CONFIG_LED_STATUS_BIT1=2 -CONFIG_LED_STATUS_STATE1=2 -CONFIG_LED_STATUS2=y -CONFIG_LED_STATUS_BIT2=4 -CONFIG_LED_STATUS_STATE2=2 -CONFIG_LED_STATUS_CMD=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_BCH=y -CONFIG_PANIC_HANG=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig deleted file mode 100644 index 0ade2d35ca..0000000000 --- a/configs/tricorder_flash_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x40200000 -CONFIG_TARGET_TRICORDER=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" -CONFIG_BOOTDELAY=0 -CONFIG_SILENT_CONSOLE=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_IMI is not set -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS1=y -CONFIG_LED_STATUS_BIT1=2 -CONFIG_LED_STATUS_STATE1=2 -CONFIG_LED_STATUS2=y -CONFIG_LED_STATUS_BIT2=4 -CONFIG_LED_STATUS_STATE2=2 -CONFIG_LED_STATUS_CMD=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_BCH=y -CONFIG_PANIC_HANG=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig deleted file mode 100644 index 806cbc6684..0000000000 --- a/configs/ts4600_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_TS4600=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MMC=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig deleted file mode 100644 index df935b6102..0000000000 --- a/configs/ts4800_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX5=y -CONFIG_SYS_TEXT_BASE=0x90008000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_TARGET_TS4800=y -# CONFIG_CMD_BMODE is not set -CONFIG_BOOTDELAY=1 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig deleted file mode 100644 index e8e401b179..0000000000 --- a/configs/vexpress_ca15_tc2_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA15_TC2=y -CONFIG_SYS_TEXT_BASE=0x80800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFF80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x1a000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig deleted file mode 100644 index 88027b940b..0000000000 --- a/configs/vexpress_ca5x2_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA5X2=y -CONFIG_SYS_TEXT_BASE=0x80800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFF80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x1a000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig deleted file mode 100644 index 7b148450e5..0000000000 --- a/configs/vexpress_ca9x4_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA9X4=y -CONFIG_SYS_TEXT_BASE=0x60800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x47F80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x4e000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig deleted file mode 100644 index ca47edf321..0000000000 --- a/configs/wb45n_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_WB45N=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x20000000 -CONFIG_SYS_MEMTEST_END=0x23e00000 -CONFIG_ENV_OFFSET=0xA0000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xC0000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw noinitrd mem=64M rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_AT91_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_ATMEL_USART=y -CONFIG_LZMA=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig deleted file mode 100644 index 0ffc5b4d73..0000000000 --- a/configs/wb50n_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_WB50N=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x21000000 -CONFIG_SYS_MEMTEST_END=0x22000000 -CONFIG_ENV_OFFSET=0xA0000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xC0000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_AT91_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_PMECC_CAP=8 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ATMEL_USART=y -CONFIG_LZMA=y -CONFIG_OF_LIBFDT=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig deleted file mode 100644 index c49319c3c2..0000000000 --- a/configs/xfi3_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_XFI3=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig deleted file mode 100644 index b77bf9a470..0000000000 --- a/configs/xpress_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_MX6UL=y -CONFIG_TARGET_XPRESS=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig deleted file mode 100644 index aee059dea0..0000000000 --- a/configs/xpress_spl_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x90000000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_MX6UL=y -CONFIG_TARGET_XPRESS=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig deleted file mode 100644 index 321a9351d2..0000000000 --- a/configs/zc5202_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10800000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_ZC5202=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MV88E6352_SWITCH=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_IMX_THERMAL=y -CONFIG_OF_LIBFDT=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig deleted file mode 100644 index ed6978e32c..0000000000 --- a/configs/zc5601_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MEMTEST_END=0x10800000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 -CONFIG_MX6Q=y -CONFIG_TARGET_ZC5601=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_IMX_THERMAL=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index f2f8275aec..9ff4b8736c 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -62,6 +62,7 @@ config DWC_AHCI config DWC_AHSATA bool "Enable DWC AHSATA driver support" select LIBATA + depends on BLK help Enable this driver to support the DWC AHSATA SATA controller found in i.MX5 and i.MX6 SoCs. @@ -82,12 +83,6 @@ config FSL_SATA Enable this driver to support the SATA controller found in some Freescale PowerPC SoCs. -config MVSATA_IDE - bool "Enable Marvell SATA controller driver support via IDE interface" - help - Enable this driver to support the SATA controller found in - some Marvell SoCs, running in IDE compatibility mode using PIO. - config SATA_MV bool "Enable Marvell SATA controller driver support" select AHCI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 98fb480700..4811b2f82c 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o obj-$(CONFIG_LIBATA) += libata.o -obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o obj-$(CONFIG_SATA_MV) += sata_mv.o diff --git a/drivers/ata/mvsata_ide.c b/drivers/ata/mvsata_ide.c deleted file mode 100644 index 41f9a91617..0000000000 --- a/drivers/ata/mvsata_ide.c +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net> - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/delay.h> - -#if defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> -#elif defined(CONFIG_ARCH_KIRKWOOD) -#include <asm/arch/soc.h> -#elif defined(CONFIG_ARCH_MVEBU) -#include <linux/mbus.h> -#endif - -/* SATA port registers */ -struct mvsata_port_registers { - u32 reserved0[10]; - u32 edma_cmd; - u32 reserved1[181]; - /* offset 0x300 : ATA Interface registers */ - u32 sstatus; - u32 serror; - u32 scontrol; - u32 ltmode; - u32 phymode3; - u32 phymode4; - u32 reserved2[5]; - u32 phymode1; - u32 phymode2; - u32 bist_cr; - u32 bist_dw1; - u32 bist_dw2; - u32 serrorintrmask; -}; - -/* - * Sanity checks: - * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR. - * - for ide_preinit to make sense, we need at least one of - * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET; - * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT. - * Fail with an explanation message if these conditions are not met. - * This is particularly important for CONFIG_IDE_PREINIT, because - * its lack would not cause a build error. - */ - -#if !defined(CONFIG_SYS_ATA_BASE_ADDR) -#error CONFIG_SYS_ATA_BASE_ADDR must be defined -#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \ - && !defined(CONFIG_SYS_ATA_IDE1_OFFSET) -#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \ - must be defined -#elif !defined(CONFIG_IDE_PREINIT) -#error CONFIG_IDE_PREINIT must be defined -#endif - -/* - * Masks and values for SControl DETection and Interface Power Management, - * and for SStatus DETection. - */ - -#define MVSATA_EDMA_CMD_ATA_RST 0x00000004 -#define MVSATA_SCONTROL_DET_MASK 0x0000000F -#define MVSATA_SCONTROL_DET_NONE 0x00000000 -#define MVSATA_SCONTROL_DET_INIT 0x00000001 -#define MVSATA_SCONTROL_IPM_MASK 0x00000F00 -#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300 -#define MVSATA_SCONTROL_MASK \ - (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK) -#define MVSATA_PORT_INIT \ - (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) -#define MVSATA_PORT_USE \ - (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) -#define MVSATA_SSTATUS_DET_MASK 0x0000000F -#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 - -/* - * Status codes to return to client callers. Currently, callers ignore - * exact value and only care for zero or nonzero, so no need to make this - * public, it is only #define'd for clarity. - * If/when standard negative codes are implemented in U-Boot, then these - * #defines should be moved to, or replaced by ones from, the common list - * of status codes. - */ - -#define MVSATA_STATUS_OK 0 -#define MVSATA_STATUS_TIMEOUT -1 - -/* - * Registers for SATA MBUS memory windows - */ - -#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) -#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) - -/* - * Initialize SATA memory windows for Armada XP - */ - -#ifdef CONFIG_ARCH_MVEBU -static void mvsata_ide_conf_mbus_windows(void) -{ - const struct mbus_dram_target_info *dram; - int i; - - dram = mvebu_mbus_dram_info(); - - /* Disable windows, Set Size/Base to 0 */ - for (i = 0; i < 4; i++) { - writel(0, MVSATA_WIN_CONTROL(i)); - writel(0, MVSATA_WIN_BASE(i)); - } - - for (i = 0; i < dram->num_cs; i++) { - const struct mbus_dram_window *cs = dram->cs + i; - writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1, - MVSATA_WIN_CONTROL(i)); - writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); - } -} -#endif - -/* - * Initialize one MVSATAHC port: set SControl's IPM to "always active" - * and DET to "reset", then wait for SStatus's DET to become "device and - * comm ok" (or time out after 50 us if no device), then set SControl's - * DET back to "no action". - */ - -static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) -{ - u32 control; - u32 status; - u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ - - /* Hard reset */ - writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd); - udelay(25); /* taken from original marvell port */ - writel(0, &port->edma_cmd); - - /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ - control = readl(&port->scontrol); - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; - writel(control, &port->scontrol); - /* Toggle control DET back to 0 (normal operation) */ - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; - writel(control, &port->scontrol); - /* wait for status DET to become 3 (device and communication OK) */ - while (--timeleft) { - status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; - if (status == MVSATA_SSTATUS_DET_DEVCOMM) - break; - udelay(1); - } - /* return success or time-out error depending on time left */ - if (!timeleft) - return MVSATA_STATUS_TIMEOUT; - return MVSATA_STATUS_OK; -} - -/* - * ide_preinit() will be called by ide_init in cmd_ide.c and will - * reset the MVSTATHC ports needed by the board. - */ - -int ide_preinit(void) -{ - int ret = MVSATA_STATUS_TIMEOUT; - int status; - -#ifdef CONFIG_ARCH_MVEBU - mvsata_ide_conf_mbus_windows(); -#endif - - /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ -#if defined(CONFIG_SYS_ATA_IDE0_OFFSET) - status = mvsata_ide_initialize_port( - (struct mvsata_port_registers *) - (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); - if (status == MVSATA_STATUS_OK) - ret = MVSATA_STATUS_OK; -#endif - /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ -#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) - status = mvsata_ide_initialize_port( - (struct mvsata_port_registers *) - (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); - if (status == MVSATA_STATUS_OK) - ret = MVSATA_STATUS_OK; -#endif - /* Return success if at least one port initialization succeeded */ - return ret; -} diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 5f62489a90..8b480dfd69 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -44,7 +44,6 @@ config SYS_NUM_DDR_CTLRS ARCH_MPC8572 || \ ARCH_MPC8641 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 || \ ARCH_LX2160A || \ ARCH_LX2162A || \ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1844941eb2..57a4efb88e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -479,7 +479,7 @@ config SYS_I2C_UNIPHIER_F config SYS_I2C_VERSATILE bool "Arm Ltd Versatile I2C bus driver" - depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) + depends on DM_I2C && TARGET_VEXPRESS64_JUNO help Add support for the Arm Ltd Versatile Express I2C driver. The I2C host controller is present in the development boards manufactured by Arm Ltd. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 197aa82040..d862d1e202 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -804,7 +804,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index cf062fad4d..54f7b81624 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -721,13 +721,11 @@ config SYS_DPAA_QBMAN ARCH_T1040 || \ ARCH_T1042 || \ ARCH_T2080 || \ - ARCH_T2081 || \ ARCH_T4240 || \ ARCH_T4160 || \ ARCH_P4080 || \ ARCH_P3041 || \ ARCH_P5040 || \ - ARCH_P5020 || \ ARCH_LS1043A || \ ARCH_LS1046A help diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index e10db710e6..b4ede61113 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -20,14 +20,12 @@ obj-$(CONFIG_ARCH_P1023) += p1023.o obj-$(CONFIG_ARCH_P2041) += p5020.o obj-$(CONFIG_ARCH_P3041) += p5020.o obj-$(CONFIG_ARCH_P4080) += p4080.o -obj-$(CONFIG_ARCH_P5020) += p5020.o obj-$(CONFIG_ARCH_P5040) += p5040.o obj-$(CONFIG_ARCH_T1040) += t1040.o obj-$(CONFIG_ARCH_T1042) += t1040.o obj-$(CONFIG_ARCH_T1023) += t1024.o obj-$(CONFIG_ARCH_T1024) += t1024.o obj-$(CONFIG_ARCH_T2080) += t2080.o -obj-$(CONFIG_ARCH_T2081) += t2080.o obj-$(CONFIG_ARCH_T4240) += t4240.o obj-$(CONFIG_ARCH_T4160) += t4240.o obj-$(CONFIG_ARCH_B4420) += b4860.o diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig index 864b36b822..553ed5780e 100644 --- a/drivers/qe/Kconfig +++ b/drivers/qe/Kconfig @@ -14,7 +14,6 @@ config U_QE default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \ || (TARGET_T1024QDS) \ || (TARGET_T1024RDB) \ - || (TARGET_T1040QDS && !NOBQFMAN) \ || (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT) help Choose this option to add support for U QUICC Engine. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 24413d14f9..af83e9673a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -635,7 +635,7 @@ config MCFUART config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \ + depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h deleted file mode 100644 index af2916bf75..0000000000 --- a/include/configs/MPC8308RDB.h +++ /dev/null @@ -1,329 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_USE_PIO -#endif - -/* - * On-board devices - * - * TSEC1 is SoC TSEC - * TSEC2 is VSC switch - */ -#define CONFIG_TSEC1 -#define CONFIG_VSC7385_ENET - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -/* 127 64KB sectors and 8 8KB top sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ - /* 0xFFFF8396 */ - -#ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - /* VSC7385 Base address on CS2 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ - /* 0xFFFE09FF */ -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 -#endif -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * SPI on header J8 - * - * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) - * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. - */ -#ifdef CONFIG_MPC8XXX_SPI -#define CONFIG_USE_SPIFLASH -#endif - -/* - * Board info - revision and where boot from - */ -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${consoledev},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "kernel_addr=FE080000\0" \ - "fdt_addr=FE280000\0" \ - "ramdisk_addr=FE290000\0" \ - "u-boot=mpc8308rdb/u-boot.bin\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr_r=C00000\0" \ - "hostname=mpc8308rdb\0" \ - "bootfile=mpc8308rdb/uImage\0" \ - "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h deleted file mode 100644 index 586c1e9ae8..0000000000 --- a/include/configs/MPC8349ITX.h +++ /dev/null @@ -1,439 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - */ - -/* - MPC8349E-mITX and MPC8349E-mITX-GP board configuration file - - Memory map: - - 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) - 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) - 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory - 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) - - I2C address list: - Align. Board - Bus Addr Part No. Description Length Location - ---------------------------------------------------------------- - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - - I2C1 0x20 PCF8574 I2C Expander 0 U8 - I2C1 0x21 PCF8574 I2C Expander 0 U10 - I2C1 0x38 PCF8574A I2C Expander 0 U8 - I2C1 0x39 PCF8574A I2C Expander 0 U10 - I2C1 0x51 (DDR) DDR EEPROM 1 U1 - I2C1 0x68 DS1339 RTC 1 U68 - - Note that a given board has *either* a pair of 8574s or a pair of 8574As. -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * On-board devices - */ - -#ifdef CONFIG_TARGET_MPC8349ITX -/* The CF card interface on the back of the board */ -#define CONFIG_COMPACT_FLASH -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ -#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ -#endif - -#include <linux/stringify.h> -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C - -/* - * Device configurations - */ - -/* I2C */ -#ifdef CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ - -#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ - -/* Don't probe these addresses: */ -#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574_ADDR2}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR2} } -/* Bit definitions for the 8574[A] I2C expander */ - /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ -#define I2C_8574_REVISION 0x03 -#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ -#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ -#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ -#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ - -#endif - -/* Compact Flash */ -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 -#define CONFIG_SYS_ATA_STRIDE 2 - -/* If a CF card is not inserted, time out quickly */ -#define ATA_RESET_TIME 1 - -#endif - -/* - * SATA - */ -#ifdef CONFIG_SATA_SIL3114 - -#define CONFIG_SYS_SATA_MAX_DEVICE 4 -#define CONFIG_LBA48 - -#endif - -#ifdef CONFIG_SYS_USB_HOST -/* - * Support USB - */ -#define CONFIG_USB_EHCI_FSL - -/* Current USB implementation supports the only USB controller, - * so we have to choose between the MPH or the DR ones */ -#if 1 -#define CONFIG_HAS_FSL_MPH_USB -#else -#define CONFIG_HAS_FSL_DR_USB -#endif - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) - -#ifdef CONFIG_SYS_I2C -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -#endif - -/* No SPD? Then manually set up DDR parameters */ -#ifndef CONFIG_SPD_EEPROM - #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ - #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - - #define CONFIG_SYS_DDR_TIMING_1 0x26242321 - #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ -#endif - -/* - *Flash on the Local Bus - */ - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* 127 64KB sectors + 8 8KB sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* The ITX has two flash chips, but the ITX-GP has only one. To support both -boards, we say we have two, but don't display a message if we find only one. */ -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC2 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFEFFE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * BRx, ORx, LBLAWBARx, and LBLAWARx - */ - - -/* Vitesse 7385 */ - -#define CONFIG_SYS_VSC7385_BASE 0xF8000000 - -#define CONFIG_SYS_LED_BASE 0xF9000000 - - -/* Compact Flash */ - -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_CF_BASE 0xF0000000 - - -#endif - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONSOLE ttyS0 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_MPC83XX_PCI2 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE \ - (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE \ - (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS \ - (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ -#endif - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR 0x00000000 - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE - #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* TSEC */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 - -#define TSEC2_PHY_ADDR 4 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS TSEC_GIGABIT -#endif - -#define CONFIG_ETHPRIME "Freescale TSEC" - -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Watchdog */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ -#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ - -/* - * System IO Config - */ -/* Needed for gigabit to work on TSEC 1 */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 - /* USB DR as device + USB MPH as host */ -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_NETDEV "eth0" - -/* Default path and filenames */ -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_TARGET_MPC8349ITX -#define CONFIG_FDTFILE "mpc8349emitx.dtb" -#else -#define CONFIG_FDTFILE "mpc8349emitxgp.dtb" -#endif - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=" __stringify(CONSOLE) "\0" \ - "netdev=" CONFIG_NETDEV "\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ - " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ - " console=$console,$baudrate $othbootargs; " \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw" \ - " console=$console,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h deleted file mode 100644 index c42cb426d8..0000000000 --- a/include/configs/MPC837XEMDS.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * IP blocks clock configuration - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x31100000 - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ /* ODT 150ohm on SoC */ - -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - -#if defined(CONFIG_SPD_EEPROM) -#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ -#else -/* - * Manually set up DDR parameters - * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM - * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ - | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_14 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010202 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00620802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (6 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x131088c8 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03E00100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x1432 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#ifndef __ASSEMBLY__ -extern int board_pci_host_broken(void); -#endif -#define CONFIG_PCIE -#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ - -#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif /* CONFIG_PCI */ - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC1_PHY_ADDR_SGMII 8 -#define TSEC2_PHY_ADDR_SGMII 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8379_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f0ef365a85..b1acb564c3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -#elif defined(CONFIG_ARCH_T2081) #endif /* High Level Configuration Options */ @@ -50,8 +49,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg #endif #endif @@ -67,8 +64,6 @@ #endif #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg #endif #endif @@ -83,8 +78,6 @@ #endif #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg #endif #endif diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h deleted file mode 100644 index 1ecb7c9df8..0000000000 --- a/include/configs/advantech_dms-ba16.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Timesys Corporation - * Copyright (C) 2016 Advantech Corporation - * Copyright (C) 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __ADVANTECH_DMSBA16_CONFIG_H -#define __ADVANTECH_DMSBA16_CONFIG_H - -#include <asm/arch/imx-regs.h> -#include <asm/mach-imx/gpio.h> - -#define CONFIG_BOARD_NAME "Advantech DMS-BA16" - -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" -#define CONFIG_EXTRA_BOOTARGS "panic=10" - -#define CONFIG_BOOT_DIR "" -#define CONFIG_LOADCMD "fatload" -#define CONFIG_RFSPART "2" - -#include "mx6_common.h" -#include <linux/sizes.h> - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* SATA Configs */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_USBD_HS - -/* Networking Configs */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 - -/* Serial Flash */ - -#define CONFIG_LOADADDR 0x12000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=" CONFIG_BOOT_DIR "/uImage\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=yes\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "sddev=0\0" \ - "emmcdev=1\0" \ - "partnum=1\0" \ - "loadcmd=" CONFIG_LOADCMD "\0" \ - "rfspart=" CONFIG_RFSPART "\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "update_sf_uboot=" \ - "if tftp $loadaddr $uboot; then " \ - "sf probe; " \ - "sf erase 0 0xC0000; " \ - "sf write $loadaddr 0x400 $filesize; " \ - "echo 'U-Boot upgraded. Please reset'; " \ - "fi\0" \ - "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \ - "loadbootscript=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ - " source\0" \ - "loadimage=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ - "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \ - "tryboot=" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run doboot; " \ - "fi; " \ - "fi;\0" \ - "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \ - "run setargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "usb start; " \ - "setenv dev usb; " \ - "setenv devnum 0; " \ - "setenv rootdev sda${rfspart}; " \ - "run tryboot; " \ - \ - "setenv dev mmc; " \ - "setenv rootdev mmcblk0p${rfspart}; " \ - \ - "setenv devnum ${sddev}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "setenv devnum ${emmcdev}; " \ - "setenv rootdev mmcblk${emmcdev}p${rfspart}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "bmode usb; " \ - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ - -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -/* Framebuffer */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 - -#endif /* __ADVANTECH_DMSBA16_CONFIG_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h deleted file mode 100644 index aa20a7d8f2..0000000000 --- a/include/configs/am3517_crane.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517_crane.h - Default configuration for AM3517 CraneBoard. - * - * Author: Srinath.R <srinath@mistralsolutions.com> - * - * Based on include/configs/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions pvt Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* initial data */ -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_UDC for Device functionalities. - */ - -#ifdef CONFIG_USB_AM35X -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_AM35X */ - -#define CONFIG_SYS_I2C - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "mmcdev=0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command */ - /* args */ -/* memtest works on */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h deleted file mode 100644 index b69e5772a6..0000000000 --- a/include/configs/apf27.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Configuration settings for the Armadeus Project motherboard APF27 - * - * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#define CONFIG_ENV_VERSION 10 -#define CONFIG_BOARD_NAME apf27 - -/* - * SoC configurations - */ -#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ -#define CONFIG_MACH_TYPE 1698 /* APF27 */ - -/* - * Enable the call to miscellaneous platform dependent initialization. - */ - -/* - * SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 2048 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "apf27" -#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_POPULATED 1 - -#define ACFG_SDRAM_MBYTE_SYZE 64 - -#define PHYS_SDRAM_1 0xA0000000 -#define PHYS_SDRAM_2 0xB0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ - + PHYS_SDRAM_1_SIZE - 0x0100000) - -/* - * FLASH organization - */ -#define ACFG_MONITOR_OFFSET 0x00000000 -#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ -#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ -#define CONFIG_FIRMWARE_OFFSET 0x00200000 -#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ -#define CONFIG_KERNEL_OFFSET 0x00300000 -#define CONFIG_ROOTFS_OFFSET 0x00800000 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ - -#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" - -#define ACFG_CONSOLE_DEV ttySMX0 -#define CONFIG_BOOTCOMMAND "run ubifsboot" -#define CONFIG_SYS_AUTOLOAD "no" -/* - * Default load address for user programs and kernel - */ -#define CONFIG_LOADADDR 0xA0000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,6\0" \ - "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ - "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ - "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ - "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ - "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ - "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ - "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ - "kernel_addr_r=A0000000\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; "\ - "fi; " \ - "if itest ${flash_env_version} < ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; "\ - "env default flash_reset_env; "\ - "fi; \0" \ - "check_flash=nand lock; nand unlock ${env_addr}; \0" \ - "flash_reset_env=env default -f -a; saveenv; run update_env;" \ - "echo Flash environment variables erased!\0" \ - "download_uboot=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-with-spl.bin\0" \ - "flash_uboot=nand unlock ${u-boot_addr} ;" \ - "nand erase.part u-boot;" \ - "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ - "then nand lock; nand unlock ${env_addr};" \ - "echo Flashing of uboot succeed;" \ - "else echo Flashing of uboot failed;" \ - "fi; \0" \ - "update_uboot=run download_uboot flash_uboot\0" \ - "download_env=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-env.txt\0" \ - "flash_env=env import -t ${loadaddr}; env save; \0" \ - "update_env=run download_env flash_env\0" \ - "update_all=run update_env update_uboot\0" \ - "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * NOR - */ - -/* - * NAND - */ - -#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 -#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 -#define NAND_MAX_CHIPS 1 - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_NAND_QUIET 1 - -/* - * Partitions & Filsystems - */ - -/* - * Ethernet (on SOC imx FEC) - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -#define CONFIG_SYS_FPGA_CHECK_ERROR - -/* - * Fuses - IIM - */ -#ifdef CONFIG_CMD_IMX_FUSE -#define IIM_MAC_BANK 0 -#define IIM_MAC_ROW 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 -#endif - -/* - * I2C - */ - -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES { } - -#ifdef CONFIG_CMD_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ -#endif /* CONFIG_CMD_EEPROM */ -#endif /* CONFIG_CMD_I2C */ - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1374 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif /* CONFIG_CMD_DATE */ - -/* - * PLL - * - * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 - * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| - */ -#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ - -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ -#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h deleted file mode 100644 index 05ada258ea..0000000000 --- a/include/configs/bcm23550_w1d.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM23550_W1D_H -#define __BCM23550_W1D_H - -#include <linux/sizes.h> -#include <asm/arch/sysmap.h> - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_KONA_RESET_S - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#define CONFIG_SYS_L2CACHE_OFF - -#endif /* __BCM23550_W1D_H */ diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h deleted file mode 100644 index c84a5ca2e5..0000000000 --- a/include/configs/bcm28155_ap.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM28155_AP_H -#define __BCM28155_AP_H - -#include <linux/sizes.h> -#include <asm/arch/sysmap.h> - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h deleted file mode 100644 index ac5cc4c1c1..0000000000 --- a/include/configs/bcm_ep_board.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __BCM_EP_BOARD_H -#define __BCM_EP_BOARD_H - -#include <asm/arch/configs.h> - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - * (these must be defined elsewhere) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#error CONFIG_SYS_TEXT_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_BASE -#error CONFIG_SYS_SDRAM_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_SIZE -#error CONFIG_SYS_SDRAM_SIZE must be defined! -#endif - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -/* Enable Time Command */ - -#endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h deleted file mode 100644 index fbfab288b3..0000000000 --- a/include/configs/bcm_northstar2.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Broadcom NS2. - */ - -#ifndef __BCM_NORTHSTAR2_H -#define __BCM_NORTHSTAR2_H - -#include <linux/sizes.h> - -#define CONFIG_HOSTNAME "northstar2" - -/* Physical Memory Map */ -#define V2M_BASE 0x80000000 -#define PHYS_SDRAM_1 V2M_BASE - -#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G) -#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* define text_base for U-boot image */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00) -#define CONFIG_SYS_LOAD_ADDR 0x90000000 -#define CONFIG_SYS_MALLOC_LEN SZ_16M - -/* Serial Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_NS16550_COM1 0x66100000 -#define CONFIG_SYS_NS16550_COM2 0x66110000 -#define CONFIG_SYS_NS16550_COM3 0x66120000 -#define CONFIG_SYS_NS16550_COM4 0x66130000 - -/* console configuration */ -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -#endif /* __BCM_NORTHSTAR2_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h deleted file mode 100644 index bdd5973cb7..0000000000 --- a/include/configs/cgtqmx6eval.h +++ /dev/null @@ -1,197 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Congatec Conga-QEVAl board configuration file. - * - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * Based on Freescale i.MX6Q Sabre Lite board configuration file. - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Leo Sartre, <lsartre@adeneo-embedded.com> - */ - -#ifndef __CONFIG_CGTQMX6EVAL_H -#define __CONFIG_CGTQMX6EVAL_H - -#include <linux/stringify.h> - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4122 - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* SPI NOR */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST - -/* Thermal support */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ - -#define CONFIG_USBD_HS - -/* Framebuffer */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI - -/* SATA */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -/* Command definition */ - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr_r=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-qmx6.dtb; fi; " \ - "if test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ - -#define CONFIG_BOOTCOMMAND \ - "run spilock;" \ - "run findfdt; " \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#endif /* __CONFIG_CGTQMX6EVAL_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h deleted file mode 100644 index 8ab8bb9f33..0000000000 --- a/include/configs/controlcenterd.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2013 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - * based on P1022DS.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#endif - -/* High Level Configuration Options */ -#define CONFIG_CONTROLCENTERD - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CLK_FREQ 66666600 -#define CONFIG_DDR_CLK_FREQ 66666600 - -#define CONFIG_SYS_RAMBOOT - -#ifdef CONFIG_TRAILBLAZER - -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -/* - * Config the L2 Cache - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#else /* CONFIG_TRAILBLAZER */ - -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#endif /* CONFIG_TRAILBLAZER */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable - * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable - * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#ifdef CONFIG_TRAILBLAZER -/* leave CCSRBAR at default, because u-boot expects it to be exactly there */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#else -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#endif -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) - -/* - * DDR Setup - */ - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 1024 -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x52 -/*#define CONFIG_FSL_DDR_INTERACTIVE*/ -#endif - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_ELBC_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE -#endif - -#define CONFIG_UART_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) -#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) - -#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ -#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ - -#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * MMC - */ -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR - -#ifndef CONFIG_TRAILBLAZER - -/* - * Video - */ -#define CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ - -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* - * SATA - */ -#define CONFIG_LBA48 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -/* - * Ethernet - */ - -#define CONFIG_TSECV2 - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* - * USB - */ - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Environment - */ -#if defined(CONFIG_TRAILBLAZER) -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifndef CONFIG_TRAILBLAZER -/* - * Board initialisation callbacks - */ -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mp_holdoff=1\0" - -#else - -#define CONFIG_HOSTNAME "controlcenterd" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ - -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=controlcenterd.dtb\0" \ - "bdev=sda3\0" - -/* these are used and NUL-terminated in env_default.h */ -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* CONFIG_TRAILBLAZER */ - -#endif diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h deleted file mode 100644 index 9a8735f850..0000000000 --- a/include/configs/cyrus.h +++ /dev/null @@ -1,458 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on corenet_ds.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) -#error Must call Cyrus CONFIG with a specific CPU enabled. -#endif - -#define CONFIG_SDCARD -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#ifdef CONFIG_ARCH_P5020 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN -#endif -#define CONFIG_SYS_DPAA_PME - -/* - * Corenet DS style board configuration file - */ -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg -#if defined(CONFIG_ARCH_P5020) -#define CONFIG_SYS_CLK_FREQ 133000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#define CONFIG_SYS_MMC_MAX_DEVICE 1 - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -/* test POST memory test */ -#undef CONFIG_POST - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) -#else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR -#endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE -#endif - -#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull -#else -#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE -#endif - -/* Set the local bus clock 1/16 of platform clock */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) - -#define CONFIG_SYS_BR0_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_BR1_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR0_PRELIM 0xfff00010 -#define CONFIG_SYS_OR1_PRELIM 0xfff00010 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ -{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 - -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 - -#define CONFIG_SYS_I2C_GENERIC_MAC -#define CONFIG_SYS_I2C_MAC1_BUS 3 -#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 -#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 -#define CONFIG_SYS_I2C_MAC2_BUS 0 -#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 -#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa - -#define CONFIG_RTC_MCP79411 1 -#define CONFIG_SYS_RTC_BUS_NUM 3 -#define CONFIG_SYS_I2C_RTC_ADDR 0x6f - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -/* Default address of microcode for the Linux Fman driver */ -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) - -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_EHCI_IS_TDI - /* _VIA_CONTROL_EP */ -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ -"bank_intlv=cs0_cs1;" \ -"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ -"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"fdtaddr=1e00000\0" \ -"bdev=sda3\0" - -#define CONFIG_HDBOOT \ -"setenv bootargs root=/dev/$bdev rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ -"setenv bootargs root=/dev/nfs rw " \ -"nfsroot=$serverip:$rootpath " \ -"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $ramdiskaddr $ramdiskfile;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index ea8d28b5b5..8990efb3f6 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -36,14 +36,6 @@ #endif /* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* * Enable GPI0 support */ #define CONFIG_KIRKWOOD_GPIO diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 09bac01779..9106203ebc 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -52,11 +52,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 35d85361b4..f232abe430 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -55,11 +55,4 @@ #define CONFIG_PHY_BASE_ADR 8 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_DS109_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index dd16e3fbda..949ff55624 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -122,9 +122,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -/* ED Mini V has an IDE-compatible SATA connector for port 1 */ -#define CONFIG_MVSATA_IDE_USE_PORT1 /* Needs byte-swapping for ATA data register */ #define CONFIG_IDE_SWAP_IO /* Data, registers and alternate blocks are at the same offset */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 51325047ec..a18e7869b0 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -72,11 +72,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * * SATA Driver configuration - * */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 1e1e5da4d5..8de888fe7e 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -66,11 +66,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h deleted file mode 100644 index ca40417e9a..0000000000 --- a/include/configs/hrcon.h +++ /dev/null @@ -1,421 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#if 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F - -#ifdef CONFIG_HRCON_DH -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#else -#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) - -#ifdef CONFIG_HRCON_DH -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 41483a2f7e..ba859a9a24 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -56,9 +56,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/kc1.h b/include/configs/kc1.h deleted file mode 100644 index 4e9a567842..0000000000 --- a/include/configs/kc1.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amazon Kindle Fire (first generation) codename kc1 config - * - * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/cpu.h> -#include <asm/arch/omap.h> - -/* - * Build - */ - -/* - * CPU - */ - -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Board - */ - -/* - * Clocks - */ - -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 - -/* - * DRAM - */ - -/* - * Memory - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - -/* - * I2C - */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * Power - */ - -#define CONFIG_TWL6030_POWER - -/* - * Input - */ - -#define CONFIG_TWL6030_INPUT - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) - -/* - * Console - */ - -#define CONFIG_SYS_CBSIZE 512 - -/* - * Serial - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ - 115200 } - -/* - * USB gadget - */ - -/* - * Environment - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "loadaddr=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "fdtaddr=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "scriptaddr=0x80000000\0" \ - "bootm_size=0x10000000\0" \ - "boot_mmc_dev=0\0" \ - "kernel_mmc_part=7\0" \ - "recovery_mmc_part=5\0" \ - "fdtfile=omap4-kc1.dtb\0" \ - "bootfile=/boot/extlinux/extlinux.conf\0" \ - "bootargs=console=ttyO2,115200 mem=512M\0" - -/* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Boot - */ - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_BOOTCOMMAND \ - "setenv boot_mmc_part ${kernel_mmc_part}; " \ - "if test reboot-${reboot-mode} = reboot-r; then " \ - "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \ - "if test reboot-${reboot-mode} = reboot-b; then " \ - "echo fastboot; fastboot 0; fi; " \ - "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \ - "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \ - "mmc dev ${boot_mmc_dev}; " \ - "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \ - "bootm ${kernel_addr_r};" - -#endif diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h deleted file mode 100644 index 91a56dda28..0000000000 --- a/include/configs/mx53evk.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53-EVK Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK - -#include <asm/arch/imx-regs.h> - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* PMIC Configs */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_RTC_MC13XXX - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* Eth Configs */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* Command definition */ - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h deleted file mode 100644 index 83c09ead27..0000000000 --- a/include/configs/mx6qarm2.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Armadillo2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART4_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index b95c7fc3be..1fd5471ac5 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -81,14 +81,6 @@ #define CONFIG_JFFS2_LZO /* - * SATA - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* * EFI partition */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1cb0d68b5a..e38c65a485 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -48,8 +48,6 @@ /* SATA driver configuration */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h deleted file mode 100644 index ea61f92bdb..0000000000 --- a/include/configs/ot1200.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2014 Bachmann electronic GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* UART Configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* SF Configs */ - -/* IO expander */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#define CONFIG_IMX_OTP -#define IMX_OTP_BASE OCOTP_BASE_ADDR -#define IMX_OTP_ADDR_MAX 0x7F -#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA -#define IMX_OTPWRITE_ENABLED - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x5 - -#ifndef CONFIG_SPL -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_BUS 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -/* M25P16 has an erase size of 64 KiB */ - -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTFILE - -#endif /* __CONFIG_H */ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h deleted file mode 100644 index e96429083e..0000000000 --- a/include/configs/pfla02.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - */ - - -#ifndef __PCM058_CONFIG_H -#define __PCM058_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Serial */ -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* Early setup */ - - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Enable NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ - -/* Various command support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Environment organization */ - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ - "addmtd=run mtdnand;run mtdspi;" \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \ - "40m(Kernels),400m(root),-(nand)\0" \ - "mtdspi=setenv mtdparts ${mtdparts}" \ - "';spi2.0:1024k(bootloader)," \ - "64k(env1),64k(env2),-(rescue)'\0" \ - "bootcmd=if test -n ${rescue};" \ - "then run swupdate;fi;run nandboot;run swupdate\0" \ - "bootfile=uImage\0" \ - "bootimage=uImage\0" \ - "console=ttymxc3\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_file=pfla02.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "miscargs=panic=1 quiet\0" \ - "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ - "mmcboot=if run mmcload;then " \ - "run mmcargs addcons addmisc;" \ - "bootm;fi\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1\0" \ - "ubiroot=1\0" \ - "nandargs=setenv bootargs ubi.mtd=1 " \ - "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \ - "nandboot=run mtdnand;ubi part nand0,0;" \ - "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \ - "run nandargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ - "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs" \ - " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \ - "swupdate=setenv bootargs root=/dev/ram;" \ - "run addip addcons addmtd addmisc;" \ - "sf probe;" \ - "sf read ${kernel_addr_r} 120000 600000;" \ - "sf read 14000000 730000 800000;" \ - "bootm ${kernel_addr_r} 14000000\0" - -#endif diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h deleted file mode 100644 index 77b7ce411f..0000000000 --- a/include/configs/picosam9g45.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the mini-box PICOSAM9G45 board. - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: include/configs/at91sam9m10g45ek.h - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 -/* board specific(not enough SRAM) */ -#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000 - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env + linux in mmc */ - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SYS_USE_MMC - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif -#endif diff --git a/include/configs/platinum.h b/include/configs/platinum.h deleted file mode 100644 index 325a28001e..0000000000 --- a/include/configs/platinum.h +++ /dev/null @@ -1,189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_CONFIG_H__ -#define __PLATINUM_CONFIG_H__ - -/* SPL */ - -/* Location in NAND to read U-Boot from */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) - -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#include "mx6_common.h" - -/* - * Hardware configuration - */ - -/* UART config */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C config */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR - -/* USB config */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Memory config */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#ifndef PHYS_SDRAM_SIZE -#define PHYS_SDRAM_SIZE (1024 << 20) -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - -#ifdef CONFIG_CMD_NAND - -/* NAND config */ -#ifndef CONFIG_SYS_NAND_MAX_CHIPS -#define CONFIG_SYS_NAND_MAX_CHIPS 2 -#endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA config, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ - -#endif /* CONFIG_CMD_NAND */ - -/* - * U-Boot configuration - */ - -/* Board startup config */ - -#define CONFIG_BOOTCOMMAND "run bootubi_scr" - -/* Miscellaneous configurable options */ - -/* MTD/UBI/UBIFS config */ - -/* - * Environment configuration - */ - -#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi\0" \ - "setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" -#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi$boot_vol\0" \ - "setubirfs=env set ubirfs ubi0:rootfs\0" -#endif - -#define CONFIG_COMMON_ENV_MISC \ - "user=user\0" \ - "project="CONFIG_PLATINUM_PROJECT"\0" \ - "uimage=uImage\0" \ - "dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \ - "serverip=serverip\0" \ - "memaddrlinux=0x10800000\0" \ - "memaddrsrc=0x11000000\0" \ - "memaddrdtb=0x12000000\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "boot_scr=boot.uboot\0" \ - "boot_vol=0\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mmcfs=ext2\0" \ - "mmcrootpart=1\0" \ - \ - "setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \ - "settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \ - "settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \ - "setubifilelinux=env set ubifilelinux boot/$uimage\0" \ - "setubipfiledtb=env set ubifiledtb boot/$dtb\0" \ - "setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \ - "setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \ - "setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \ - \ - "loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \ - "loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \ - "loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \ - "loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \ - "loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \ - "$mmcfilelinux\0" \ - "loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \ - "$mmcfiledtb\0" \ - \ - "ubipart=ubi part $ubipartition\0" \ - "ubimount=ubifsmount $ubirfs\0" \ - \ - "setbootargscommon=env set bootargs $bootargs " \ - "console=$console,$baudrate enable_wait_mode=off\0" \ - "setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \ - "setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \ - "setbootargsubirfs=env set bootargs $bootargs " \ - "ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \ - "setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \ - "nfsroot=$serverip:$nfspath,v3,tcp\0" \ - "setbootargsmmcrfs=env set bootargs $bootargs " \ - "root=$mmcrootdev rootwait rw\0" \ - \ - "bootnet=run settftpfilelinux settftpfiledtb setnfspath " \ - "setbootargscommon setbootargsmtd setbootargsdhcp " \ - "setbootargsnfsrfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \ - "run setubipartition setubirfs;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi=run setubipartition setubirfs setubifilelinux " \ - "setubipfiledtb;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run ubipart ubimount loadubikernel loadubidtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi_scr=run setubipartition setubirfs;" \ - "run ubipart ubimount;" \ - "if ubifsload ${memaddrsrc} boot/${boot_scr}; " \ - "then source ${memaddrsrc}; else run bootubi; fi\0" \ - "bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \ - "setbootargscommon setbootargsmmcrfs;" \ - "run loadmmckernel loadmmcdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - \ - "bootcmd="CONFIG_BOOTCOMMAND"\0" - -#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ - CONFIG_COMMON_ENV_UBI -#endif /* __PLATINUM_CONFIG_H__ */ diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h deleted file mode 100644 index 1b55e73979..0000000000 --- a/include/configs/platinum_picon.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_PICON_CONFIG_H__ -#define __PLATINUM_PICON_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Picon" -#define CONFIG_PLATINUM_PROJECT "picon" -#define CONFIG_PLATINUM_CPU "imx6dl" - -#include <configs/platinum.h> - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_HOSTNAME "picon" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_PICON_CONFIG_H__ */ diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h deleted file mode 100644 index b4028832e9..0000000000 --- a/include/configs/platinum_titanium.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_TITANIUM_CONFIG_H__ -#define __PLATINUM_TITANIUM_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Titanium" -#define CONFIG_PLATINUM_PROJECT "titanium" -#define CONFIG_PLATINUM_CPU "imx6q" - -#define PHYS_SDRAM_SIZE (512 << 20) -#define CONFIG_SYS_NAND_MAX_CHIPS 1 - -#include <configs/platinum.h> - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_HOSTNAME "titanium" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h deleted file mode 100644 index 275d92eff7..0000000000 --- a/include/configs/s32v234evb.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale S32V234 EVB board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -#define CONFIG_S32V234 - -/* Config GIC */ -#define CONFIG_GICV2 -#define GICD_BASE 0x7D001000 -#define GICC_BASE 0x7D002000 - -#define CONFIG_REMAKE_ELF -#undef CONFIG_RUN_FROM_IRAM_ONLY - -#define CONFIG_RUN_FROM_DDR1 -#undef CONFIG_RUN_FROM_DDR0 - -/* Run by default from DDR1 */ -#ifdef CONFIG_RUN_FROM_DDR0 -#define DDR_BASE_ADDR 0x80000000 -#else -#define DDR_BASE_ADDR 0xC0000000 -#endif - -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */ -#define CONFIG_SYS_FSL_ERRATUM_A008585 - -/* Size of malloc() pool */ -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#endif - -#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR - -#define CONFIG_DEBUG_UART_LINFLEXUART -#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE - -#define CONFIG_SYS_UART_PORT (1) - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#if 0 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#endif - -#if 0 /* Disable until the FLASH will be implemented */ -#define CONFIG_SYS_USE_NAND -#endif - -#ifdef CONFIG_SYS_USE_NAND -/* Nand Flash Configs */ -#define CONFIG_JFFS2_NAND -#define MTD_NAND_FSL_NFC_SWECC 1 -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0x400E0000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif - -#define CONFIG_LOADADDR 0xC307FFC0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot_scripts=boot.scr.uimg boot.scr\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "console=ttyLF0,115200\0" \ - "fdt_file=s32v234-evb.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0xC2000000\0" \ - "kernel_addr_r=0xC307FFC0\0" \ - "ramdisk_addr_r=0xC4000000\0" \ - "ramdisk=rootfs.uimg\0"\ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \ - "jtagboot=echo Booting using jtag...; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \ - "run loaduimage; run loadramdisk; run loadfdt;"\ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "boot_net_usb_start=true\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include <config_distro_bootcmd.h> -#include <linux/stringify.h> - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "=> " - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) -#endif - -/* Physical memory map */ -/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ -#define PHYS_SDRAM (DDR_BASE_ADDR) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - - -#define CONFIG_BOOTP_BOOTFILESIZE - -#endif diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h deleted file mode 100644 index 853a89ced1..0000000000 --- a/include/configs/sansa_fuze_plus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ -#define __CONFIGS_SANSA_FUZE_PLUS_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h deleted file mode 100644 index 6011fb7d52..0000000000 --- a/include/configs/sc_sps_1.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SchulerControl GmbH, SC_SPS_1 module config - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_SC_SPS_1_H__ -#define __CONFIGS_SC_SPS_1_H__ - -/* System configuration */ -#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SC_SPS_1_H__ */ diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h deleted file mode 100644 index bd3c3402c4..0000000000 --- a/include/configs/secomx6quq7.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Seco S.r.l - * - * Configuration settings for the Seco Boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_BOARD_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "uboot=u-boot.bin\0" \ - "kernel=uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ - "ip_server=10.0.0.1\0" \ - "nfs_path=/targetfs \0" \ - "memory=mem=1024M\0" \ - "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ - "root=root=/dev/mmcblk0p1\0" \ - "option=rootwait rw fixrtc rootflags=barrier=1\0" \ - "cpu_freq=arm_freq=996\0" \ - "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \ - " ${option} ${memory} ${cpu_freq}\0" \ - "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \ - " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \ - " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \ - " ${memory} ${cpu_freq}\0" \ - "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ - "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \ - " bootm 0x10800000\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -#if defined(CONFIG_ENV_IS_IN_MMC) - #define CONFIG_DYNAMIC_MMC_DEVNO -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index abe8418984..41ba799659 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -55,9 +55,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/strider.h b/include/configs/strider.h deleted file mode 100644 index 85db657077..0000000000 --- a/include/configs/strider.h +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -#define CONFIG_SYS_FPGA_NO_RFL_HI - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ - {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SOFT_I2C_READ_REPEATED_START -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F -#endif -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_STRIDER_CON -#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} -#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} -#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CON_DP) -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} -#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CPU_DP) -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#else -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ - {4, 0x18} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#ifdef CONFIG_STRIDER_CON -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) -#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ - (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) -#elif defined(CONFIG_STRIDER_CON_DP) -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) -#else -#define I2C_SDA_GPIO 0x0040 -#define I2C_SCL_GPIO 0x0020 -#define I2C_FPGA_IDX I2C_ADAP_HWNR -#endif - -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif - -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS 0 - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h deleted file mode 100644 index 2954baf165..0000000000 --- a/include/configs/tao3530.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the TechNexion TAO-3530 SOM - * equipped on Thunder baseboard. - * - * Edward Lin <linuxfae@technexion.com> - * Tapani Utriainen <linuxfae@technexion.com> - * - * Copyright (C) 2013 Stefan Roese <sr@denx.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* commands to include */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=600\0" \ - "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ - "tv_mode=omapfb.mode=tv:ntsc\0" \ - "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ - "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ - "extra_options= \0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=ubi0:rootfs ubi.mtd=4\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "${extra_options}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "${network_setting} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} "\ - "${extra_options}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ - -/* turn on command-line edit/hist/auto */ - - /* defaults */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * USB - * - * Currently only EHCI is enabled, the MUSB OTG controller - * is not enabled. - */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 - -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -/* - * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: - * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT - */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -/* - * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the - * older x-loader implementations. And move the BSS area so that it - * doesn't overlap with TEXT_BASE. - */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/titanium.h b/include/configs/titanium.h deleted file mode 100644 index 895c79f1a9..0000000000 --- a/include/configs/titanium.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Stefan Roese <sr@denx.de> - * - * Configuration settings for the ProjectionDesign / Barco - * Titanium board. - * - * Based on mx6qsabrelite.h which is: - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_HOSTNAME "titanium" -#define CONFIG_UBI_PART ubi -#define CONFIG_UBIFS_VOLUME rootfs0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel=" CONFIG_HOSTNAME "/uImage\0" \ - "kernel_fs=/boot/uImage\0" \ - "kernel_addr=11000000\0" \ - "dtb=" CONFIG_HOSTNAME "/" \ - CONFIG_HOSTNAME ".dtb\0" \ - "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ - "dtb_addr=12800000\0" \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "uimage=uImage\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${script}\0" \ - "bootscript=echo Running bootscript from mmc ...; source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot} rootwait rw\0" \ - "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${uimage}; bootm\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcon=setenv bootargs ${bootargs} console=ttymxc0," \ - "${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ - "part=" __stringify(CONFIG_UBI_PART) "\0" \ - "boot_vol=0\0" \ - "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ - "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ - "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ - " ${filesize}\0" \ - "upd_ubifs=run load_ubifs update_ubifs\0" \ - "init_ubi=nand erase.part ubi;ubi part ${part};" \ - "ubi create ${vol} c800000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ - " addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "ubifsargs=set bootargs ubi.mtd=ubi " \ - "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \ - "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \ - "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ - "ubifsload ${dtb_addr} ${dtb_fs};\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ - "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \ - "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ - "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ - "net_nfs=run load_dtb load_kernel; " \ - "run nfsargs addip addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "delenv=env default -a -f; saveenv; reset\0" - -#define CONFIG_BOOTCOMMAND "run nand_ubifs" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (512 << 20) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ - -#endif /* CONFIG_CMD_NAND */ - -/* UBI/UBIFS config options */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h deleted file mode 100644 index 55f25857eb..0000000000 --- a/include/configs/tricorder.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * (C) Copyright 2012 - * Corscience GmbH & Co. KG - * Thomas Weber <weber@corscience.de> - * - * Configuration settings for the Tricorder board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024*1024) - -/* Hardware drivers */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* I2C */ -#define CONFIG_SYS_I2C - - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* TWL4030 */ - -/* Board NAND Info */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 - -/* needed for ubi */ - -/* Environment information (this is the common part) */ - - -/* hang() the board on panic() */ - -/* environment placement (for NAND), is different for FLASHCARD but does not - * harm there */ -#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ - -/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend - * value can not be used here! */ -#define CONFIG_LOADADDR 0x82000000 - -#define CONFIG_COMMON_ENV_SETTINGS \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "vram=3M\0" \ - "defaultdisplay=lcd\0" \ - "kernelopts=mtdoops.mtddev=3\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "commonargs=" \ - "setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${kernelopts} " \ - "vt.global_cursor_default=0 " \ - "vram=${vram} " \ - "omapdss.def_disp=${defaultdisplay}\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" - -/* specific environment settings for different use cases - * FLASHCARD: used to run a rdimage from sdcard to program the device - * 'NORMAL': used to boot kernel from sdcard, nand, ... - * - * The main aim for the FLASHCARD skin is to have an embedded environment - * which will not be influenced by any data already on the device. - */ -#ifdef CONFIG_FLASHCARD -/* the rdaddr is 16 MiB before the loadaddr */ -#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_ENV_RDADDR \ - "autoboot=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ - "rdinit=/sbin/init; " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ - "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ - "bootm ${loadaddr} ${rdaddr}\0" - -#else /* CONFIG_FLASHCARD */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - "mmcargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootwait " \ - "rw\0" \ - "nandargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=ubi0:root " \ - "ubi.mtd=7 " \ - "rootfstype=ubifs " \ - "ro\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "loaduimage_ubi=ubi part ubi; " \ - "ubifsmount ubi:root; " \ - "ubifsload ${loadaddr} /boot/uImage\0" \ - "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "run loaduimage_nand; " \ - "bootm ${loadaddr}\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi\0" - -#endif /* CONFIG_FLASHCARD */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* NAND and environment organization */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h deleted file mode 100644 index ae9352f5b9..0000000000 --- a/include/configs/ts4600.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> - * - * Derived from MX28EVK code by - * Fabio Estevam <fabio.estevam@freescale.com> - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4600 Board - */ -#ifndef __CONFIGS_TS4600_H__ -#define __CONFIGS_TS4600_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* Boot Linux */ -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr=0x41000000\0" \ - "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \ - "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \ - "bootscript=echo Running bootscript from mmc...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "run loadbootscript && source ${loadaddr}; \0" \ - "sdboot=echo Booting from SD card ...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv root /dev/mmcblk0p3; " \ - "run loadkernel && run loadfdt; \0" \ - "startbootsequence=run bootscript || run sdboot \0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "run startbootsequence; " \ - "setenv cmdline_append console=ttyAMA0,115200; " \ - "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \ - "bootz ${loadaddr} - ${fdt_addr}; " - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_TS4600_H__ */ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h deleted file mode 100644 index f0630a7b92..0000000000 --- a/include/configs/ts4800.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Savoir-faire Linux Inc. - * - * Derived from MX51EVK code by - * Guennadi Liakhovetski <lg@denx.de> - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4800 Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ - -#define CONFIG_HW_WATCHDOG - -#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX - -/* text base address used when linking */ - -#include <asm/arch/imx-regs.h> - -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * MMC Configs - * */ -#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR - -/* - * Eth Configs - */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -/*********************************************************** - * Command definition - ***********************************************************/ - -/* Environment variables */ - - -#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=imx51-ts4800.dtb\0" \ - "fdt_addr=0x90fe0000\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ - "mmcargs=setenv bootargs root=${mmcroot}\0" \ - "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addtty; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo ERR: cannot load FDT; " \ - "fi; " - - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Low level init */ -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON - -/*----------------------------------------------------------------------- - * Environment organization - */ - -#endif diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h deleted file mode 100644 index 4f8e63574d..0000000000 --- a/include/configs/vexpress_ca15_tc2.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Linaro - * Andre Przywara, <andre.przywara@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA15X2_TC2_h -#define __VEXPRESS_CA15X2_TC2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#define CONFIG_SYSFLAGS_ADDR 0x1c010030 -#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR - -#endif diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h deleted file mode 100644 index b8079e63d6..0000000000 --- a/include/configs/vexpress_ca5x2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, <ryan.harkin@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA5X2_h -#define __VEXPRESS_CA5X2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h deleted file mode 100644 index 8157a5868d..0000000000 --- a/include/configs/vexpress_ca9x4.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, <ryan.harkin@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA9X4_H -#define __VEXPRESS_CA9X4_H - -#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h deleted file mode 100644 index cc7a688580..0000000000 --- a/include/configs/wb45n.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB45N CPU Module. - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -#include <asm/hardware.h> -#include <linux/stringify.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 - -#define CONFIG_RBTREE - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -/* System */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env + linux in nandflash */ - -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ - "run _mtd; bootm" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ - "128K(at91bs)," \ - "512K(u-boot)," \ - "128K(u-boot-env)," \ - "128K(redund-env)," \ - "2560K(kernel-a)," \ - "2560K(kernel-b)," \ - "38912K(rootfs-a)," \ - "38912K(rootfs-b)," \ - "46208K(user)," \ - "512K(logs)" - -#else -#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ - "autoload=no\0" \ - "autostart=no\0" \ - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ - "\0" - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif /* __CONFIG_H__ */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h deleted file mode 100644 index b1f3b8452c..0000000000 --- a/include/configs/wb50n.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB50N CPU Module. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_DBGU - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x310000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_RGMII -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "autostart=no\0" - -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_BOOTCOMMAND \ - "nand read 0x22000000 0x000e0000 0x500000; " \ - "bootm" - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h deleted file mode 100644 index 80849129b9..0000000000 --- a/include/configs/xfi3.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIGS_XFI3_H__ -#define __CONFIGS_XFI3_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_XFI3_H__ */ diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h deleted file mode 100644 index 7246b9eb65..0000000000 --- a/include/configs/zc5202.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5202_H -#define __EL_ZC5202_H - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h deleted file mode 100644 index e4fe7a462d..0000000000 --- a/include/configs/zc5601.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5601_H -#define __EL_ZC5601_H - - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x10 -#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */ - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 6d38a83d90..aa9b9f58b8 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -88,113 +88,4 @@ struct ihs_fpga { }; #endif -#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[2]; /* 0x000c */ - u16 control; /* 0x0010 */ - u16 extended_control; /* 0x0012 */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c0; /* 0x0040 */ - u16 reserved_4[10]; /* 0x004c */ - u16 mc_int; /* 0x0060 */ - u16 mc_int_en; /* 0x0062 */ - u16 mc_status; /* 0x0064 */ - u16 mc_control; /* 0x0066 */ - u16 mc_tx_data; /* 0x0068 */ - u16 mc_tx_address; /* 0x006a */ - u16 mc_tx_cmd; /* 0x006c */ - u16 mc_res; /* 0x006e */ - u16 mc_rx_cmd_status; /* 0x0070 */ - u16 mc_rx_data; /* 0x0072 */ - u16 reserved_5[69]; /* 0x0074 */ - u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd0; /* 0x0100 */ -#ifdef CONFIG_SYS_OSD_DH - u16 reserved_6[57]; /* 0x010e */ - struct ihs_osd osd1; /* 0x0180 */ - u16 reserved_7[9]; /* 0x018e */ - struct ihs_i2c i2c1; /* 0x01a0 */ - u16 reserved_8[1834]; /* 0x01ac */ - u16 videomem0[2048]; /* 0x1000 */ - u16 videomem1[2048]; /* 0x2000 */ -#else - u16 reserved_6[889]; /* 0x010e */ - u16 videomem0[2048]; /* 0x0800 */ -#endif -}; -#endif - -#ifdef CONFIG_STRIDER_CPU -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[3]; /* 0x000c */ - u16 extended_control; /* 0x0012 */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - u16 mc_int; /* 0x0040 */ - u16 mc_int_en; /* 0x0042 */ - u16 mc_status; /* 0x0044 */ - u16 mc_control; /* 0x0046 */ - u16 mc_tx_data; /* 0x0048 */ - u16 mc_tx_address; /* 0x004a */ - u16 mc_tx_cmd; /* 0x004c */ - u16 mc_res; /* 0x004e */ - u16 mc_rx_cmd_status; /* 0x0050 */ - u16 mc_rx_data; /* 0x0052 */ - u16 reserved_4[62]; /* 0x0054 */ - struct ihs_i2c i2c0; /* 0x00d0 */ -}; -#endif - -#ifdef CONFIG_STRIDER_CON -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c0; /* 0x0040 */ - u16 reserved_4[10]; /* 0x004c */ - u16 mc_int; /* 0x0060 */ - u16 mc_int_en; /* 0x0062 */ - u16 mc_status; /* 0x0064 */ - u16 mc_control; /* 0x0066 */ - u16 mc_tx_data; /* 0x0068 */ - u16 mc_tx_address; /* 0x006a */ - u16 mc_tx_cmd; /* 0x006c */ - u16 mc_res; /* 0x006e */ - u16 mc_rx_cmd_status; /* 0x0070 */ - u16 mc_rx_data; /* 0x0072 */ - u16 reserved_5[70]; /* 0x0074 */ - struct ihs_osd osd0; /* 0x0100 */ - u16 reserved_6[889]; /* 0x010e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 39e6416afc..425a7ecb89 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1079,8 +1079,6 @@ CONFIG_MUSB_HOST CONFIG_MVGBE_PORTS CONFIG_MVMFP_V2 CONFIG_MVS -CONFIG_MVSATA_IDE_USE_PORT0 -CONFIG_MVSATA_IDE_USE_PORT1 CONFIG_MV_ETH_RXQ CONFIG_MV_I2C_NUM CONFIG_MV_I2C_REG |