Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/10Sep2021

- mvebu: dts: Armada8k enable mdio (Sven)
- a37xx: pci: Fix / enhance error handling (Pali)
- mvebu: espressobin/turris_: Enable GPT partition support (Pali)
- mvebu: sata_mv: Probe all ports (Tony)
- a37xx: pci: Don't spam about PIO Response Status (Marek)

12 files changed, 76 insertions, 24 deletions

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index b158f92349..9104042359 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -175,6 +175,7 @@
 };
 
 &cp0_mdio {
+	status = "okay";
 	phy0: ethernet-phy@0 {
 		reg = <0>;
 	};
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 6a586dbbba..79ee871c5a 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -295,6 +295,7 @@
 };
 
 &cp1_mdio {
+	status = "okay";
 	phy0: ethernet-phy@0 {
 		reg = <0>;
 	};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 51c2f23f4d..2686e00242 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -270,6 +270,7 @@
 };
 
 &cp0_mdio {
+	status = "okay";
 	phy1: ethernet-phy@1 {
 		reg = <1>;
 	};
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 2184648318..b0bed77ae6 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -155,6 +155,7 @@
 };
 
 &cp0_mdio {
+	status = "okay";
 	ge_phy: ethernet-phy@0 {
 		reg = <0>;
 	};
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
index d5b6b22ddf..7ba14021b2 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -163,7 +163,7 @@ void reset_phy(void)
 	char *eth0_name = "ethernet-controller@72000";
 	char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
 	char *eth1_name = "ethernet-controller@76000";
-	char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0";
+	char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
 
 	/* configure and initialize both PHY's */
 	mv_phy_88e1116_init(eth0_name, eth0_path);
diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS
index 2b0103d07d..282f046667 100644
--- a/board/Marvell/sheevaplug/MAINTAINERS
+++ b/board/Marvell/sheevaplug/MAINTAINERS
@@ -1,5 +1,5 @@
 SHEEVAPLUG BOARD
-M:	Prafulla Wadaskar <prafulla@marvell.com>
+M:	Tony Dinh <mibodhi@gmail.com>
 S:	Maintained
 F:	board/Marvell/sheevaplug/
 F:	include/configs/sheevaplug.h
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 9641c02d93..761187479f 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -26,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index 40f975ead3..9a9102430e 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index b2bbbd1469..a724a1baa1 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -40,6 +40,7 @@ CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_LZMADEC=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index dadb2c7c2e..003222d47b 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev)
 	int nr_ports;
 	int ret;
 	int i;
+	int status = -ENODEV; /* If the probe fails to detected any SATA port */
 
 	/* Get number of ports of this SATA controller */
 	nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
@@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev)
 					 IF_TYPE_SATA, -1, 512, 0, &blk);
 		if (ret) {
 			debug("Can't create device\n");
-			return ret;
+			continue;
 		}
 
 		priv = dev_get_plat(blk);
@@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev)
 		ret = sata_mv_init_sata(blk, i);
 		if (ret) {
 			debug("%s: Failed to init bus\n", __func__);
-			return ret;
+			continue;
 		}
 
 		/* Scan SATA port */
 		ret = sata_mv_scan_sata(blk, i);
 		if (ret) {
 			debug("%s: Failed to scan bus\n", __func__);
-			return ret;
+			continue;
 		}
+
+		/* If we got here, the current SATA port was probed
+		 * successfully, so set the probe status to successful.
+		 */
+		status = 0;
 	}
 
-	return 0;
+	return status;
 }
 
 static int sata_mv_scan(struct udevice *dev)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 815b26162f..cf6e30f936 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -234,19 +234,19 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  *
  * Wait up to 1.5 seconds for PIO access to be accomplished.
  *
- * Return 1 (true) if PIO access is accomplished.
- * Return 0 (false) if PIO access is timed out.
+ * Return positive - retry count if PIO access is accomplished.
+ * Return negative - error if PIO access is timed out.
  */
 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
 {
 	uint start, isr;
 	uint count;
 
-	for (count = 0; count < PIO_MAX_RETRIES; count++) {
+	for (count = 1; count <= PIO_MAX_RETRIES; count++) {
 		start = advk_readl(pcie, PIO_START);
 		isr = advk_readl(pcie, PIO_ISR);
 		if (!start && isr)
-			return 1;
+			return count;
 		/*
 		 * Do not check the PIO state too frequently,
 		 * 100us delay is appropriate.
@@ -255,7 +255,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
 	}
 
 	dev_err(pcie->dev, "PIO read/write transfer time out\n");
-	return 0;
+	return -ETIMEDOUT;
 }
 
 /**
@@ -265,11 +265,13 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  * @allow_crs: Only for read requests, if CRS response is allowed
  * @read_val: Pointer to the read result
  *
+ * Return: 0 on success
  */
 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 				      bool allow_crs,
 				      uint *read_val)
 {
+	int ret;
 	uint reg;
 	unsigned int status;
 	char *strcomp_status, *str_posted;
@@ -282,6 +284,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 	case PIO_COMPLETION_STATUS_OK:
 		if (reg & PIO_ERR_STATUS) {
 			strcomp_status = "COMP_ERR";
+			ret = -EFAULT;
 			break;
 		}
 		/* Get the read result */
@@ -289,40 +292,46 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 			*read_val = advk_readl(pcie, PIO_RD_DATA);
 		/* No error */
 		strcomp_status = NULL;
+		ret = 0;
 		break;
 	case PIO_COMPLETION_STATUS_UR:
 		strcomp_status = "UR";
+		ret = -EOPNOTSUPP;
 		break;
 	case PIO_COMPLETION_STATUS_CRS:
 		if (allow_crs && read_val) {
 			/* For reading, CRS is not an error status. */
 			*read_val = CFG_RD_CRS_VAL;
 			strcomp_status = NULL;
+			ret = 0;
 		} else {
 			strcomp_status = "CRS";
+			ret = -EAGAIN;
 		}
 		break;
 	case PIO_COMPLETION_STATUS_CA:
 		strcomp_status = "CA";
+		ret = -ECANCELED;
 		break;
 	default:
 		strcomp_status = "Unknown";
+		ret = -EINVAL;
 		break;
 	}
 
 	if (!strcomp_status)
-		return 0;
+		return ret;
 
 	if (reg & PIO_NON_POSTED_REQ)
 		str_posted = "Non-posted";
 	else
 		str_posted = "Posted";
 
-	dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
+	dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
 		str_posted, strcomp_status, reg,
 		advk_readl(pcie, PIO_ADDR_LS));
 
-	return -EFAULT;
+	return ret;
 }
 
 /**
@@ -345,6 +354,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 				 enum pci_size_t size)
 {
 	struct pcie_advk *pcie = dev_get_priv(bus);
+	int retry_count;
 	bool allow_crs;
 	uint reg;
 	int ret;
@@ -358,7 +368,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 		return 0;
 	}
 
-	allow_crs = (offset == PCI_VENDOR_ID) && (size == 4);
+	/*
+	 * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
+	 * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
+	 * only when CRSSVE bit in Root Port PCIe device is enabled. In all
+	 * other error PCIe Root Complex must return all-ones.
+	 * Aardvark HW does not have Root Port PCIe device and U-Boot does not
+	 * implement emulation of this device.
+	 * U-Boot currently does not support handling of CRS return value for
+	 * PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
+	 * Therefore disable returning CRS response for now.
+	 */
+	allow_crs = false;
 
 	if (advk_readl(pcie, PIO_START)) {
 		dev_err(pcie->dev,
@@ -368,7 +389,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 			return 0;
 		}
 		*valuep = pci_get_ff(size);
-		return -EINVAL;
+		return -EAGAIN;
 	}
 
 	/* Program the control register */
@@ -385,21 +406,29 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 	advk_writel(pcie, reg, PIO_ADDR_LS);
 	advk_writel(pcie, 0, PIO_ADDR_MS);
 
+	retry_count = 0;
+
+retry:
 	/* Start the transfer */
 	advk_writel(pcie, 1, PIO_ISR);
 	advk_writel(pcie, 1, PIO_START);
 
-	if (!pcie_advk_wait_pio(pcie)) {
+	ret = pcie_advk_wait_pio(pcie);
+	if (ret < 0) {
 		if (allow_crs) {
 			*valuep = CFG_RD_CRS_VAL;
 			return 0;
 		}
 		*valuep = pci_get_ff(size);
-		return -EINVAL;
+		return ret;
 	}
 
+	retry_count += ret;
+
 	/* Check PIO status and get the read result */
 	ret = pcie_advk_check_pio_status(pcie, allow_crs, &reg);
+	if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
+		goto retry;
 	if (ret) {
 		*valuep = pci_get_ff(size);
 		return ret;
@@ -461,7 +490,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 				  enum pci_size_t size)
 {
 	struct pcie_advk *pcie = dev_get_priv(bus);
+	int retry_count;
 	uint reg;
+	int ret;
 
 	dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
 		PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
@@ -476,7 +507,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 	if (advk_readl(pcie, PIO_START)) {
 		dev_err(pcie->dev,
 			"Previous PIO read/write transfer is still running\n");
-		return -EINVAL;
+		return -EAGAIN;
 	}
 
 	/* Program the control register */
@@ -504,16 +535,24 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 	advk_writel(pcie, reg, PIO_WR_DATA_STRB);
 	dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
 
+	retry_count = 0;
+
+retry:
 	/* Start the transfer */
 	advk_writel(pcie, 1, PIO_ISR);
 	advk_writel(pcie, 1, PIO_START);
 
-	if (!pcie_advk_wait_pio(pcie)) {
-		return -EINVAL;
-	}
+	ret = pcie_advk_wait_pio(pcie);
+	if (ret < 0)
+		return ret;
+
+	retry_count += ret;
 
 	/* Check PIO status */
-	return pcie_advk_check_pio_status(pcie, false, NULL);
+	ret = pcie_advk_check_pio_status(pcie, false, NULL);
+	if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
+		goto retry;
+	return ret;
 }
 
 /**
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 53d7acbb10..6036bf4fa5 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -45,7 +45,7 @@
 					  230400, 460800, 500000, 576000, \
 					  921600, 1000000, 1152000, 1500000, \
 					  2000000, 2500000, 3125000, 4000000, \
-					  5150000 }
+					  5200000 }
 #endif
 
 /* auto boot */