Merge tag 'u-boot-imx-20191104' of https://gitlab.denx.de/u-boot/custodians/u-boot-imxWIP/04Nov2019

u-boot-imx-20191104
-------------------

- i.MX NAND: nandbcb support for MX6UL / i.MX7
- i.MX8: support for HAB
- Convert to DM (opos6ul, mccmon6)
- Toradex i.MX6ull colibri
- sync DTS with kernel

Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416

89 files changed, 7568 insertions, 2731 deletions

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index a5c528a18d..7a1b39844e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -1254,8 +1254,8 @@ void mxs_power_init(void)
 	debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
 	mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
 
-	debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n");
-	mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315);
+	debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
+	mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
 #ifdef CONFIG_MX23
 	debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
 	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47978e7685..251d32ca62 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -565,6 +565,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 
 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
 dtb-y += \
+	imx6dl-brppt2.dtb \
 	imx6dl-dhcom-pdk2.dtb \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
@@ -589,6 +590,7 @@ dtb-y += \
 	imx6q-icore-rqs.dtb \
 	imx6q-kp.dtb \
 	imx6q-logicpd.dtb \
+	imx6q-mccmon6.dtb\
 	imx6q-nitrogen6x.dtb \
 	imx6q-novena.dtb \
 	imx6q-pico.dtb \
@@ -651,11 +653,14 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
+	imx8qm-rom7720-a1.dtb \
+	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-mek.dtb
 
-dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
-	imx8mm-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8M) += \
+	imx8mm-evk.dtb \
+	imx8mq-evk.dtb
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
deleted file mode 100644
index 4a08099b3c..0000000000
--- a/arch/arm/dts/fsl-imx8mq-evk.dts
+++ /dev/null
@@ -1,414 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-/dts-v1/;
-
-/* First 128KB is for PSCI ATF. */
-/memreserve/ 0x40000000 0x00020000;
-
-#include "fsl-imx8mq.dtsi"
-
-/ {
-	model = "Freescale i.MX8MQ EVK";
-	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
-
-	chosen {
-		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reg_usdhc2_vmmc: usdhc2_vmmc {
-			compatible = "regulator-fixed";
-			regulator-name = "VSD_3V3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
-	};
-
-	pwmleds {
-		compatible = "pwm-leds";
-
-		ledpwm2 {
-			label = "PWM2";
-			pwms = <&pwm2 0 50000>;
-			max-brightness = <255>;
-		};
-	};
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-
-	imx8mq-evk {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
-				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
-				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
-				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
-				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
-				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
-				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
-				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
-				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
-				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
-				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
-				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
-				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
-			>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f
-				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f
-			>;
-		};
-
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f
-				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f
-			>;
-		};
-
-		pinctrl_pwm2: pwm2grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
-			>;
-		};
-
-		pinctrl_qspi: qspigrp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
-				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
-				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
-				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
-				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
-				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
-
-			>;
-		};
-
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83
-				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
-			>;
-		};
-
-		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85
-				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
-			>;
-		};
-
-		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87
-				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
-			>;
-		};
-
-		pinctrl_usdhc2_gpio: usdhc2grpgpio {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
-				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
-			>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
-				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
-			>;
-		};
-
-		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5
-				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
-			>;
-		};
-
-		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7
-				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
-			>;
-		};
-
-		pinctrl_sai2: sai2grp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
-				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
-				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
-				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
-				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
-			>;
-		};
-
-		pinctrl_wdog: wdoggrp {
-			fsl,pins = <
-				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
-			>;
-		};
-	};
-};
-
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy0>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@0 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			at803x,led-act-blind-workaround;
-			at803x,eee-disabled;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	pmic: pfuze100@08 {
-		compatible = "fsl,pfuze100";
-		reg = <0x08>;
-
-		regulators {
-			sw1a_reg: sw1ab {
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1875000>;
-				regulator-always-on;
-			};
-
-			sw1c_reg: sw1c {
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1875000>;
-				regulator-always-on;
-			};
-
-			sw2_reg: sw2 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			sw3a_reg: sw3ab {
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1975000>;
-				regulator-always-on;
-			};
-
-			sw4_reg: sw4 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			swbst_reg: swbst {
-				regulator-min-microvolt = <5000000>;
-				regulator-max-microvolt = <5150000>;
-			};
-
-			snvs_reg: vsnvs {
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-
-			vref_reg: vrefddr {
-				regulator-always-on;
-			};
-
-			vgen1_reg: vgen1 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1550000>;
-			};
-
-			vgen2_reg: vgen2 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1550000>;
-				regulator-always-on;
-			};
-
-			vgen3_reg: vgen3 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vgen4_reg: vgen4 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vgen5_reg: vgen5 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vgen6_reg: vgen6 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "disabled";
-};
-
-&pwm2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm2>;
-	status = "okay";
-};
-
-&lcdif {
-	status = "okay";
-	disp-dev = "mipi_dsi_northwest";
-	display = <&display0>;
-
-	display0: display@0 {
-		bits-per-pixel = <24>;
-		bus-width = <24>;
-
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: timing0 {
-			clock-frequency = <9200000>;
-			hactive = <480>;
-			vactive = <272>;
-			hfront-porch = <8>;
-			hback-porch = <4>;
-			hsync-len = <41>;
-			vback-porch = <2>;
-			vfront-porch = <4>;
-			vsync-len = <10>;
-
-			hsync-active = <0>;
-			vsync-active = <0>;
-			de-active = <1>;
-			pixelclk-active = <0>;
-			};
-		};
-	};
-};
-
-&qspi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_qspi>;
-	status = "okay";
-
-	flash0: n25q256a@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "micron,n25q256a";
-		spi-max-frequency = <29000000>;
-		spi-nor,ddr-quad-read-dummy = <6>;
-	};
-};
-
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	bus-width = <4>;
-	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
deleted file mode 100644
index d0206c9dbe..0000000000
--- a/arch/arm/dts/fsl-imx8mq.dtsi
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "fsl-imx8-ca53.dtsi"
-#include <dt-bindings/clock/imx8mq-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/pins-imx8mq.h>
-#include <dt-bindings/reset/imx8mq-reset.h>
-#include <dt-bindings/power/imx8mq-power.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	compatible = "fsl,imx8mq";
-	interrupt-parent = <&gpc>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		ethernet0 = &fec1;
-		mmc0 = &usdhc1;
-		mmc1 = &usdhc2;
-		gpio0 = &gpio1;
-		gpio1 = &gpio2;
-		gpio2 = &gpio3;
-		gpio3 = &gpio4;
-		gpio4 = &gpio5;
-		i2c0 = &i2c1;
-		i2c1 = &i2c2;
-		i2c2 = &i2c3;
-		i2c3 = &i2c4;
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x00000000 0x40000000 0 0xc0000000>;
-	};
-
-	gic: interrupt-controller@38800000 {
-		compatible = "arm,gic-v3";
-		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
-		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
-			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
-			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
-			     IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
-			     IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
-		clock-frequency = <8333333>;
-		interrupt-parent = <&gic>;
-	};
-
-	pwm2: pwm@30670000 {
-		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
-		reg = <0x0 0x30670000 0x0 0x10000>;
-		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
-			 <&clk IMX8MQ_CLK_PWM2_ROOT>;
-		clock-names = "ipg", "per";
-		#pwm-cells = <2>;
-		status = "disabled";
-	};
-
-	gpio1: gpio@30200000 {
-		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x30200000 0x0 0x10000>;
-		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio2: gpio@30210000 {
-		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x30210000 0x0 0x10000>;
-		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio3: gpio@30220000 {
-		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x30220000 0x0 0x10000>;
-		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio4: gpio@30230000 {
-		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x30230000 0x0 0x10000>;
-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio5: gpio@30240000 {
-		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x30240000 0x0 0x10000>;
-		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	tmu: tmu@30260000 {
-		compatible = "fsl,imx8mq-tmu";
-		reg = <0x0 0x30260000 0x0 0x10000>;
-		interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-		little-endian;
-		u-boot,dm-pre-reloc;
-		fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
-		fsl,tmu-calibration = <0x00000000 0x00000020
-				       0x00000001 0x00000028
-				       0x00000002 0x00000030
-				       0x00000003 0x00000038
-				       0x00000004 0x00000040
-				       0x00000005 0x00000048
-				       0x00000006 0x00000050
-				       0x00000007 0x00000058
-				       0x00000008 0x00000060
-				       0x00000009 0x00000068
-				       0x0000000a 0x00000070
-				       0x0000000b 0x00000077
-
-				       0x00010000 0x00000057
-				       0x00010001 0x0000005b
-				       0x00010002 0x0000005f
-				       0x00010003 0x00000063
-				       0x00010004 0x00000067
-				       0x00010005 0x0000006b
-				       0x00010006 0x0000006f
-				       0x00010007 0x00000073
-				       0x00010008 0x00000077
-				       0x00010009 0x0000007b
-				       0x0001000a 0x0000007f
-
-				       0x00020000 0x00000002
-				       0x00020001 0x0000000e
-				       0x00020002 0x0000001a
-				       0x00020003 0x00000026
-				       0x00020004 0x00000032
-				       0x00020005 0x0000003e
-				       0x00020006 0x0000004a
-				       0x00020007 0x00000056
-				       0x00020008 0x00000062
-
-				       0x00030000 0x00000000
-				       0x00030001 0x00000008
-				       0x00030002 0x00000010
-				       0x00030003 0x00000018
-				       0x00030004 0x00000020
-				       0x00030005 0x00000028
-				       0x00030006 0x00000030
-				       0x00030007 0x00000038>;
-		#thermal-sensor-cells =  <0>;
-	};
-
-	thermal-zones {
-		/* cpu thermal */
-		cpu-thermal {
-			polling-delay-passive = <250>;
-			polling-delay = <2000>;
-			thermal-sensors = <&tmu>;
-			trips {
-				cpu_alert0: trip0 {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				cpu_crit0: trip1 {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map0 {
-					trip = <&cpu_alert0>;
-					cooling-device =
-					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-			};
-		};
-	};
-
-	lcdif: lcdif@30320000 {
-		compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
-		reg = <0x0 0x30320000 0x0 0x10000>;
-		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
-			 <&clk IMX8MQ_CLK_DUMMY>,
-			 <&clk IMX8MQ_CLK_DUMMY>;
-		clock-names = "pix", "axi", "disp_axi";
-		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
-		assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
-		assigned-clock-rate = <594000000>;
-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-	};
-
-	iomuxc: iomuxc@30330000 {
-		compatible = "fsl,imx8mq-iomuxc";
-		reg = <0x0 0x30330000 0x0 0x10000>;
-	};
-
-	gpr: iomuxc-gpr@30340000 {
-		compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
-		reg = <0x0 0x30340000 0x0 0x10000>;
-	};
-
-	ocotp: ocotp-ctrl@30350000 {
-		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
-		reg = <0x0 0x30350000 0x0 0x10000>;
-	};
-
-	anatop: anatop@30360000 {
-		compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
-			"syscon", "simple-bus";
-		reg = <0x0 0x30360000 0x0 0x10000>;
-		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	clk: ccm@30380000 {
-		compatible = "fsl,imx8mq-ccm";
-		reg = <0x0 0x30380000 0x0 0x10000>;
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-		#clock-cells = <1>;
-	};
-
-	src: reset-controller@30390000 {
-		compatible = "fsl,imx8mq-src", "syscon";
-		reg = <0x0 0x30390000 0x0 0x10000>;
-		#reset-cells = <1>;
-	};
-
-	gpc: gpc@303a0000 {
-		compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
-		reg = <0x0 0x303a0000 0x0 0x10000>;
-		interrupt-controller;
-		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-
-		pgc {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/*
-			 * As per comment in ATF source code:
-			 *
-			 * PCIE1 and PCIE2 share the
-			 * same reset signal, if we
-			 * power down PCIE2, PCIE1
-			 * will be held in reset too.
-			 *
-			 * So instead of creating two
-			 * separate power domains for
-			 * PCIE1 and PCIE2 we create a
-			 * link between both and use
-			 * it as a shared PCIE power
-			 * domain.
-			 */
-			pgc_pcie: power-domain@1 {
-				#power-domain-cells = <0>;
-				reg = <IMX8M_POWER_DOMAIN_PCIE1>;
-				power-domains = <&pgc_pcie2>;
-			};
-
-			pgc_pcie2: power-domain@a {
-				#power-domain-cells = <0>;
-				reg = <IMX8M_POWER_DOMAIN_PCIE2>;
-			};
-		};
-	};
-
-	usdhc1: usdhc@30b40000 {
-		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
-		reg = <0x0 0x30b40000 0x0 0x10000>;
-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_DUMMY>,
-			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
-			<&clk IMX8MQ_CLK_USDHC1_ROOT>;
-		clock-names = "ipg", "ahb", "per";
-		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
-		assigned-clock-rates = <400000000>;
-		fsl,tuning-start-tap = <20>;
-		fsl,tuning-step= <2>;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
-	usdhc2: usdhc@30b50000 {
-		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
-		reg = <0x0 0x30b50000 0x0 0x10000>;
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_DUMMY>,
-			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
-			<&clk IMX8MQ_CLK_USDHC2_ROOT>;
-		clock-names = "ipg", "ahb", "per";
-		fsl,tuning-start-tap = <20>;
-		fsl,tuning-step= <2>;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
-	fec1: ethernet@30be0000 {
-		compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
-		reg = <0x0 0x30be0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
-			<&clk IMX8MQ_CLK_ENET1_ROOT>,
-			<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
-			<&clk IMX8MQ_CLK_ENET_REF_DIV>,
-			<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
-		clock-names = "ipg", "ahb", "ptp",
-			"enet_clk_ref", "enet_out";
-		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
-		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
-					 <&clk IMX8MQ_SYS2_PLL_100M>,
-					 <&clk IMX8MQ_SYS2_PLL_125M>;
-		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
-		stop-mode = <&gpr 0x10 3>;
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
-		fsl,wakeup_irq = <2>;
-		status = "disabled";
-	};
-
-	imx_ion {
-		compatible = "fsl,mxc-ion";
-		fsl,heap-id = <0>;
-	};
-
-	i2c1: i2c@30a20000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx21-i2c";
-		reg = <0x0 0x30a20000 0x0 0x10000>;
-		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
-		status = "disabled";
-	};
-
-	i2c2: i2c@30a30000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx21-i2c";
-		reg = <0x0 0x30a30000 0x0 0x10000>;
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
-		status = "disabled";
-	};
-
-	i2c3: i2c@30a40000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx21-i2c";
-		reg = <0x0 0x30a40000 0x0 0x10000>;
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
-		status = "disabled";
-	};
-
-	i2c4: i2c@30a50000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx21-i2c";
-		reg = <0x0 0x30a50000 0x0 0x10000>;
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
-		status = "disabled";
-	};
-
-	wdog1: wdog@30280000 {
-			compatible = "fsl,imx21-wdt";
-			reg = <0 0x30280000 0 0x10000>;
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
-			status = "disabled";
-	};
-
-	wdog2: wdog@30290000 {
-			compatible = "fsl,imx21-wdt";
-			reg = <0 0x30290000 0 0x10000>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
-			status = "disabled";
-	};
-
-	wdog3: wdog@302a0000 {
-			compatible = "fsl,imx21-wdt";
-			reg = <0 0x302a0000 0 0x10000>;
-			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
-			status = "disabled";
-	};
-
-	dma_cap: dma_cap {
-		compatible = "dma-capability";
-		only-dma-mask32 = <1>;
-	};
-
-	qspi: qspi@30bb0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx7d-qspi";
-		reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
-		reg-names = "QuadSPI", "QuadSPI-memory";
-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
-		<&clk IMX8MQ_CLK_QSPI_ROOT>;
-		clock-names = "qspi_en", "qspi";
-		status = "disabled";
-	};
-};
-
-&A53_0 {
-	#cooling-cells = <2>;
-};
diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
new file mode 100644
index 0000000000..3ca53bb945
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Linaro Ltd.
+ */
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&lpuart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
new file mode 100644
index 0000000000..aa85caaff5
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Einfochips
+ * Copyright 2019 Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"
+
+/ {
+	model = "Einfochips i.MX8QXP AI_ML";
+	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+		stdout-path = &lpuart2;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	status = "okay";
+};
+
+&lpuart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart3>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	phy-reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+/* LS-I2C1 */
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <4>;
+	no-sd;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+			SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+			SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+			SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+			SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+			SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+			SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+			SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+			SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+			SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+			SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+			SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+			SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+			SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+			SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			SC_P_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
+			SC_P_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
+		>;
+	};
+
+	pinctrl_lpuart0: lpuart0grp {
+		fsl,pins = <
+			SC_P_UART0_RX_ADMA_UART0_RX			0X06000020
+			SC_P_UART0_TX_ADMA_UART0_TX			0X06000020
+		>;
+	};
+
+	pinctrl_lpuart1: lpuart1grp {
+		fsl,pins = <
+			SC_P_UART1_RX_ADMA_UART1_RX			0X06000020
+			SC_P_UART1_TX_ADMA_UART1_TX			0X06000020
+		>;
+	};
+
+	pinctrl_lpuart2: lpuart2grp {
+		fsl,pins = <
+			SC_P_UART2_RX_ADMA_UART2_RX			0X06000020
+			SC_P_UART2_TX_ADMA_UART2_TX			0X06000020
+		>;
+	};
+
+	pinctrl_lpuart3: lpuart3grp {
+		fsl,pins = <
+			SC_P_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020
+			SC_P_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+			SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
+			SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021
+			SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021
+			SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021
+			SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
+			SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
+			SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021
+			SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021
+			SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021
+			SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021
+			SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6dl-brppt2.dts b/arch/arm/dts/imx6dl-brppt2.dts
new file mode 100644
index 0000000000..4f1c52bff8
--- /dev/null
+++ b/arch/arm/dts/imx6dl-brppt2.dts
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 B&R Industrial Automation GmbH
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-u-boot.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <include/dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "PPT50";
+	compatible = "fsl,imx6dl";
+
+	config {
+		u-boot,spl-payload-offset = <0x100000>;
+	};
+
+	fset: factory-settings {
+		bl-version	= "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+		order-no	= "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+		hw-revision	= "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+		serial-no	= <0>;
+		device-id	= <0x0>;
+		parent-id	= <0x0>;
+		hw-variant	= <0x0>;
+	};
+
+	aliases {
+		ds1timing0 = &timing0;
+		ds1timing1 = &timing1;
+		ds1bkl = &backlight;
+		fset = &fset;
+		mxcfb0 = &mxcfb0;
+		touch0 = &touch0;
+		touch1 = &touch1;
+		touch2 = &touch2;
+		display_regulator = &display_regulator;
+		ldb = &ldb;
+		mmc0 = &usdhc4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	mxcfb0: fb@0 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "ldb";
+		interface_pix_fmt = "RGB24";
+		default_bpp = <32>;
+		int_clk = <0>;
+		late_init = <0>;
+		rotation = <0>;
+		status = "okay";
+	};
+
+	lcd@0 {
+		compatible = "fsl,lcd";
+		vlcd-supply = <&display_regulator>;
+		ipu_id = <0>;
+		disp_id = <0>;
+		default_ifmt = "RGB24";
+		status = "disabled";
+
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: lcd {
+			};
+		};
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100>;
+		default-brightness-level = <0>;
+		status = "okay";
+
+		enable-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+	};
+
+	beeper: pwm-beep {
+		compatible = "pwm-beeper";
+		pwms = <&pwm3 0 0 0>;
+	};
+
+	vbus1_regulator: regulator@1 {
+		u-boot,dm-preloc;
+		compatible = "regulator-fixed";
+		regulator-name = "vbus1_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+	vbus2_regulator: regulator@2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus2_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+	usbhub_regulator: gpio-regulator@3 {
+		compatible = "regulator-gpio";
+		regulator-name = "ushbub_regulator";
+		enable-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		enable-at-boot;
+		states = <0 0 1 1>;
+	};
+	display_regulator: regulator@4 {
+		compatible = "regulator-fixed";
+		regulator-name = "display_regulator";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <1000>;
+	};
+};
+
+&fec {
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&uart1 {
+	u-boot,dm-spl;
+	u-boot,dm-preloc;
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+&ldb {
+	status = "disabled";
+	vldb-supply = <&display_regulator>;
+
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		primary;
+		status = "okay";
+		crtc = "ipu1-di0";
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: lcd {
+			};
+		};
+	};
+};
+
+&usdhc4 {
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&vbus1_regulator>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&vbus2_regulator>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	touch0: egalax_i2c@2a {
+		compatible = "eeti,egalax_i2c";
+		reg = <0x2a>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <9 2>;
+		int-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	touch1: gt911@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <9 2>;
+		irq-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+
+	touch2: i2c-hid-dev@2c {
+		compatible = "hid-over-i2c";
+		reg = <0x2c>;
+		hid-descr-addr = <0x0001>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <9 2>;
+		status = "disabled";
+	};
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&usdhc4 {
+	status = "okay";
+};
+
+&ecspi1 {
+	u-boot,dm-spl;
+	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	spi-max-frequency = <25000000>;
+
+	m25p32@1 {
+		u-boot,dm-spl;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p", "jedec,spi-nor";
+		spi-max-frequency = <25000000>;
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-kp.dts b/arch/arm/dts/imx6q-kp.dts
index 12d6db6f80..48ade9eeac 100644
--- a/arch/arm/dts/imx6q-kp.dts
+++ b/arch/arm/dts/imx6q-kp.dts
@@ -76,6 +76,11 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";
+
+	ds1307: rtc@32 {
+		compatible = "dallas,ds1307";
+		reg = <0x32>;
+	};
 };
 
 &i2c2 {
diff --git a/arch/arm/dts/imx6q-mccmon6.dts b/arch/arm/dts/imx6q-mccmon6.dts
new file mode 100644
index 0000000000..27cde56115
--- /dev/null
+++ b/arch/arm/dts/imx6q-mccmon6.dts
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q.dtsi"
+
+/ {
+	model = "Liebherr Nenzig (LWN) iMX6Q";
+	compatible = "lwn,imx6-mccmon6", "fsl,imx6";
+
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc2;
+		spi0 = &ecspi3;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@10000000 {
+		reg = <0x10000000 0x80000000>;
+	};
+};
+
+&ecspi3 {
+	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
+	spi-max-frequency = <25000000>;
+	status = "okay";
+
+	s25sl032p: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <40000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <1>;
+	/* KSZ9031 PHY SKEW setup - old values * 60 ps */
+	rxc-skew-ps = <1860>;
+	txc-skew-ps = <1860>;
+	txen-skew-ps = <900>;
+	rxdv-skew-ps = <900>;
+	rxd0-skew-ps = <180>;
+	rxd1-skew-ps = <180>;
+	rxd2-skew-ps = <180>;
+	rxd3-skew-ps = <180>;
+	txd0-skew-ps = <120>;
+	txd1-skew-ps = <300>;
+	txd2-skew-ps = <0>;
+	txd3-skew-ps = <120>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pfuze100: pmic@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3950000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "okay";
+
+	nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		use-advanced-sector-protection;
+		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi3: ecspi3grp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
+			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
+			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
+		>;
+	};
+
+	pinctrl_ecspi3_cs: ecspi3csgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
+		>;
+	};
+
+	pinctrl_ecspi3_flwp: ecspi3flwpgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
+		>;
+	};
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+			MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			MX6QDL_PAD_SD3_RST__SD3_RESET		0x17059
+		>;
+	};
+
+	pinctrl_weim_cs0: weimcs0grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
+		>;
+	};
+
+	pinctrl_weim_nor: weimnorgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
+			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
+			MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B	0xb060
+			MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
+			MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
+			MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
+			MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
+			MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
+			MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
+			MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
+			MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
+			MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
+			MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
+			MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
+			MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
+			MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
+			MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
+			MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
+			MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
+			MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
+			MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
+			MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
+			MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
+			MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
+			MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
+			MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
+			MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
+			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
+			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
+			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
+			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
+			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
+			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
+			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
+			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
+			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
+			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
+			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
+			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
+			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
+			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
+			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
+			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	keep-power-in-suspend;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi
index da8b0392ef..3f351ef0c4 100644
--- a/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi
@@ -7,6 +7,12 @@
 
 #include "imx6ul-opos6ul-u-boot.dtsi"
 
+/ {
+	aliases {
+		display0 = &lcdif;
+	};
+};
+
 &aips1 {
 	u-boot,dm-spl;
 
@@ -15,6 +21,10 @@
 	};
 };
 
+&lcdif {
+	u-boot,dm-pre-proper;
+};
+
 &pinctrl_uart1 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts b/arch/arm/dts/imx6ul-opos6uldev.dts
index 0e59ee57fd..4a541be6b0 100644
--- a/arch/arm/dts/imx6ul-opos6uldev.dts
+++ b/arch/arm/dts/imx6ul-opos6uldev.dts
@@ -187,7 +187,7 @@
 	status = "okay";
 
 	display0: display0 {
-		bits-per-pixel = <32>;
+		bits-per-pixel = <18>;
 		bus-width = <18>;
 
 		display-timings {
@@ -202,7 +202,7 @@
 				hsync-len = <64>;
 				vsync-len = <4>;
 				de-active = <1>;
-				pixelclk-active = <0>;
+				pixelclk-active = <1>;
 			};
 		};
 	};
diff --git a/arch/arm/dts/imx6ull-colibri-u-boot.dtsi b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi
new file mode 100644
index 0000000000..531cdcc4da
--- /dev/null
+++ b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+&pinctrl_uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1_ctrl1 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 262205ac5e..15338a1ae3 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -3,634 +3,10 @@
  * Copyright 2018-2019 Toradex AG
  */
 
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include "imx6ull.dtsi"
+#include "imx6ull-colibri.dtsi"
+#include "imx6ull-colibri-u-boot.dtsi"
 
 / {
 	model = "Toradex Colibri iMX6ULL";
 	compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
-
-	aliases {
-		u-boot,dm-pre-reloc;
-		mmc0 = &usdhc1;
-		usb0 = &usbotg1; /* required for ums */
-		display0 = &lcdif;
-	};
-
-	chosen {
-		stdout-path = &uart1;
-	};
-
-	reg_module_3v3: regulator-module-3v3 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-name = "+V3.3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	reg_module_3v3_avdd: regulator-module-3v3-avdd {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-name = "+V3.3_AVDD_AUDIO";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	reg_5v0: regulator-5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_sd1_vmmc: regulator-sd1-vmmc {
-		compatible = "regulator-gpio";
-		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_snvs_reg_sd>;
-		regulator-always-on;
-		regulator-name = "+V3.3_1.8_SD";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		states = <1800000 0x1 3300000 0x0>;
-		vin-supply = <&reg_module_3v3>;
-	};
-
-	reg_usbh_vbus: regulator-usbh-vbus {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh_reg>;
-		regulator-name = "VCC_USB[1-4]";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
-		vin-supply = <&reg_5v0>;
-	};
-};
-
-&adc1 {
-	num-channels = <10>;
-	vref-supply = <&reg_module_3v3_avdd>;
-};
-
-/* Colibri SPI */
-&ecspi1 {
-	cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
-};
-
-/* Ethernet */
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy1>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@2 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			max-speed = <100>;
-			reg = <2>;
-		};
-	};
-};
-
-/* NAND */
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	nand-ecc-mode = "hw";
-	nand-ecc-strength = <8>;
-	nand-ecc-step-size = <512>;
-	status = "okay";
-};
-
-/*
- * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
- */
-&i2c1 {
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	status = "okay";
-};
-
-/*
- * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
- * touch screen controller
- */
-&i2c2 {
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	pinctrl-1 = <&pinctrl_i2c2_gpio>;
-	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	status = "okay";
-
-	ad7879@2c {
-		compatible = "adi,ad7879-1";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
-		reg = <0x2c>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
-		touchscreen-max-pressure = <4096>;
-		adi,resistance-plate-x = <120>;
-		adi,first-conversion-delay = /bits/ 8 <3>;
-		adi,acquisition-time = /bits/ 8 <1>;
-		adi,median-filter-size = /bits/ 8 <2>;
-		adi,averaging = /bits/ 8 <1>;
-		adi,conversion-interval = /bits/ 8 <255>;
-	};
-};
-
-&lcdif {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lcdif_dat
-		     &pinctrl_lcdif_ctrl>;
-	status = "okay";
-	display = <&display0>;
-	u-boot,dm-pre-reloc;
-
-	display0: display0 {
-		bits-per-pixel = <18>;
-		bus-width = <24>;
-		status = "okay";
-
-		display-timings {
-			native-mode = <&timing_vga>;
-			timing_vga: 640x480 {
-				u-boot,dm-pre-reloc;
-				clock-frequency = <25175000>;
-				hactive = <640>;
-				vactive = <480>;
-				hback-porch = <48>;
-				hfront-porch = <16>;
-				vback-porch = <33>;
-				vfront-porch = <10>;
-				hsync-len = <96>;
-				vsync-len = <2>;
-
-				de-active = <1>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				pixelclk-active = <0>;
-			};
-		};
-	};
-};
-
-/* PWM <A> */
-&pwm4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm4>;
-	#pwm-cells = <3>;
-};
-
-/* PWM <B> */
-&pwm5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm5>;
-	#pwm-cells = <3>;
-};
-
-/* PWM <C> */
-&pwm6 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm6>;
-	#pwm-cells = <3>;
-};
-
-/* PWM <D> */
-&pwm7 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm7>;
-	#pwm-cells = <3>;
-};
-
-&sdma {
-	status = "okay";
-};
-
-&snvs_pwrkey {
-	status = "disabled";
-};
-
-/* Colibri UART_A */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
-	uart-has-rtscts;
-	fsl,dte-mode;
-	status = "okay";
-};
-
-/* Colibri UART_B */
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	uart-has-rtscts;
-	fsl,dte-mode;
-};
-
-/* Colibri UART_C */
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5>;
-	fsl,dte-mode;
-};
-
-/* Colibri USBC */
-&usbotg1 {
-	dr_mode = "host";
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	status = "okay";
-};
-
-/* Colibri USBH */
-&usbotg2 {
-	dr_mode = "host";
-	vbus-supply = <&reg_usbh_vbus>;
-	status = "okay";
-};
-
-/* Colibri MMC */
-&usdhc1 {
-	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
-	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
-	assigned-clock-rates = <0>, <198000000>;
-	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	vmmc-supply = <&reg_sd1_vmmc>;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_can_int: canint-grp {
-		fsl,pins = <
-			/* SODIMM 73 */
-			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14
-		>;
-	};
-
-	pinctrl_enet2: enet2-grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-		>;
-	};
-
-	pinctrl_ecspi1_cs: ecspi1-cs-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
-			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
-			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
-			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
-		>;
-	};
-
-	pinctrl_gpio_bl_on: gpio-bl-on-grp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
-		>;
-	};
-
-	pinctrl_gpio1: gpio1-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
-			MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01	0x74 /* SODIMM 63 */
-			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0X14 /* SODIMM 77 */
-			MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x14 /* SODIMM 99 */
-			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x14 /* SODIMM 133 */
-			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x14 /* SODIMM 135 */
-			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x14 /* SODIMM 100 */
-			MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x14 /* SODIMM 102 */
-			MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x14 /* SODIMM 104 */
-			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x14 /* SODIMM 186 */
-		>;
-	};
-
-	pinctrl_gpio2: gpio2-grp { /* Camera */
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x74 /* SODIMM 69 */
-			MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x14 /* SODIMM 75 */
-			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x14 /* SODIMM 85 */
-			MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x14 /* SODIMM 96 */
-			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x14 /* SODIMM 98 */
-		>;
-	};
-
-	pinctrl_gpio3: gpio3-grp { /* CAN2 */
-		fsl,pins = <
-			MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02	0x14 /* SODIMM 178 */
-			MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03	0x14 /* SODIMM 188 */
-		>;
-	};
-
-	pinctrl_gpio4: gpio4-grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x74 /* SODIMM 65 */
-		>;
-	};
-
-	pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
-		fsl,pins = <
-			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x74 /* SODIMM 106 */
-		>;
-	};
-
-	pinctrl_gpio6: gpio6-grp { /* Wifi pins */
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x14 /* SODIMM 89 */
-			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x14 /* SODIMM 79 */
-			MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x14 /* SODIMM 81 */
-			MX6UL_PAD_CSI_DATA03__GPIO4_IO24	0x14 /* SODIMM 97 */
-			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x14 /* SODIMM 101 */
-			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x14 /* SODIMM 103 */
-			MX6UL_PAD_CSI_HSYNC__GPIO4_IO20		0x14 /* SODIMM 94 */
-		>;
-	};
-
-	pinctrl_gpmi_nand: gpmi-nand-grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
-			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x100a9
-			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x100a9
-			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x100a9
-			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x100a9
-			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x100a9
-			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x100a9
-			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x100a9
-			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x100a9
-			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x100a9
-			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x100a9
-			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x100a9
-			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x100a9
-			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x100a9
-		>;
-	};
-
-	pinctrl_i2c1: i2c1-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
-			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
-		>;
-	};
-
-	pinctrl_i2c1_gpio: i2c1-gpio-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
-			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
-		>;
-	};
-
-	pinctrl_i2c2: i2c2-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
-			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
-		>;
-	};
-
-	pinctrl_i2c2_gpio: i2c2-gpio-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
-			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
-		>;
-	};
-
-	pinctrl_lcdif_dat: lcdif-dat-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
-			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
-			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
-			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
-			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
-			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
-			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
-			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
-			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
-			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
-			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
-			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
-			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
-			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
-			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
-			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
-			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
-			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
-		>;
-	};
-
-	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x00079
-			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
-			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
-			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
-		>;
-	};
-
-	pinctrl_pwm4: pwm4-grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_WP_B__PWM4_OUT	0x00079
-		>;
-	};
-
-	pinctrl_pwm5: pwm5-grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_DQS__PWM5_OUT	0x00079
-		>;
-	};
-
-	pinctrl_pwm6: pwm6-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_EN__PWM6_OUT	0x00079
-		>;
-	};
-
-	pinctrl_pwm7: pwm7-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x00079
-		>;
-	};
-
-	pinctrl_uart1: uart1-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x1b0b1
-			MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x1b0b1
-			MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x1b0b1
-			MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x1b0b1 /* DCD */
-			MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0x1b0b1 /* DSR */
-			MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x1b0b1 /* DTR */
-			MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
-		>;
-	};
-
-	pinctrl_uart2: uart2-grp {
-		fsl,pins = <
-			MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
-			MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
-			MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS	0x1b0b1
-			MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS	0x1b0b1
-		>;
-	};
-	pinctrl_uart5: uart5-grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX	0x1b0b1
-			MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX	0x1b0b1
-		>;
-	};
-
-	pinctrl_usbh_reg: gpio-usbh-reg {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x1b0b1 /* SODIMM 129 USBH PEN */
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1-grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x10059
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170b9
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100b9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170f9
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100f9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2-grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
-			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
-			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
-			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
-			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
-			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x17059
-
-			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x14
-		>;
-	};
-};
-
-&iomuxc_snvs {
-	pinctrl_snvs_gpio1: snvs-gpio1-grp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x14 /* SODIMM 93 */
-			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x14 /* SODIMM 95 */
-			MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10	0x74 /* SODIMM 105 */
-			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x14 /* SODIMM 131 USBH OC */
-			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x74 /* SODIMM 138 */
-		>;
-	};
-
-	pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x74 /* SODIMM 107 */
-		>;
-	};
-
-	pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
-		fsl,pins = <
-			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14 /* SODIMM 127 */
-		>;
-	};
-
-	pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0
-		>;
-	};
-
-	pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x4001b8b0
-		>;
-	};
-
-	pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0
-		>;
-	};
-
-	pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x130b0
-		>;
-	};
-
-	pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* CD */
-		>;
-	};
-
-	pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
-		fsl,pins = <
-			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14
-		>;
-	};
 };
diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi
new file mode 100644
index 0000000000..fca53119fe
--- /dev/null
+++ b/arch/arm/dts/imx6ull-colibri.dtsi
@@ -0,0 +1,633 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6ull.dtsi"
+
+/ {
+	aliases {
+		u-boot,dm-pre-reloc;
+		mmc0 = &usdhc1;
+		usb0 = &usbotg1; /* required for ums */
+		display0 = &lcdif;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_module_3v3_avdd: regulator-module-3v3-avdd {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-name = "+V3.3_AVDD_AUDIO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_sd1_vmmc: regulator-sd1-vmmc {
+		compatible = "regulator-gpio";
+		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_snvs_reg_sd>;
+		regulator-always-on;
+		regulator-name = "+V3.3_1.8_SD";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		states = <1800000 0x1 3300000 0x0>;
+		vin-supply = <&reg_module_3v3>;
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+		vin-supply = <&reg_5v0>;
+	};
+};
+
+&adc1 {
+	num-channels = <10>;
+	vref-supply = <&reg_module_3v3_avdd>;
+};
+
+/* Colibri SPI */
+&ecspi1 {
+	cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+};
+
+/* Ethernet */
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			max-speed = <100>;
+			reg = <2>;
+		};
+	};
+};
+
+/* NAND */
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	nand-ecc-mode = "hw";
+	nand-ecc-strength = <8>;
+	nand-ecc-step-size = <512>;
+	status = "okay";
+};
+
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c1 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	ad7879@2c {
+		compatible = "adi,ad7879-1";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
+		reg = <0x2c>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-max-pressure = <4096>;
+		adi,resistance-plate-x = <120>;
+		adi,first-conversion-delay = /bits/ 8 <3>;
+		adi,acquisition-time = /bits/ 8 <1>;
+		adi,median-filter-size = /bits/ 8 <2>;
+		adi,averaging = /bits/ 8 <1>;
+		adi,conversion-interval = /bits/ 8 <255>;
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	status = "okay";
+	display = <&display0>;
+	u-boot,dm-pre-reloc;
+
+	display0: display0 {
+		bits-per-pixel = <18>;
+		bus-width = <24>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing_vga>;
+			timing_vga: 640x480 {
+				u-boot,dm-pre-reloc;
+				clock-frequency = <25175000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hfront-porch = <16>;
+				vback-porch = <33>;
+				vfront-porch = <10>;
+				hsync-len = <96>;
+				vsync-len = <2>;
+
+				de-active = <1>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+/* PWM <A> */
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	#pwm-cells = <3>;
+};
+
+/* PWM <B> */
+&pwm5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm5>;
+	#pwm-cells = <3>;
+};
+
+/* PWM <C> */
+&pwm6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm6>;
+	#pwm-cells = <3>;
+};
+
+/* PWM <D> */
+&pwm7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm7>;
+	#pwm-cells = <3>;
+};
+
+&sdma {
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "disabled";
+};
+
+/* Colibri UART_A */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+	uart-has-rtscts;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
+	fsl,dte-mode;
+};
+
+/* Colibri UART_C */
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	fsl,dte-mode;
+};
+
+/* Colibri USBC */
+&usbotg1 {
+	dr_mode = "host";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+	dr_mode = "host";
+	vbus-supply = <&reg_usbh_vbus>;
+	status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+	assigned-clock-rates = <0>, <198000000>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_can_int: canint-grp {
+		fsl,pins = <
+			/* SODIMM 73 */
+			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14
+		>;
+	};
+
+	pinctrl_enet2: enet2-grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi1_cs: ecspi1-cs-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
+			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
+			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
+			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpio-bl-on-grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
+		>;
+	};
+
+	pinctrl_gpio1: gpio1-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
+			MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01	0x74 /* SODIMM 63 */
+			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0X14 /* SODIMM 77 */
+			MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x14 /* SODIMM 99 */
+			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x14 /* SODIMM 133 */
+			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x14 /* SODIMM 135 */
+			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x14 /* SODIMM 100 */
+			MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x14 /* SODIMM 102 */
+			MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x14 /* SODIMM 104 */
+			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x14 /* SODIMM 186 */
+		>;
+	};
+
+	pinctrl_gpio2: gpio2-grp { /* Camera */
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x74 /* SODIMM 69 */
+			MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x14 /* SODIMM 75 */
+			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x14 /* SODIMM 85 */
+			MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x14 /* SODIMM 96 */
+			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x14 /* SODIMM 98 */
+		>;
+	};
+
+	pinctrl_gpio3: gpio3-grp { /* CAN2 */
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02	0x14 /* SODIMM 178 */
+			MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03	0x14 /* SODIMM 188 */
+		>;
+	};
+
+	pinctrl_gpio4: gpio4-grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x74 /* SODIMM 65 */
+		>;
+	};
+
+	pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
+		fsl,pins = <
+			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x74 /* SODIMM 106 */
+		>;
+	};
+
+	pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x14 /* SODIMM 89 */
+			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x14 /* SODIMM 79 */
+			MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x14 /* SODIMM 81 */
+			MX6UL_PAD_CSI_DATA03__GPIO4_IO24	0x14 /* SODIMM 97 */
+			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x14 /* SODIMM 101 */
+			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x14 /* SODIMM 103 */
+			MX6UL_PAD_CSI_HSYNC__GPIO4_IO20		0x14 /* SODIMM 94 */
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpmi-nand-grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x100a9
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x100a9
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x100a9
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x100a9
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x100a9
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x100a9
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x100a9
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x100a9
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x100a9
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x100a9
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x100a9
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x100a9
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x100a9
+		>;
+	};
+
+	pinctrl_i2c1: i2c1-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2: i2c2-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2-gpio-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+		>;
+	};
+
+	pinctrl_lcdif_dat: lcdif-dat-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
+			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
+			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
+			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
+			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
+			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
+		>;
+	};
+
+	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x00079
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
+		>;
+	};
+
+	pinctrl_pwm4: pwm4-grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_WP_B__PWM4_OUT	0x00079
+		>;
+	};
+
+	pinctrl_pwm5: pwm5-grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_DQS__PWM5_OUT	0x00079
+		>;
+	};
+
+	pinctrl_pwm6: pwm6-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_EN__PWM6_OUT	0x00079
+		>;
+	};
+
+	pinctrl_pwm7: pwm7-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x00079
+		>;
+	};
+
+	pinctrl_uart1: uart1-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x1b0b1
+			MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x1b0b1
+			MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x1b0b1 /* DCD */
+			MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0x1b0b1 /* DSR */
+			MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x1b0b1 /* DTR */
+			MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
+		>;
+	};
+
+	pinctrl_uart2: uart2-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
+			MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
+			MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS	0x1b0b1
+			MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS	0x1b0b1
+		>;
+	};
+	pinctrl_uart5: uart5-grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX	0x1b0b1
+			MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbh_reg: gpio-usbh-reg {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x1b0b1 /* SODIMM 129 USBH PEN */
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1-grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x10059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170b9
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100b9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170f9
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100f9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2-grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
+			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
+			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
+			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
+			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
+			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x17059
+
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x14
+		>;
+	};
+};
+
+&iomuxc_snvs {
+	pinctrl_snvs_gpio1: snvs-gpio1-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x14 /* SODIMM 93 */
+			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x14 /* SODIMM 95 */
+			MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10	0x74 /* SODIMM 105 */
+			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x14 /* SODIMM 131 USBH OC */
+			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x74 /* SODIMM 138 */
+		>;
+	};
+
+	pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x74 /* SODIMM 107 */
+		>;
+	};
+
+	pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+		fsl,pins = <
+			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14 /* SODIMM 127 */
+		>;
+	};
+
+	pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0
+		>;
+	};
+
+	pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x4001b8b0
+		>;
+	};
+
+	pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0
+		>;
+	};
+
+	pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x130b0
+		>;
+	};
+
+	pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* CD */
+		>;
+	};
+
+	pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+		fsl,pins = <
+			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 1095d36e31..16093f2067 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -3,7 +3,7 @@
  * Copyright 2019 NXP
  */
 
-&{/soc} {
+&{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
 };
@@ -90,3 +90,23 @@
 &usdhc3 {
 	u-boot,dm-spl;
 };
+
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
index 2d5d89475b..faefb7182a 100644
--- a/arch/arm/dts/imx8mm-evk.dts
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/usb/pd.h>
 #include "imx8mm.dtsi"
 
 / {
@@ -37,6 +38,41 @@
 		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_wlf>;
+		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
+	};
+
+	sound-wm8524 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "wm8524-audio";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&cpudai>;
+		simple-audio-card,bitclock-master = <&cpudai>;
+		simple-audio-card,widgets =
+			"Line", "Left Line Out Jack",
+			"Line", "Right Line Out Jack";
+		simple-audio-card,routing =
+			"Left Line Out Jack", "LINEVOUTL",
+			"Right Line Out Jack", "LINEVOUTR";
+
+		cpudai: simple-audio-card,cpu {
+			sound-dai = <&sai3>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8524>;
+			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+		};
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
 };
 
 &fec1 {
@@ -54,19 +90,208 @@
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
-			at803x,led-act-blind-workaround;
-			at803x,eee-okay;
-			at803x,vddio-1p8v;
 		};
 	};
 };
 
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@4b {
+		compatible = "rohm,bd71847";
+		reg = <0x4b>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 GPIO_ACTIVE_LOW>;
+		rohm,reset-snvs-powered;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3_reg: BUCK3 {
+				// BUCK5 in datasheet
+				regulator-name = "BUCK3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				// BUCK6 in datasheet
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				// BUCK7 in datasheet
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				// BUCK8 in datasheet
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "LDO6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec1>;
+		reg = <0x50>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <11 8>;
+		status = "okay";
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
 &uart2 { /* console */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
 	status = "okay";
 };
 
+&usbotg1 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@@ -124,12 +349,60 @@
 		>;
 	};
 
+	pinctrl_gpio_wlf: gpiowlfgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirq {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+		>;
+	};
+
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
 		>;
 	};
 
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+		>;
+	};
+
+	pinctrl_typec1: typec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 6b407a94c0..8aafad2449 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -44,6 +44,19 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		idle-states {
+			entry-method = "psci";
+
+			cpu_pd_wait: cpu-pd-wait {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010033>;
+				local-timer-stop;
+				entry-latency-us = <1000>;
+				exit-latency-us = <700>;
+				min-residency-us = <2700>;
+			};
+		};
+
 		A53_0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
@@ -53,6 +66,9 @@
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
+			cpu-idle-states = <&cpu_pd_wait>;
 		};
 
 		A53_1: cpu@1 {
@@ -64,6 +80,7 @@
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
+			cpu-idle-states = <&cpu_pd_wait>;
 		};
 
 		A53_2: cpu@2 {
@@ -75,6 +92,7 @@
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
+			cpu-idle-states = <&cpu_pd_wait>;
 		};
 
 		A53_3: cpu@3 {
@@ -86,6 +104,7 @@
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
+			cpu-idle-states = <&cpu_pd_wait>;
 		};
 
 		A53_L2: l2-cache0 {
@@ -100,12 +119,23 @@
 		opp-1200000000 {
 			opp-hz = /bits/ 64 <1200000000>;
 			opp-microvolt = <850000>;
+			opp-supported-hw = <0xe>, <0x7>;
 			clock-latency-ns = <150000>;
+			opp-suspend;
 		};
 
 		opp-1600000000 {
 			opp-hz = /bits/ 64 <1600000000>;
 			opp-microvolt = <900000>;
+			opp-supported-hw = <0xc>, <0x7>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+
+		opp-1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1000000>;
+			opp-supported-hw = <0x8>, <0x3>;
 			clock-latency-ns = <150000>;
 			opp-suspend;
 		};
@@ -158,15 +188,6 @@
 		clock-output-names = "clk_ext4";
 	};
 
-	gic: interrupt-controller@38800000 {
-		compatible = "arm,gic-v3";
-		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
-		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
@@ -189,7 +210,23 @@
 		arm,no-tick-in-suspend;
 	};
 
-	soc {
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+		clock-names = "main_clk";
+	};
+
+	usbphynop2: usbphynop2 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+		clock-names = "main_clk";
+	};
+
+	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -199,17 +236,85 @@
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0x30000000 0x30000000 0x400000>;
+
+			sai1: sai@30010000 {
+				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+				reg = <0x30010000 0x10000>;
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
+					 <&clk IMX8MM_CLK_SAI1_ROOT>,
+					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			sai2: sai@30020000 {
+				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+				reg = <0x30020000 0x10000>;
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
+					<&clk IMX8MM_CLK_SAI2_ROOT>,
+					<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			sai3: sai@30030000 {
+				#sound-dai-cells = <0>;
+				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+				reg = <0x30030000 0x10000>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
+					 <&clk IMX8MM_CLK_SAI3_ROOT>,
+					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			sai5: sai@30050000 {
+				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+				reg = <0x30050000 0x10000>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+					 <&clk IMX8MM_CLK_SAI5_ROOT>,
+					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			sai6: sai@30060000 {
+				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+				reg = <0x30060000 0x10000>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
+					 <&clk IMX8MM_CLK_SAI6_ROOT>,
+					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
 
 			gpio1: gpio@30200000 {
 				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 				reg = <0x30200000 0x10000>;
 				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 10 30>;
 			};
 
 			gpio2: gpio@30210000 {
@@ -217,10 +322,12 @@
 				reg = <0x30210000 0x10000>;
 				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 40 21>;
 			};
 
 			gpio3: gpio@30220000 {
@@ -228,10 +335,12 @@
 				reg = <0x30220000 0x10000>;
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 61 26>;
 			};
 
 			gpio4: gpio@30230000 {
@@ -239,10 +348,12 @@
 				reg = <0x30230000 0x10000>;
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 87 32>;
 			};
 
 			gpio5: gpio@30240000 {
@@ -250,10 +361,12 @@
 				reg = <0x30240000 0x10000>;
 				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 119 30>;
 			};
 
 			wdog1: watchdog@30280000 {
@@ -313,12 +426,16 @@
 			};
 
 			ocotp: ocotp-ctrl@30350000 {
-				compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
+				compatible = "fsl,imx8mm-ocotp", "syscon";
 				reg = <0x30350000 0x10000>;
 				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
 				/* For nvmem subnodes */
 				#address-cells = <1>;
 				#size-cells = <1>;
+
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 4>;
+				};
 			};
 
 			anatop: anatop@30360000 {
@@ -336,6 +453,8 @@
 					offset = <0x34>;
 					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
+					clock-names = "snvs-rtc";
 				};
 
 				snvs_pwrkey: snvs-powerkey {
@@ -344,6 +463,7 @@
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 					linux,keycode = <KEY_POWER>;
 					wakeup-source;
+					status = "disabled";
 				};
 			};
 
@@ -355,10 +475,22 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
+				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
+						<&clk IMX8MM_CLK_AUDIO_AHB>,
+						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
+						<&clk IMX8MM_SYS_PLL3>,
+						<&clk IMX8MM_VIDEO_PLL1>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+							 <&clk IMX8MM_SYS_PLL1_800M>;
+				assigned-clock-rates = <0>,
+							<400000000>,
+							<400000000>,
+							<750000000>,
+							<594000000>;
 			};
 
 			src: reset-controller@30390000 {
-				compatible = "fsl,imx8mm-src", "syscon";
+				compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
 				reg = <0x30390000 0x10000>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
@@ -369,7 +501,7 @@
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0x30400000 0x30400000 0x400000>;
 
 			pwm1: pwm@30660000 {
 				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
@@ -414,13 +546,21 @@
 				#pwm-cells = <2>;
 				status = "disabled";
 			};
+
+			system_counter: timer@306a0000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x306a0000 0x20000>;
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_24m>;
+				clock-names = "per";
+			};
 		};
 
 		aips3: bus@30800000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0x30800000 0x30800000 0x400000>;
 
 			ecspi1: spi@30820000 {
 				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
@@ -554,7 +694,7 @@
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_DUMMY>,
+				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
@@ -570,7 +710,7 @@
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b50000 0x10000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_DUMMY>,
+				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
 				clock-names = "ipg", "ahb", "per";
@@ -584,7 +724,7 @@
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b60000 0x10000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_DUMMY>,
+				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
@@ -639,7 +779,7 @@
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0x32c00000 0x32c00000 0x400000>;
 
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
@@ -647,23 +787,13 @@
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 				clock-names = "usb1_ctrl_root_clk";
-				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
-						  <&clk IMX8MM_CLK_USB_CORE_REF>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
-							 <&clk IMX8MM_SYS_PLL1_100M>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
 				status = "disabled";
 			};
 
-			usbphynop1: usbphynop1 {
-				compatible = "usb-nop-xceiv";
-				clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
-				assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
-				clock-names = "main_clk";
-			};
-
 			usbmisc1: usbmisc@32e40200 {
 				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 				#index-cells = <1>;
@@ -676,23 +806,13 @@
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 				clock-names = "usb1_ctrl_root_clk";
-				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
-						  <&clk IMX8MM_CLK_USB_CORE_REF>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
-							 <&clk IMX8MM_SYS_PLL1_100M>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
 				status = "disabled";
 			};
 
-			usbphynop2: usbphynop2 {
-				compatible = "usb-nop-xceiv";
-				clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
-				assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
-				clock-names = "main_clk";
-			};
-
 			usbmisc2: usbmisc@32e50200 {
 				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 				#index-cells = <1>;
@@ -729,5 +849,21 @@
 			dma-names = "rx-tx";
 			status = "disabled";
 		};
+
+		gic: interrupt-controller@38800000 {
+			compatible = "arm,gic-v3";
+			reg = <0x38800000 0x10000>, /* GIC Dist */
+			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		ddr-pmu@3d800000 {
+			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
+			reg = <0x3d800000 0x400000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 };
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
new file mode 100644
index 0000000000..3693933451
--- /dev/null
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "NXP i.MX8MQ EVK";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000 0 0xc0000000>;
+	};
+
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-vsd-3v3 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2>;
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	buck2_reg: regulator-buck2 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_buck2>;
+		compatible = "regulator-gpio";
+		regulator-name = "vdd_arm";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <1000000>;
+		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		states = <1000000 0x0
+			  900000 0x1>;
+	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+	};
+
+	sound-wm8524 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "wm8524-audio";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&cpudai>;
+		simple-audio-card,bitclock-master = <&cpudai>;
+		simple-audio-card,widgets =
+			"Line", "Left Line Out Jack",
+			"Line", "Right Line Out Jack";
+		simple-audio-card,routing =
+			"Left Line Out Jack", "LINEVOUTL",
+			"Right Line Out Jack", "LINEVOUTR";
+
+		cpudai: simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+		};
+
+		link_codec: simple-audio-card,codec {
+			sound-dai = <&wm8524>;
+			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+		};
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
+	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>, <24576000>;
+	status = "okay";
+};
+
+&gpio5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wifi_reset>;
+
+	wl-reg-on {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <975000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1675000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1625000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <3075000>;
+				regulator-max-microvolt = <3625000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
+		 <&pcie0_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	status = "okay";
+};
+
+&pgc_gpu {
+	power-supply = <&sw1a_reg>;
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	n25q256a: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vqmmc-supply = <&sw4_reg>;
+	bus-width = <8>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_buck2: vddarmgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
+		>;
+
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
+			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
+		>;
+	};
+
+	pinctrl_qspi: qspigrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+
+		>;
+	};
+
+	pinctrl_reg_usdhc2: regusdhc2grpgpio {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
+		>;
+	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
+			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_wdog: wdog1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+
+	pinctrl_wifi_reset: wifiresetgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
new file mode 100644
index 0000000000..621e9593ec
--- /dev/null
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -0,0 +1,1111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/pinctrl/pins-imx8mq.h>
+#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "dt-bindings/input/input.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&gpc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
+	};
+
+	ckil: clock-ckil {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ckil";
+	};
+
+	osc_25m: clock-osc-25m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "osc_25m";
+	};
+
+	osc_27m: clock-osc-27m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+		clock-output-names = "osc_27m";
+	};
+
+	clk_ext1: clock-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	clk_ext2: clock-ext2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext2";
+	};
+
+	clk_ext3: clock-ext3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext3";
+	};
+
+	clk_ext4: clock-ext4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency= <133000000>;
+		clock-output-names = "clk_ext4";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A53_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MQ_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+			#cooling-cells = <2>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
+		};
+
+		A53_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MQ_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		A53_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MQ_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		A53_3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MQ_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		A53_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	a53_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <900000>;
+			/* Industrial only */
+			opp-supported-hw = <0xf>, <0x4>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <900000>;
+			/* Consumer only */
+			opp-supported-hw = <0xe>, <0x3>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+
+		opp-1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1000000>;
+			opp-supported-hw = <0xc>, <0x4>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1000000>;
+			opp-supported-hw = <0x8>, <0x3>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu 0>;
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <80000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu 1>;
+
+			trips {
+				gpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		vpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu 2>;
+
+			trips {
+				vpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+		interrupt-parent = <&gic>;
+		arm,no-tick-in-suspend;
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x3e000000>;
+		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
+
+		bus@30000000 { /* AIPS1 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30000000 0x30000000 0x400000>;
+
+			gpio1: gpio@30200000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30200000 0x10000>;
+				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 10 30>;
+			};
+
+			gpio2: gpio@30210000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30210000 0x10000>;
+				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 40 21>;
+			};
+
+			gpio3: gpio@30220000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30220000 0x10000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 61 26>;
+			};
+
+			gpio4: gpio@30230000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30230000 0x10000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 87 32>;
+			};
+
+			gpio5: gpio@30240000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30240000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 119 30>;
+			};
+
+			tmu: tmu@30260000 {
+				compatible = "fsl,imx8mq-tmu";
+				reg = <0x30260000 0x10000>;
+				interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
+				little-endian;
+				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+				fsl,tmu-calibration = <0x00000000 0x00000023
+						       0x00000001 0x00000029
+						       0x00000002 0x0000002f
+						       0x00000003 0x00000035
+						       0x00000004 0x0000003d
+						       0x00000005 0x00000043
+						       0x00000006 0x0000004b
+						       0x00000007 0x00000051
+						       0x00000008 0x00000057
+						       0x00000009 0x0000005f
+						       0x0000000a 0x00000067
+						       0x0000000b 0x0000006f
+
+						       0x00010000 0x0000001b
+						       0x00010001 0x00000023
+						       0x00010002 0x0000002b
+						       0x00010003 0x00000033
+						       0x00010004 0x0000003b
+						       0x00010005 0x00000043
+						       0x00010006 0x0000004b
+						       0x00010007 0x00000055
+						       0x00010008 0x0000005d
+						       0x00010009 0x00000067
+						       0x0001000a 0x00000070
+
+						       0x00020000 0x00000017
+						       0x00020001 0x00000023
+						       0x00020002 0x0000002d
+						       0x00020003 0x00000037
+						       0x00020004 0x00000041
+						       0x00020005 0x0000004b
+						       0x00020006 0x00000057
+						       0x00020007 0x00000063
+						       0x00020008 0x0000006f
+
+						       0x00030000 0x00000015
+						       0x00030001 0x00000021
+						       0x00030002 0x0000002d
+						       0x00030003 0x00000039
+						       0x00030004 0x00000045
+						       0x00030005 0x00000053
+						       0x00030006 0x0000005f
+						       0x00030007 0x00000071>;
+				#thermal-sensor-cells =  <1>;
+			};
+
+			wdog1: watchdog@30280000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x30280000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+				status = "disabled";
+			};
+
+			wdog2: watchdog@30290000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x30290000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+				status = "disabled";
+			};
+
+			wdog3: watchdog@302a0000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x302a0000 0x10000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+				status = "disabled";
+			};
+
+			sdma2: sdma@302c0000 {
+				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
+				reg = <0x302c0000 0x10000>;
+				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
+					 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			iomuxc: iomuxc@30330000 {
+				compatible = "fsl,imx8mq-iomuxc";
+				reg = <0x30330000 0x10000>;
+			};
+
+			iomuxc_gpr: syscon@30340000 {
+				compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
+					     "syscon", "simple-mfd";
+				reg = <0x30340000 0x10000>;
+
+				mux: mux-controller {
+					compatible = "mmio-mux";
+					#mux-control-cells = <1>;
+					mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
+				};
+			};
+
+			ocotp: ocotp-ctrl@30350000 {
+				compatible = "fsl,imx8mq-ocotp", "syscon";
+				reg = <0x30350000 0x10000>;
+				clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 4>;
+				};
+			};
+
+			anatop: syscon@30360000 {
+				compatible = "fsl,imx8mq-anatop", "syscon";
+				reg = <0x30360000 0x10000>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			snvs: snvs@30370000 {
+				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+				reg = <0x30370000 0x10000>;
+
+				snvs_rtc: snvs-rtc-lp{
+					compatible = "fsl,sec-v4.0-mon-rtc-lp";
+					regmap =<&snvs>;
+					offset = <0x34>;
+					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
+					clock-names = "snvs-rtc";
+				};
+
+				snvs_pwrkey: snvs-powerkey {
+					compatible = "fsl,sec-v4.0-pwrkey";
+					regmap = <&snvs>;
+					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					linux,keycode = <KEY_POWER>;
+					wakeup-source;
+					status = "disabled";
+				};
+			};
+
+			clk: clock-controller@30380000 {
+				compatible = "fsl,imx8mq-ccm";
+				reg = <0x30380000 0x10000>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				#clock-cells = <1>;
+				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
+				         <&clk_ext1>, <&clk_ext2>,
+				         <&clk_ext3>, <&clk_ext4>;
+				clock-names = "ckil", "osc_25m", "osc_27m",
+				              "clk_ext1", "clk_ext2",
+				              "clk_ext3", "clk_ext4";
+			};
+
+			src: reset-controller@30390000 {
+				compatible = "fsl,imx8mq-src", "syscon";
+				reg = <0x30390000 0x10000>;
+				#reset-cells = <1>;
+			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mq-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_mipi: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI>;
+					};
+
+					/*
+					 * As per comment in ATF source code:
+					 *
+					 * PCIE1 and PCIE2 share the
+					 * same reset signal, if we
+					 * power down PCIE2, PCIE1
+					 * will be held in reset too.
+					 *
+					 * So instead of creating two
+					 * separate power domains for
+					 * PCIE1 and PCIE2 we create a
+					 * link between both and use
+					 * it as a shared PCIE power
+					 * domain.
+					 */
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+						power-domains = <&pgc_pcie2>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
+					};
+
+					pgc_ddr1: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_DDR1>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_GPU>;
+						clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+						         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+							 <&clk IMX8MQ_CLK_GPU_AXI>,
+						         <&clk IMX8MQ_CLK_GPU_AHB>;
+					};
+
+					pgc_vpu: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_VPU>;
+					};
+
+					pgc_disp: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_DISP>;
+					};
+
+					pgc_mipi_csi1: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
+					};
+
+					pgc_mipi_csi2: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
+					};
+
+					pgc_pcie2: power-domain@a {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_PCIE2>;
+					};
+				};
+			};
+		};
+
+		bus@30400000 { /* AIPS2 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30400000 0x30400000 0x400000>;
+
+			pwm1: pwm@30660000 {
+				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+				reg = <0x30660000 0x10000>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
+				         <&clk IMX8MQ_CLK_PWM1_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm2: pwm@30670000 {
+				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+				reg = <0x30670000 0x10000>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
+				         <&clk IMX8MQ_CLK_PWM2_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm3: pwm@30680000 {
+				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+				reg = <0x30680000 0x10000>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
+				         <&clk IMX8MQ_CLK_PWM3_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm4: pwm@30690000 {
+				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+				reg = <0x30690000 0x10000>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
+				         <&clk IMX8MQ_CLK_PWM4_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			system_counter: timer@306a0000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x306a0000 0x20000>;
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_25m>;
+				clock-names = "per";
+			};
+		};
+
+		bus@30800000 { /* AIPS3 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30800000 0x30800000 0x400000>,
+				 <0x08000000 0x08000000 0x10000000>;
+
+			ecspi1: spi@30820000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x30820000 0x10000>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			ecspi2: spi@30830000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x30830000 0x10000>;
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			ecspi3: spi@30840000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x30840000 0x10000>;
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart1: serial@30860000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30860000 0x10000>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
+				         <&clk IMX8MQ_CLK_UART1_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart3: serial@30880000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30880000 0x10000>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
+				         <&clk IMX8MQ_CLK_UART3_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart2: serial@30890000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30890000 0x10000>;
+				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
+				         <&clk IMX8MQ_CLK_UART2_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			sai2: sai@308b0000 {
+				#sound-dai-cells = <0>;
+				compatible = "fsl,imx8mq-sai";
+				reg = <0x308b0000 0x10000>;
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
+					 <&clk IMX8MQ_CLK_SAI2_ROOT>,
+					 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			crypto: crypto@30900000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x30900000 0x40000>;
+				ranges = <0 0x30900000 0x40000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_AHB>,
+					 <&clk IMX8MQ_CLK_IPG_ROOT>;
+				clock-names = "aclk", "ipg";
+
+				sec_jr0: jr@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
+			dphy: dphy@30a00300 {
+				compatible = "fsl,imx8mq-mipi-dphy";
+				reg = <0x30a00300 0x100>;
+				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+				clock-names = "phy_ref";
+				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <24000000>;
+				#phy-cells = <0>;
+				power-domains = <&pgc_mipi>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@30a20000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a20000 0x10000>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@30a30000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a30000 0x10000>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@30a40000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a40000 0x10000>;
+				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@30a50000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a50000 0x10000>;
+				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart4: serial@30a60000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30a60000 0x10000>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
+				         <&clk IMX8MQ_CLK_UART4_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			usdhc1: mmc@30b40000 {
+				compatible = "fsl,imx8mq-usdhc",
+				             "fsl,imx7d-usdhc";
+				reg = <0x30b40000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DUMMY>,
+				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
+				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+				assigned-clock-rates = <400000000>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step = <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc2: mmc@30b50000 {
+				compatible = "fsl,imx8mq-usdhc",
+				             "fsl,imx7d-usdhc";
+				reg = <0x30b50000 0x10000>;
+				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DUMMY>,
+				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
+				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step = <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			qspi0: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
+				reg = <0x30bb0000 0x10000>,
+				      <0x08000000 0x10000000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
+					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
+				clock-names = "qspi_en", "qspi";
+				status = "disabled";
+			};
+
+			sdma1: sdma@30bd0000 {
+				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
+				reg = <0x30bd0000 0x10000>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
+					 <&clk IMX8MQ_CLK_AHB>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			fec1: ethernet@30be0000 {
+				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+				reg = <0x30be0000 0x10000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
+				         <&clk IMX8MQ_CLK_ENET_TIMER>,
+				         <&clk IMX8MQ_CLK_ENET_REF>,
+				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
+				clock-names = "ipg", "ahb", "ptp",
+				              "enet_clk_ref", "enet_out";
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
+				status = "disabled";
+			};
+		};
+
+		bus@32c00000 { /* AIPS4 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x32c00000 0x32c00000 0x400000>;
+
+			irqsteer: interrupt-controller@32e2d000 {
+				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
+				reg = <0x32e2d000 0x1000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+				clock-names = "ipg";
+				fsl,channel = <0>;
+				fsl,num-irqs = <64>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		gpu: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x40000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+			         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+			         <&clk IMX8MQ_CLK_GPU_AXI>,
+			         <&clk IMX8MQ_CLK_GPU_AHB>;
+			clock-names = "core", "shader", "bus", "reg";
+			assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+			                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+			                  <&clk IMX8MQ_CLK_GPU_AXI>,
+			                  <&clk IMX8MQ_CLK_GPU_AHB>,
+			                  <&clk IMX8MQ_GPU_PLL_BYPASS>;
+			assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL>;
+			assigned-clock-rates = <800000000>, <800000000>,
+			                       <800000000>, <800000000>, <0>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		usb_dwc3_0: usb@38100000 {
+			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+			reg = <0x38100000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
+			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
+				 <&clk IMX8MQ_CLK_32K>;
+			clock-names = "bus_early", "ref", "suspend";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                         <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb3_phy0>, <&usb3_phy0>;
+			phy-names = "usb2-phy", "usb3-phy";
+			power-domains = <&pgc_otg1>;
+			usb3-resume-missing-cas;
+			status = "disabled";
+		};
+
+		usb3_phy0: usb-phy@381f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb_dwc3_1: usb@38200000 {
+			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+			reg = <0x38200000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
+			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
+				 <&clk IMX8MQ_CLK_32K>;
+			clock-names = "bus_early", "ref", "suspend";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                         <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb3_phy1>, <&usb3_phy1>;
+			phy-names = "usb2-phy", "usb3-phy";
+			power-domains = <&pgc_otg2>;
+			usb3-resume-missing-cas;
+			status = "disabled";
+		};
+
+		usb3_phy1: usb-phy@382f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie0: pcie@33800000 {
+			compatible = "fsl,imx8mq-pcie";
+			reg = <0x33800000 0x400000>,
+			      <0x1ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+			          0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY>,
+			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "turnoff";
+			status = "disabled";
+		};
+
+		pcie1: pcie@33c00000 {
+			compatible = "fsl,imx8mq-pcie";
+			reg = <0x33c00000 0x400000>,
+			      <0x27f00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+				   0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "turnoff";
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@38800000 {
+			compatible = "arm,gic-v3";
+			reg = <0x38800000 0x10000>,	/* GIC Dist */
+			      <0x38880000 0xc0000>,	/* GICR */
+			      <0x31000000 0x2000>,	/* GICC */
+			      <0x31010000 0x2000>,	/* GICV */
+			      <0x31020000 0x2000>;	/* GICH */
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+		};
+
+		ddr-pmu@3d800000 {
+			compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
+			reg = <0x3d800000 0x400000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts
new file mode 100644
index 0000000000..5f9ac955ed
--- /dev/null
+++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+	model = "Advantech iMX8QM Qseven series";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		stdout-path = &lpuart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+		user {
+			label = "heartbeat";
+			gpios = <&gpio2 15 0>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx8qm-mek {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
+				/* WP */
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11		0x00000021
+				/* CD */
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
+				/*
+				 * Change the default alt function from SCL/SDA to others,
+				 * to avoid select input conflict with GPT0
+				 */
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
+			>;
+		};
+
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15		0x00000021
+			>;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	pca9557_a: gpio@18 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_b: gpio@19 {
+		compatible = "nxp,pca9557";
+		reg = <0x19>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_c: gpio@1b {
+		compatible = "nxp,pca9557";
+		reg = <0x1b>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_d: gpio@1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 9fa9eb2687..38a6f5966b 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -421,4 +421,6 @@ enum frac_pll_out_val {
 	FRAC_PLL_OUT_1000M,
 	FRAC_PLL_OUT_1600M,
 };
+
+void init_nand_clk(void);
 #endif
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index a9481a5fea..f7760541a4 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -71,6 +71,7 @@ int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
+void disable_ipu_clock(void);
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 int enable_lcdif_clock(u32 base_addr, bool enable);
diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
index 033659a038..907e7ed8f9 100644
--- a/arch/arm/include/asm/mach-imx/imx-nandbcb.h
+++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
@@ -106,6 +106,18 @@ struct fcb_block {
 
 	/* The swap position of main area in spare area */
 	u32 spare_offset;
+
+	/* Actual for iMX7 only */
+	u32 onfi_sync_enable;
+	u32 onfi_sync_speed;
+	u32 onfi_sync_nand_data;
+	u32 reserved2[6];
+	u32 disbbm_search;
+	u32 disbbm_search_limit;
+	u32 reserved3[15];
+	u32 read_retry_enable;
+	u32 reserved4[1];
+	u32 fill_to_1024[183];
 };
 
 #endif	/* _IMX_NAND_BCB_H_ */
diff --git a/arch/arm/include/asm/mach-imx/regs-gpmi.h b/arch/arm/include/asm/mach-imx/regs-gpmi.h
index 80cb731724..33daa53c45 100644
--- a/arch/arm/include/asm/mach-imx/regs-gpmi.h
+++ b/arch/arm/include/asm/mach-imx/regs-gpmi.h
@@ -70,6 +70,11 @@ struct mxs_gpmi_regs {
 #define	GPMI_ECCCTRL_ECC_CMD_OFFSET			13
 #define	GPMI_ECCCTRL_ECC_CMD_DECODE			(0x0 << 13)
 #define	GPMI_ECCCTRL_ECC_CMD_ENCODE			(0x1 << 13)
+#define	GPMI_ECCCTRL_RANDOMIZER_ENABLE			(1 << 11)
+#define	GPMI_ECCCTRL_RANDOMIZER_TYPE0			0
+#define	GPMI_ECCCTRL_RANDOMIZER_TYPE1			(1 << 9)
+#define	GPMI_ECCCTRL_RANDOMIZER_TYPE2			(2 << 9)
+
 #define	GPMI_ECCCTRL_ENABLE_ECC				(1 << 12)
 #define	GPMI_ECCCTRL_BUFFER_MASK_MASK			0x1ff
 #define	GPMI_ECCCTRL_BUFFER_MASK_OFFSET			0
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index aa66fdc88f..1e627c8fc3 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -99,11 +99,6 @@ enum imx6_bmode {
 	IMX6_BMODE_NAND_MAX = 0xf,
 };
 
-static inline u8 imx6_is_bmode_from_gpr9(void)
-{
-	return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
-}
-
 u32 imx6_src_get_boot_mode(void);
 void gpr_init(void);
 
@@ -143,7 +138,8 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
-			   unsigned long reg1, unsigned long reg2);
+			   unsigned long reg1, unsigned long reg2,
+			   unsigned long reg3);
 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
 				unsigned long *reg1, unsigned long reg2,
 				unsigned long reg3);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b0b9d2c070..3f93fe5174 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -81,7 +81,8 @@ config CMD_HDMIDETECT
 config CMD_NANDBCB
 	bool "i.MX6 NAND Boot Control Block(BCB) command"
 	depends on NAND && CMD_MTDPARTS
-	default y if ARCH_MX6 && NAND_MXS
+	select BCH if MX6UL || MX6ULL
+	default y if (ARCH_MX6 && NAND_MXS) || (ARCH_MX7 && NAND_MXS)
 	help
 	  Unlike normal 'nand write/erase' commands, this command update
 	  Boot Control Block(BCB) for i.MX6 platform NAND IP's.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9dfe883ead..6e87dc58a0 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -155,10 +155,8 @@ ifeq ($(DEPFILE_EXISTS),0)
 endif
 
 flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
-ifeq ($(DEPFILE_EXISTS),0)
 	$(call if_changed,mkimage)
 endif
-endif
 
 ifeq ($(CONFIG_ARCH_IMX8), y)
 SPL:
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 7811c61d22..09c4356529 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,8 +14,10 @@
 
 #include <asm/io.h>
 #include <jffs2/jffs2.h>
+#include <linux/bch.h>
 #include <linux/mtd/mtd.h>
 
+#include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/imx-nandbcb.h>
 #include <asm/mach-imx/imximage.cfg>
 #include <mxs_nand.h>
@@ -25,6 +27,68 @@
 #define BF_VAL(v, bf)		(((v) & bf##_MASK) >> bf##_OFFSET)
 #define GETBIT(v, n)		(((v) >> (n)) & 0x1)
 
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+static uint8_t reverse_bit(uint8_t b)
+{
+	b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+	b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+	b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+	return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+	int i, j, m = 13;
+	int blocksize = 128;
+	int numblocks = 8;
+	int ecc_buf_size = (m * eccbits + 7) / 8;
+	struct bch_control *bch = init_bch(m, eccbits, 0);
+	u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+	u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+	u8 *psrc, *pdst;
+
+	/*
+	 * The blocks here are bit aligned. If eccbits is a multiple of 8,
+	 * we just can copy bytes. Otherwiese we must move the blocks to
+	 * the next free bit position.
+	 */
+	WARN_ON(eccbits % 8);
+
+	memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+	for (i = 0; i < numblocks; i++) {
+		memset(ecc_buf, 0, ecc_buf_size);
+		psrc = tmp_buf + i * blocksize;
+		pdst = buf + i * (blocksize + ecc_buf_size);
+
+		/* copy data byte aligned to destination buf */
+		memcpy(pdst, psrc, blocksize);
+
+		/*
+		 * imx-kobs use a modified encode_bch which reverse the
+		 * bit order of the data before calculating bch.
+		 * Do this in the buffer and use the bch lib here.
+		 */
+		for (j = 0; j < blocksize; j++)
+			psrc[j] = reverse_bit(psrc[j]);
+
+		encode_bch(bch, psrc, blocksize, ecc_buf);
+
+		/* reverse ecc bit */
+		for (j = 0; j < ecc_buf_size; j++)
+			ecc_buf[j] = reverse_bit(ecc_buf[j]);
+
+		/* Here eccbuf is byte aligned and we can just copy it */
+		memcpy(pdst + blocksize, ecc_buf, ecc_buf_size);
+	}
+
+	kfree(ecc_buf);
+	kfree(tmp_buf);
+	free_bch(bch);
+}
+#else
+
 static u8 calculate_parity_13_8(u8 d)
 {
 	u8 p = 0;
@@ -50,6 +114,7 @@ static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
 	for (i = 0; i < size; i++)
 		ecc[i] = calculate_parity_13_8(src[i]);
 }
+#endif
 
 static u32 calc_chksum(void *buf, size_t size)
 {
@@ -63,30 +128,41 @@ static u32 calc_chksum(void *buf, size_t size)
 	return ~chksum;
 }
 
-static void fill_fcb(struct fcb_block *fcb, struct mtd_info *mtd)
+static void fill_fcb(struct fcb_block *fcb, struct mtd_info *mtd,
+		     u32 fw1_start, u32 fw2_start, u32 fw_pages)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
+	struct mxs_nand_layout l;
+
+	mxs_nand_get_layout(mtd, &l);
 
 	fcb->fingerprint = FCB_FINGERPRINT;
 	fcb->version = FCB_VERSION_1;
+
 	fcb->pagesize = mtd->writesize;
 	fcb->oob_pagesize = mtd->writesize + mtd->oobsize;
 	fcb->sectors = mtd->erasesize / mtd->writesize;
 
-	/* Divide ECC strength by two and save the value into FCB structure. */
-	fcb->ecc_level = nand_info->bch_geometry.ecc_strength >> 1;
-
-	fcb->ecc_type = fcb->ecc_level;
+	fcb->meta_size = l.meta_size;
+	fcb->nr_blocks = l.nblocks;
+	fcb->ecc_nr = l.data0_size;
+	fcb->ecc_level = l.ecc0;
+	fcb->ecc_size = l.datan_size;
+	fcb->ecc_type = l.eccn;
 
 	/* Also hardcoded in kobs-ng */
-	fcb->ecc_nr = 0x00000200;
-	fcb->ecc_size = 0x00000200;
-	fcb->datasetup = 80;
-	fcb->datahold = 60;
-	fcb->addr_setup = 25;
-	fcb->dsample_time = 6;
-	fcb->meta_size = 10;
+	if (is_mx6()) {
+		fcb->datasetup = 80;
+		fcb->datahold = 60;
+		fcb->addr_setup = 25;
+		fcb->dsample_time = 6;
+	} else if (is_mx7()) {
+		fcb->datasetup = 10;
+		fcb->datahold = 7;
+		fcb->addr_setup = 15;
+		fcb->dsample_time = 6;
+	}
 
 	/* DBBT search area starts at second page on first block */
 	fcb->dbbt_start = 1;
@@ -98,6 +174,14 @@ static void fill_fcb(struct fcb_block *fcb, struct mtd_info *mtd)
 
 	fcb->nr_blocks = mtd->writesize / fcb->ecc_nr - 1;
 
+	fcb->disbbm = 0;
+	fcb->disbbm_search = 0;
+
+	fcb->fw1_start = fw1_start; /* Firmware image starts on this sector */
+	fcb->fw2_start = fw2_start; /* Secondary FW Image starting Sector */
+	fcb->fw1_pages = fw_pages; /* Number of sectors in firmware image */
+	fcb->fw2_pages = fw_pages; /* Number of sector in secondary FW image */
+
 	fcb->checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4);
 }
 
@@ -121,6 +205,114 @@ static int dbbt_fill_data(struct mtd_info *mtd, void *buf, int num_blocks)
 	return n_bad_blocks;
 }
 
+static int write_fcb_dbbt(struct mtd_info *mtd, struct fcb_block *fcb,
+			  struct dbbt_block *dbbt, void *dbbt_data_page,
+			  loff_t off)
+{
+	void *fcb_raw_page = 0;
+	int i, ret;
+	size_t dummy;
+
+	/*
+	 * We prepare raw page only for i.MX6, for i.MX7 we
+	 * leverage BCH hw module instead
+	 */
+	if (is_mx6()) {
+		/* write fcb/dbbt */
+		fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize,
+				       GFP_KERNEL);
+		if (!fcb_raw_page) {
+			debug("failed to allocate fcb_raw_page\n");
+			ret = -ENOMEM;
+			return ret;
+		}
+
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+		/* 40 bit BCH, for i.MX6UL(L) */
+		encode_bch_ecc(fcb_raw_page + 32, fcb, 40);
+#else
+		memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
+		encode_hamming_13_8(fcb_raw_page + 12,
+				    fcb_raw_page + 12 + 512, 512);
+#endif
+		/*
+		 * Set the first and second byte of OOB data to 0xFF,
+		 * not 0x00. These bytes are used as the Manufacturers Bad
+		 * Block Marker (MBBM). Since the FCB is mostly written to
+		 * the first page in a block, a scan for
+		 * factory bad blocks will detect these blocks as bad, e.g.
+		 * when function nand_scan_bbt() is executed to build a new
+		 * bad block table.
+		 */
+		memset(fcb_raw_page + mtd->writesize, 0xFF, 2);
+	}
+	for (i = 0; i < 2; i++) {
+		if (mtd_block_isbad(mtd, off)) {
+			printf("Block %d is bad, skipped\n", i);
+			continue;
+		}
+
+		/*
+		 * User BCH ECC hardware module for i.MX7
+		 */
+		if (is_mx7()) {
+			u32 off = i * mtd->erasesize;
+			size_t rwsize = sizeof(*fcb);
+
+			printf("Writing %d bytes to 0x%x: ", rwsize, off);
+
+			/* switch nand BCH to FCB compatible settings */
+			mxs_nand_mode_fcb(mtd);
+			ret = nand_write(mtd, off, &rwsize,
+					 (unsigned char *)fcb);
+			mxs_nand_mode_normal(mtd);
+
+			printf("%s\n", ret ? "ERROR" : "OK");
+		} else if (is_mx6()) {
+			/* raw write */
+			mtd_oob_ops_t ops = {
+				.datbuf = (u8 *)fcb_raw_page,
+				.oobbuf = ((u8 *)fcb_raw_page) +
+					  mtd->writesize,
+				.len = mtd->writesize,
+				.ooblen = mtd->oobsize,
+				.mode = MTD_OPS_RAW
+			};
+
+			ret = mtd_write_oob(mtd, mtd->erasesize * i, &ops);
+			if (ret)
+				goto fcb_raw_page_err;
+			debug("NAND fcb write: 0x%x offset 0x%x written: %s\n",
+			      mtd->erasesize * i, ops.len, ret ?
+			      "ERROR" : "OK");
+		}
+
+		ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize,
+				mtd->writesize, &dummy, (void *)dbbt);
+		if (ret)
+			goto fcb_raw_page_err;
+		debug("NAND dbbt write: 0x%x offset, 0x%x bytes written: %s\n",
+		      mtd->erasesize * i + mtd->writesize, dummy,
+		      ret ? "ERROR" : "OK");
+
+		/* dbbtpages == 0 if no bad blocks */
+		if (dbbt->dbbtpages > 0) {
+			loff_t to = (mtd->erasesize * i + mtd->writesize * 5);
+
+			ret = mtd_write(mtd, to, mtd->writesize, &dummy,
+					dbbt_data_page);
+			if (ret)
+				goto fcb_raw_page_err;
+		}
+	}
+
+fcb_raw_page_err:
+	if (is_mx6())
+		kfree(fcb_raw_page);
+
+	return ret;
+}
+
 static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size,
 			  size_t maxsize, const u_char *buf)
 {
@@ -128,10 +320,11 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size,
 	struct fcb_block *fcb;
 	struct dbbt_block *dbbt;
 	loff_t fw1_off;
-	void *fwbuf, *fcb_raw_page, *dbbt_page, *dbbt_data_page;
+	void *fwbuf, *dbbt_page, *dbbt_data_page;
+	u32 fw1_start, fw1_pages;
 	int nr_blks, nr_blks_fcb, fw1_blk;
-	size_t fwsize, dummy;
-	int i, ret;
+	size_t fwsize;
+	int ret;
 
 	/* erase */
 	memset(&opts, 0, sizeof(opts));
@@ -194,9 +387,9 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size,
 		goto fwbuf_err;
 	}
 
-	fcb->fw1_start = (fw1_blk * mtd->erasesize) / mtd->writesize;
-	fcb->fw1_pages = size / mtd->writesize + 1;
-	fill_fcb(fcb, mtd);
+	fw1_start = (fw1_blk * mtd->erasesize) / mtd->writesize;
+	fw1_pages = size / mtd->writesize + 1;
+	fill_fcb(fcb, mtd, fw1_start, 0, fw1_pages);
 
 	/* fill dbbt */
 	dbbt_page = kzalloc(mtd->writesize, GFP_KERNEL);
@@ -223,77 +416,103 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size,
 	else if (ret > 0)
 		dbbt->dbbtpages = 1;
 
-	/* write fcb/dbbt */
-	fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
-	if (!fcb_raw_page) {
-		debug("failed to allocate fcb_raw_page\n");
-		ret = -ENOMEM;
-		goto dbbt_data_page_err;
+	/* write fcb and dbbt to nand */
+	ret = write_fcb_dbbt(mtd, fcb, dbbt, dbbt_data_page, off);
+	if (ret < 0)
+		printf("failed to write FCB/DBBT\n");
+
+dbbt_data_page_err:
+	kfree(dbbt_data_page);
+dbbt_page_err:
+	kfree(dbbt_page);
+fcb_err:
+	kfree(fcb);
+fwbuf_err:
+	kfree(fwbuf);
+err:
+	return ret;
+}
+
+static int do_nandbcb_bcbonly(int argc, char * const argv[])
+{
+	struct fcb_block *fcb;
+	struct dbbt_block *dbbt;
+	u32 fw_len, fw1_off, fw2_off;
+	struct mtd_info *mtd;
+	void *dbbt_page, *dbbt_data_page;
+	int dev, ret;
+
+	dev = nand_curr_device;
+	if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
+	    (!get_nand_dev_by_index(dev))) {
+		puts("No devices available\n");
+		return CMD_RET_FAILURE;
 	}
 
-	memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
-	encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
-	/*
-	 * Set the first and second byte of OOB data to 0xFF, not 0x00. These
-	 * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since
-	 * the FCB is mostly written to the first page in a block, a scan for
-	 * factory bad blocks will detect these blocks as bad, e.g. when
-	 * function nand_scan_bbt() is executed to build a new bad block table.
-	 */
-	memset(fcb_raw_page + mtd->writesize, 0xFF, 2);
+	mtd = get_nand_dev_by_index(dev);
 
-	for (i = 0; i < nr_blks_fcb; i++) {
-		if (mtd_block_isbad(mtd, off)) {
-			printf("Block %d is bad, skipped\n", i);
-			continue;
-		}
+	if (argc < 3)
+		return CMD_RET_FAILURE;
 
-		/* raw write */
-		mtd_oob_ops_t ops = {
-			.datbuf = (u8 *)fcb_raw_page,
-			.oobbuf = ((u8 *)fcb_raw_page) + mtd->writesize,
-			.len = mtd->writesize,
-			.ooblen = mtd->oobsize,
-			.mode = MTD_OPS_RAW
-		};
+	fw_len = simple_strtoul(argv[1], NULL, 16);
+	fw1_off = simple_strtoul(argv[2], NULL, 16);
 
-		ret = mtd_write_oob(mtd, mtd->erasesize * i, &ops);
-		if (ret)
-			goto fcb_raw_page_err;
-		debug("NAND fcb write: 0x%x offset, 0x%x bytes written: %s\n",
-		      mtd->erasesize * i, ops.len, ret ? "ERROR" : "OK");
+	if (argc > 3)
+		fw2_off = simple_strtoul(argv[3], NULL, 16);
+	else
+		fw2_off = fw1_off;
 
-		ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize,
-				mtd->writesize, &dummy, dbbt_page);
-		if (ret)
-			goto fcb_raw_page_err;
-		debug("NAND dbbt write: 0x%x offset, 0x%x bytes written: %s\n",
-		      mtd->erasesize * i + mtd->writesize, dummy,
-		      ret ? "ERROR" : "OK");
+	/* fill fcb */
+	fcb = kzalloc(sizeof(*fcb), GFP_KERNEL);
+	if (!fcb) {
+		debug("failed to allocate fcb\n");
+		ret = -ENOMEM;
+		return CMD_RET_FAILURE;
+	}
 
-		/* dbbtpages == 0 if no bad blocks */
-		if (dbbt->dbbtpages > 0) {
-			loff_t to = (mtd->erasesize * i + mtd->writesize * 5);
+	fill_fcb(fcb, mtd, fw1_off / mtd->writesize,
+		 fw2_off / mtd->writesize, fw_len / mtd->writesize);
 
-			ret = mtd_write(mtd, to, mtd->writesize, &dummy,
-					dbbt_data_page);
-			if (ret)
-				goto fcb_raw_page_err;
-		}
+	/* fill dbbt */
+	dbbt_page = kzalloc(mtd->writesize, GFP_KERNEL);
+	if (!dbbt_page) {
+		debug("failed to allocate dbbt_page\n");
+		ret = -ENOMEM;
+		goto fcb_err;
 	}
 
-fcb_raw_page_err:
-	kfree(fcb_raw_page);
+	dbbt_data_page = kzalloc(mtd->writesize, GFP_KERNEL);
+	if (!dbbt_data_page) {
+		debug("failed to allocate dbbt_data_page\n");
+		ret = -ENOMEM;
+		goto dbbt_page_err;
+	}
+
+	dbbt = dbbt_page;
+	dbbt->checksum = 0;
+	dbbt->fingerprint = DBBT_FINGERPRINT2;
+	dbbt->version = DBBT_VERSION_1;
+	ret = dbbt_fill_data(mtd, dbbt_data_page, 0);
+	if (ret < 0)
+		goto dbbt_data_page_err;
+	else if (ret > 0)
+		dbbt->dbbtpages = 1;
+
+	/* write fcb and dbbt to nand */
+	ret = write_fcb_dbbt(mtd, fcb, dbbt, dbbt_data_page, 0);
 dbbt_data_page_err:
 	kfree(dbbt_data_page);
 dbbt_page_err:
 	kfree(dbbt_page);
 fcb_err:
 	kfree(fcb);
-fwbuf_err:
-	kfree(fwbuf);
-err:
-	return ret;
+
+	if (ret < 0) {
+		printf("failed to write FCB/DBBT\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
 }
 
 static int do_nandbcb_update(int argc, char * const argv[])
@@ -310,7 +529,7 @@ static int do_nandbcb_update(int argc, char * const argv[])
 
 	dev = nand_curr_device;
 	if (dev < 0) {
-		printf("failed to get nand_curr_device, run nand device");
+		printf("failed to get nand_curr_device, run nand device\n");
 		return CMD_RET_FAILURE;
 	}
 
@@ -352,6 +571,11 @@ static int do_nandbcb(cmd_tbl_t *cmdtp, int flag, int argc,
 		goto done;
 	}
 
+	if (strcmp(cmd, "bcbonly") == 0) {
+		ret = do_nandbcb_bcbonly(argc, argv);
+		goto done;
+	}
+
 done:
 	if (ret != -1)
 		return ret;
@@ -362,7 +586,10 @@ usage:
 #ifdef CONFIG_SYS_LONGHELP
 static char nandbcb_help_text[] =
 	"update addr off|partition len	- update 'len' bytes starting at\n"
-	"	'off|part' to memory address 'addr', skipping  bad blocks";
+	"       'off|part' to memory address 'addr', skipping  bad blocks\n"
+	"bcbonly fw-size fw1-off [fw2-off] - write only BCB (FCB and DBBT)\n"
+	"       where `fw-size` is fw sizes in bytes, `fw1-off` and\n"
+	"       and `fw2-off` - firmware offsets		";
 #endif
 
 U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb,
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index d17760e333..cdb78afacf 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -1,5 +1,10 @@
 if ARCH_IMX8
 
+config AHAB_BOOT
+	bool "Support i.MX8 AHAB features"
+	help
+	  This option enables the support for AHAB secure boot.
+
 config IMX8
 	bool
 
@@ -55,6 +60,12 @@ config TARGET_IMX8QM_MEK
 	select BOARD_LATE_INIT
 	select IMX8QM
 
+config TARGET_IMX8QM_ROM7720_A1
+	bool "Support i.MX8QM ROM-7720-A1"
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select IMX8QM
+
 config TARGET_IMX8QXP_MEK
 	bool "Support i.MX8QXP MEK board"
 	select BOARD_LATE_INIT
@@ -64,6 +75,7 @@ endchoice
 
 source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
 
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
new file mode 100644
index 0000000000..cf3c7d762a
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/image.h>
+#include <console.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SEC_SECURE_RAM_BASE             (0x31800000UL)
+#define SEC_SECURE_RAM_END_BASE         (SEC_SECURE_RAM_BASE + 0xFFFFUL)
+#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE  (0x60000000UL)
+
+#define SECO_PT                 2U
+
+static inline bool check_in_dram(ulong addr)
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		if (bd->bi_dram[i].size) {
+			if (addr >= bd->bi_dram[i].start &&
+			    addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+				return true;
+		}
+	}
+
+	return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+	struct container_hdr *phdr;
+	int i, ret = 0;
+	int err;
+	sc_rm_mr_t mr;
+	sc_faddr_t start, end;
+	u16 length;
+	struct boot_img_t *img;
+	unsigned long s, e;
+
+	if (addr % 4) {
+		puts("Error: Image's address is not 4 byte aligned\n");
+		return -EINVAL;
+	}
+
+	if (!check_in_dram(addr)) {
+		puts("Error: Image's address is invalid\n");
+		return -EINVAL;
+	}
+
+	phdr = (struct container_hdr *)addr;
+	if (phdr->tag != 0x87 && phdr->version != 0x0) {
+		printf("Error: Wrong container header\n");
+		return -EFAULT;
+	}
+
+	if (!phdr->num_images) {
+		printf("Error: Wrong container, no image found\n");
+		return -EFAULT;
+	}
+
+	length = phdr->length_lsb + (phdr->length_msb << 8);
+
+	debug("container length %u\n", length);
+	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
+	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+	err = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+	if (err) {
+		printf("Authenticate container hdr failed, return %d\n",
+		       err);
+		ret = -EIO;
+		goto exit;
+	}
+
+	/* Copy images to dest address */
+	for (i = 0; i < phdr->num_images; i++) {
+		img = (struct boot_img_t *)(addr +
+					    sizeof(struct container_hdr) +
+					    i * sizeof(struct boot_img_t));
+
+		debug("img %d, dst 0x%llx, src 0x%lx, size 0x%x\n",
+		      i, img->dst, img->offset + addr, img->size);
+
+		memcpy((void *)img->dst, (const void *)(img->offset + addr),
+		       img->size);
+
+		s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+		e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE);
+
+		flush_dcache_range(s, e);
+
+		/* Find the memreg and set permission for seco pt */
+		err = sc_rm_find_memreg(-1, &mr, s, e);
+		if (err) {
+			printf("Not found memreg for image: %d, error %d\n",
+			       i, err);
+			ret = -ENOMEM;
+			goto exit;
+		}
+
+		err = sc_rm_get_memreg_info(-1, mr, &start, &end);
+		if (!err)
+			debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+
+		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
+						   SC_RM_PERM_FULL);
+		if (err) {
+			printf("Set permission failed for img %d, error %d\n",
+			       i, err);
+			ret = -EPERM;
+			goto exit;
+		}
+
+		err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+					   (1 << i));
+		if (err) {
+			printf("Authenticate img %d failed, return %d\n",
+			       i, err);
+			ret = -EIO;
+		}
+
+		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
+						   SC_RM_PERM_NONE);
+		if (err) {
+			printf("Remove permission failed for img %d, err %d\n",
+			       i, err);
+			ret = -EPERM;
+		}
+
+		if (ret)
+			goto exit;
+	}
+
+exit:
+	if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE)
+		printf("Error: release container failed!\n");
+
+	return ret;
+}
+
+static int do_authenticate(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	ulong addr;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	printf("Authenticate OS container at 0x%lx\n", addr);
+
+	if (authenticate_os_container(addr))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static void display_life_cycle(u16 lc)
+{
+	printf("Lifecycle: 0x%04X, ", lc);
+	switch (lc) {
+	case 0x1:
+		printf("Pristine\n\n");
+		break;
+	case 0x2:
+		printf("Fab\n\n");
+		break;
+	case 0x8:
+		printf("Open\n\n");
+		break;
+	case 0x20:
+		printf("NXP closed\n\n");
+		break;
+	case 0x80:
+		printf("OEM closed\n\n");
+		break;
+	case 0x100:
+		printf("Partial field return\n\n");
+		break;
+	case 0x200:
+		printf("Full field return\n\n");
+		break;
+	case 0x400:
+		printf("No return\n\n");
+		break;
+	default:
+		printf("Unknown\n\n");
+		break;
+	}
+}
+
+#define AHAB_AUTH_CONTAINER_REQ 0x87
+#define AHAB_VERIFY_IMAGE_REQ 0x88
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_event(u32 event)
+{
+	u8 cmd = (event >> 16) & 0xff;
+	u8 resp_ind = (event >> 8) & 0xff;
+
+	switch (cmd) {
+	case AHAB_AUTH_CONTAINER_REQ:
+		printf("\tCMD = AHAB_AUTH_CONTAINER_REQ (0x%02X)\n", cmd);
+		printf("\tIND = ");
+		break;
+	case AHAB_VERIFY_IMAGE_REQ:
+		printf("\tCMD = AHAB_VERIFY_IMAGE_REQ (0x%02X)\n", cmd);
+		printf("\tIND = ");
+		break;
+	default:
+		return;
+	}
+
+	switch (resp_ind) {
+	case AHAB_NO_AUTHENTICATION_IND:
+		printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+		break;
+	case AHAB_BAD_KEY_HASH_IND:
+		printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+		break;
+	case AHAB_INVALID_KEY_IND:
+		printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+		break;
+	case AHAB_BAD_SIGNATURE_IND:
+		printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+		break;
+	case AHAB_BAD_HASH_IND:
+		printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+		break;
+	default:
+		printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+		break;
+	}
+}
+
+static int do_ahab_status(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	int err;
+	u8 idx = 0U;
+	u32 event;
+	u16 lc;
+
+	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
+	if (err != SC_ERR_NONE) {
+		printf("Error in get lifecycle\n");
+		return -EIO;
+	}
+
+	display_life_cycle(lc);
+
+	err = sc_seco_get_event(-1, idx, &event);
+	while (err == SC_ERR_NONE) {
+		printf("SECO Event[%u] = 0x%08X\n", idx, event);
+		display_ahab_auth_event(event);
+
+		idx++;
+		err = sc_seco_get_event(-1, idx, &event);
+	}
+
+	if (idx == 0)
+		printf("No SECO Events Found!\n\n");
+
+	return 0;
+}
+
+static int confirm_close(void)
+{
+	puts("Warning: Please ensure your sample is in NXP closed state, "
+	     "OEM SRK hash has been fused, \n"
+	     "         and you are able to boot a signed image successfully "
+	     "without any SECO events reported.\n"
+	     "         If not, your sample will be unrecoverable.\n"
+	     "\nReally perform this operation? <y/N>\n");
+
+	if (confirm_yesno())
+		return 1;
+
+	puts("Ahab close aborted\n");
+	return 0;
+}
+
+static int do_ahab_close(cmd_tbl_t *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	int err;
+	u16 lc;
+
+	if (!confirm_close())
+		return -EACCES;
+
+	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
+	if (err != SC_ERR_NONE) {
+		printf("Error in get lifecycle\n");
+		return -EIO;
+	}
+
+	if (lc != 0x20) {
+		puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n");
+		display_life_cycle(lc);
+		return -EPERM;
+	}
+
+	err = sc_seco_forward_lifecycle(-1, 16);
+	if (err != SC_ERR_NONE) {
+		printf("Error in forward lifecycle to OEM closed\n");
+		return -EIO;
+	}
+
+	printf("Change to OEM closed successfully\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
+	   "autenticate OS container via AHAB",
+	   "addr\n"
+	   "addr - OS container hex address\n"
+);
+
+U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
+	   "display AHAB lifecycle and events from seco",
+	   ""
+);
+
+U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
+	   "Change AHAB lifecycle to OEM closed",
+	   ""
+);
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
index fe73e29eee..00fe4670bb 100644
--- a/arch/arm/mach-imx/imx8/misc.c
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
 #include <asm/arch/sci/sci.h>
+#include <asm/mach-imx/sys_proto.h>
 
 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 {
@@ -25,9 +26,14 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 	return 0;
 }
 
+#define FSL_SIP_BUILDINFO			0xC2000003
+#define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
+
 void build_info(void)
 {
+	u32 seco_build = 0, seco_commit = 0;
 	u32 sc_build = 0, sc_commit = 0;
+	ulong atf_commit = 0;
 
 	/* Get SCFW build and commit id */
 	sc_misc_build_info(-1, &sc_build, &sc_commit);
@@ -35,5 +41,23 @@ void build_info(void)
 		printf("SCFW does not support build info\n");
 		sc_commit = 0; /* Display 0 if build info not supported */
 	}
-	printf("Build: SCFW %x\n", sc_commit);
+
+	/* Get SECO FW build and commit id */
+	sc_seco_build_info(-1, &seco_build, &seco_commit);
+	if (!seco_build) {
+		debug("SECO FW does not support build info\n");
+		/* Display 0 when the build info is not supported */
+		seco_commit = 0;
+	}
+
+	/* Get ARM Trusted Firmware commit id */
+	atf_commit = call_imx_sip(FSL_SIP_BUILDINFO,
+				  FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+	if (atf_commit == 0xffffffff) {
+		debug("ATF does not support build info\n");
+		atf_commit = 0x30; /* Display 0 */
+	}
+
+	printf("Build: SCFW %08x, SECO-FW %08x, ATF %s\n",
+	       sc_commit, seco_commit, (char *)&atf_commit);
 }
diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c
index 32f78bdddf..b57e68e412 100644
--- a/arch/arm/mach-imx/imx8/parse-container.c
+++ b/arch/arm/mach-imx/imx8/parse-container.c
@@ -7,6 +7,67 @@
 #include <errno.h>
 #include <spl.h>
 #include <asm/arch/image.h>
+#include <asm/arch/sci/sci.h>
+
+#define SEC_SECURE_RAM_BASE		0x31800000UL
+#define SEC_SECURE_RAM_END_BASE		(SEC_SECURE_RAM_BASE + 0xFFFFUL)
+#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE	0x60000000UL
+
+#define SECO_PT         2U
+
+#ifdef CONFIG_AHAB_BOOT
+static int authenticate_image(struct boot_img_t *img, int image_index)
+{
+	sc_faddr_t start, end;
+	sc_rm_mr_t mr;
+	int err;
+	int ret = 0;
+
+	debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
+	      image_index, img->dst, img->offset, img->size);
+
+	/* Find the memreg and set permission for seco pt */
+	err = sc_rm_find_memreg(-1, &mr,
+				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
+				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE));
+
+	if (err) {
+		printf("can't find memreg for image: %d, err %d\n",
+		       image_index, err);
+		return -ENOMEM;
+	}
+
+	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
+	if (!err)
+		debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_FULL);
+	if (err) {
+		printf("set permission failed for img %d, error %d\n",
+		       image_index, err);
+		return -EPERM;
+	}
+
+	err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+				   1 << image_index);
+	if (err) {
+		printf("authenticate img %d failed, return %d\n",
+		       image_index, err);
+		ret = -EIO;
+	}
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_NONE);
+	if (err) {
+		printf("remove permission failed for img %d, error %d\n",
+		       image_index, err);
+		ret = -EPERM;
+	}
+
+	return ret;
+}
+#endif
 
 static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
 					  struct spl_load_info *info,
@@ -45,6 +106,13 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
 		return NULL;
 	}
 
+#ifdef CONFIG_AHAB_BOOT
+	if (authenticate_image(&images[image_index], image_index)) {
+		printf("Failed to authenticate image %d\n", image_index);
+		return NULL;
+	}
+#endif
+
 	return &images[image_index];
 }
 
@@ -54,7 +122,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
 	struct container_hdr *container = NULL;
 	u16 length;
 	u32 sectors;
-	int i, size;
+	int i, size, ret = 0;
 
 	size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len);
 	sectors = size / info->bl_len;
@@ -96,13 +164,27 @@ static int read_auth_container(struct spl_image_info *spl_image,
 			return -EIO;
 	}
 
+#ifdef CONFIG_AHAB_BOOT
+	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
+	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+	ret = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+	if (ret) {
+		printf("authenticate container hdr failed, return %d\n", ret);
+		return ret;
+	}
+#endif
+
 	for (i = 0; i < container->num_images; i++) {
 		struct boot_img_t *image = read_auth_image(spl_image, info,
 							   container, i,
 							   sector);
 
-		if (!image)
-			return -EINVAL;
+		if (!image) {
+			ret = -EINVAL;
+			goto end_auth;
+		}
 
 		if (i == 0) {
 			spl_image->load_addr = image->dst;
@@ -110,7 +192,12 @@ static int read_auth_container(struct spl_image_info *spl_image,
 		}
 	}
 
-	return 0;
+end_auth:
+#ifdef CONFIG_AHAB_BOOT
+	if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0))
+		printf("Error: release container failed!\n");
+#endif
+	return ret;
 }
 
 int spl_load_imx_container(struct spl_image_info *spl_image,
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index feecdb50f6..2db5bde211 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -393,6 +393,15 @@ void init_usb_clk(void)
 	}
 }
 
+void init_nand_clk(void)
+{
+	clock_enable(CCGR_RAWNAND, 0);
+	clock_set_target_val(NAND_CLK_ROOT,
+			     CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
+			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
+	clock_enable(CCGR_RAWNAND, 1);
+}
+
 void init_uart_clk(u32 index)
 {
 	/* Set uart clock root 25M OSC */
@@ -804,6 +813,13 @@ int clock_init(void)
 
 	init_wdog_clk();
 	clock_enable(CCGR_TSENSOR, 1);
+	clock_enable(CCGR_OCOTP, 1);
+
+	/* config GIC ROOT to sys_pll2_200m */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT,
+			     CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+	clock_enable(CCGR_GIC, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index aeca82cdbf..a924af431c 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -202,14 +202,21 @@ u32 get_cpu_rev(void)
 	} else {
 		if (reg == CHIP_REV_1_0) {
 			/*
-			 * For B0 chip, the DIGPROG is not updated, still TO1.0.
-			 * we have to check ROM version further
+			 * For B0 chip, the DIGPROG is not updated,
+			 * it is still TO1.0. we have to check ROM
+			 * version or OCOTP_READ_FUSE_DATA.
+			 * 0xff0055aa is magic number for B1.
 			 */
-			rom_version = readl((void __iomem *)ROM_VERSION_A0);
-			if (rom_version != CHIP_REV_1_0) {
-				rom_version = readl((void __iomem *)ROM_VERSION_B0);
-				if (rom_version >= CHIP_REV_2_0)
-					reg = CHIP_REV_2_0;
+			if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
+				reg = CHIP_REV_2_1;
+			} else {
+				rom_version =
+					readl((void __iomem *)ROM_VERSION_A0);
+				if (rom_version != CHIP_REV_1_0) {
+					rom_version = readl((void __iomem *)ROM_VERSION_B0);
+					if (rom_version == CHIP_REV_2_0)
+						reg = CHIP_REV_2_0;
+				}
 			}
 		}
 	}
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 18d7e6819c..3d9422d5a2 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -26,7 +26,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 	/* Enable M4 */
 #ifdef CONFIG_IMX8M
-	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);
 #else
 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
 			SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@@ -38,7 +38,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 int arch_auxiliary_core_check_up(u32 core_id)
 {
 #ifdef CONFIG_IMX8M
-	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0);
 #else
 	unsigned int val;
 
diff --git a/arch/arm/mach-imx/init.c b/arch/arm/mach-imx/init.c
index b8d8d12372..693b724429 100644
--- a/arch/arm/mach-imx/init.c
+++ b/arch/arm/mach-imx/init.c
@@ -108,9 +108,9 @@ void boot_mode_apply(unsigned cfg_val)
 	writel(cfg_val, &psrc->gpr9);
 	reg = readl(&psrc->gpr10);
 	if (cfg_val)
-		reg |= 1 << 28;
+		reg |= IMX6_SRC_GPR10_BMODE;
 	else
-		reg &= ~(1 << 28);
+		reg &= ~IMX6_SRC_GPR10_BMODE;
 	writel(reg, &psrc->gpr10);
 }
 #endif
@@ -118,7 +118,7 @@ void boot_mode_apply(unsigned cfg_val)
 #if defined(CONFIG_MX6)
 u32 imx6_src_get_boot_mode(void)
 {
-	if (imx6_is_bmode_from_gpr9())
+	if (readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE)
 		return readl(&src_base->gpr9);
 	else
 		return readl(&src_base->sbmr1);
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 00e3c486bc..607210520f 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -232,6 +232,13 @@ config TARGET_MCCMON6
 	bool "mccmon6"
 	select MX6QDL
 	select SUPPORT_SPL
+	select DM
+	select DM_GPIO
+	select DM_ETH
+	select DM_SERIAL
+	select DM_I2C
+	select DM_SPI
+	imply CMD_DM
 
 config TARGET_MX6CUBOXI
 	bool "Solid-run mx6 boards"
@@ -589,6 +596,24 @@ config TARGET_ZC5601
 	select SUPPORT_SPL
 	imply CMD_DM
 
+config TARGET_BRPPT2
+	bool "brppt2"
+	select BOARD_LATE_INIT
+	select MX6QDL
+	select OF_CONTROL
+	select SPL_OF_LIBFDT
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select SUPPORT_SPL
+	select SPL_DM if SPL
+	select SPL_OF_CONTROL if SPL
+        help
+          Support
+          B&R BRPPT2 platform
+          based on Freescale's iMX6 SoC
 endchoice
 
 config SYS_SOC
@@ -646,5 +671,6 @@ source "board/udoo/Kconfig"
 source "board/udoo/neo/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
+source "board/BuR/brppt2/Kconfig"
 
 endif
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 7763c79e1c..6a9e673ca2 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -1279,16 +1279,26 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 void enable_ipu_clock(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-	reg = readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
-	writel(reg, &mxc_ccm->CCGR3);
+
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
 
 	if (is_mx6dqp()) {
 		setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
 		setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
 	}
 }
+
+void disable_ipu_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
+
+	if (is_mx6dqp()) {
+		clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+		clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+	}
+}
 #endif
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index 3ab9a3f022..0c640e2e33 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -6,11 +6,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
 #include <common.h>
 #include <env.h>
@@ -20,43 +16,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_FEC_MXC
 #include <miiphy.h>
 
-#define MDIO_PAD_CTRL ( \
-	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_PAD_CTRL_PU ( \
-	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_PAD_CTRL_PD ( \
-	PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_CLK_PAD_CTRL ( \
-	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
-	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
-)
-
-static iomux_v3_cfg_t const fec1_pads[] = {
-	MX6_PAD_GPIO1_IO06__ENET1_MDIO        | MUX_PAD_CTRL(MDIO_PAD_CTRL),
-	MX6_PAD_GPIO1_IO07__ENET1_MDC         | MUX_PAD_CTRL(MDIO_PAD_CTRL),
-	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER      | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
-	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN      | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
-	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
-	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
-	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
-	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
-	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN      | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
-	/* PHY Int */
-	MX6_PAD_NAND_DQS__GPIO4_IO16          | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
-	/* PHY Reset */
-	MX6_PAD_NAND_DATA00__GPIO4_IO02       | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
-	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-};
-
 int board_phy_config(struct phy_device *phydev)
 {
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
@@ -67,43 +26,16 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
+static int setup_fec(void)
 {
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct gpio_desc rst;
-	int ret;
 
 	/* Use 50M anatop loopback REF_CLK1 for ENET1,
 	 * clear gpr1[13], set gpr1[17] */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 
-	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
-	if (ret)
-		return ret;
-
-	enable_enet_clk(1);
-
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
-	ret = dm_gpio_lookup_name("GPIO4_2", &rst);
-	if (ret) {
-		printf("Cannot get GPIO4_2\n");
-		return ret;
-	}
-
-	ret = dm_gpio_request(&rst, "phy-rst");
-	if (ret) {
-		printf("Cannot request GPIO4_2\n");
-		return ret;
-	}
-
-	dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
-	dm_gpio_set_value(&rst, 0);
-	udelay(1000);
-	dm_gpio_set_value(&rst, 1);
-
-	return fecmxc_initialize(bis);
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 #endif /* CONFIG_FEC_MXC */
 
@@ -112,6 +44,10 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
index 968e7cf309..fca520c671 100644
--- a/arch/arm/mach-imx/sip.c
+++ b/arch/arm/mach-imx/sip.c
@@ -7,7 +7,8 @@
 #include <asm/arch/sys_proto.h>
 
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
-			   unsigned long reg1, unsigned long reg2)
+			   unsigned long reg1, unsigned long reg2,
+			   unsigned long reg3)
 {
 	struct pt_regs regs;
 
@@ -15,6 +16,7 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 	regs.regs[1] = reg0;
 	regs.regs[2] = reg1;
 	regs.regs[3] = reg2;
+	regs.regs[4] = reg3;
 
 	smc_call(&regs);
 
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index f025c4b301..5cc74b6f9b 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -189,6 +189,34 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
 u32 spl_boot_mode(const u32 boot_device)
 {
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
+	switch (get_boot_device()) {
+	/* for MMC return either RAW or FAT mode */
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+#if defined(CONFIG_SPL_FAT_SUPPORT)
+		return MMCSD_MODE_FS;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+#if defined(CONFIG_SPL_FAT_SUPPORT)
+		return MMCSD_MODE_FS;
+#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
+		return MMCSD_MODE_EMMCBOOT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	default:
+		puts("spl: ERROR:  unsupported device\n");
+		hang();
+	}
+#else
 /*
  * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used
  * unconditionally to decide about device to use for booting.
@@ -217,6 +245,7 @@ u32 spl_boot_mode(const u32 boot_device)
 		puts("spl: ERROR:  unsupported device\n");
 		hang();
 	}
+#endif
 }
 #endif
 
diff --git a/board/BuR/brppt2/Kconfig b/board/BuR/brppt2/Kconfig
new file mode 100644
index 0000000000..aa39d66fb7
--- /dev/null
+++ b/board/BuR/brppt2/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_BRPPT2
+
+config SYS_BOARD
+	default "brppt2"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "brppt2"
+
+config SPL_DM_SPI
+	def_bool y
+
+endif
diff --git a/board/BuR/brppt2/MAINTAINERS b/board/BuR/brppt2/MAINTAINERS
new file mode 100644
index 0000000000..a1b5bd49bf
--- /dev/null
+++ b/board/BuR/brppt2/MAINTAINERS
@@ -0,0 +1,6 @@
+BUR_PPT2 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt2/
+F:	include/configs/brppt2.h
+F:	configs/brppt2_defconfig
diff --git a/board/BuR/brppt2/Makefile b/board/BuR/brppt2/Makefile
new file mode 100644
index 0000000000..7f3c7cd953
--- /dev/null
+++ b/board/BuR/brppt2/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+# Copyright (C) 2019
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+obj-y := ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c
new file mode 100644
index 0000000000..3284ff0936
--- /dev/null
+++ b/board/BuR/brppt2/board.c
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for BuR BRPPT2 board
+ *
+ * Copyright (C) 2019
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ *
+ */
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#ifdef CONFIG_SPL_BUILD
+# include <asm/arch/mx6-ddr.h>
+#endif
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define USBHUB_RSTN	IMX_GPIO_NR(1, 16)
+#define BKLT_EN		IMX_GPIO_NR(1, 15)
+#define CAPT_INT	IMX_GPIO_NR(4, 9)
+#define CAPT_RESETN	IMX_GPIO_NR(4, 11)
+#define SW_INTN		IMX_GPIO_NR(3, 26)
+#define VCCDISP_EN	IMX_GPIO_NR(5, 18)
+#define EMMC_RSTN	IMX_GPIO_NR(6, 8)
+#define PMIC_IRQN	IMX_GPIO_NR(5, 22)
+#define TASTER		IMX_GPIO_NR(5, 23)
+
+#define ETH0_LINK	IMX_GPIO_NR(1, 27)
+#define ETH1_LINK	IMX_GPIO_NR(1, 28)
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ECSPI_PAD_CTRL		(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL1		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK	((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) |	\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL_PD	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define LCDCMOS_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define MUXDESC(pad, ctrl)	IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
+
+#if !defined(CONFIG_SPL_BUILD)
+static iomux_v3_cfg_t const eth_pads[] = {
+	/*
+	 * Gigabit Ethernet
+	 */
+	/* CLKs */
+	MUXDESC(PAD_GPIO_16__ENET_REF_CLK,	ENET_PAD_CTRL_CLK),
+	MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK,	ENET_PAD_CTRL_CLK),
+	/* MDIO */
+	MUXDESC(PAD_ENET_MDIO__ENET_MDIO,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_ENET_MDC__ENET_MDC,		ENET_PAD_CTRL_PU),
+	/* RGMII */
+	MUXDESC(PAD_RGMII_TXC__RGMII_TXC,	ENET_PAD_CTRL1),
+	MUXDESC(PAD_RGMII_TD0__RGMII_TD0,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD1__RGMII_TD1,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD2__RGMII_TD2,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD3__RGMII_TD3,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_RXC__RGMII_RXC,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD0__RGMII_RD0,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD1__RGMII_RD1,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD2__RGMII_RD2,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD3__RGMII_RD3,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL,	ENET_PAD_CTRL_PU),
+	/* ETH0_LINK */
+	MUXDESC(PAD_ENET_RXD0__GPIO1_IO27,	GPIO_PAD_CTRL_PD),
+	/* ETH1_LINK */
+	MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28,	GPIO_PAD_CTRL_PD),
+};
+
+static iomux_v3_cfg_t const board_pads[] = {
+	/*
+	 * I2C #3, #4
+	 */
+	MUXDESC(PAD_GPIO_3__I2C3_SCL,		I2C_PAD_CTRL),
+	MUXDESC(PAD_GPIO_6__I2C3_SDA,		I2C_PAD_CTRL),
+
+	/*
+	 * UART#4 PADS
+	 * UART_Tasten
+	 */
+	MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B,	UART_PAD_CTRL),
+	/*
+	 * ESCPI#1
+	 * M25P32 NOR-Flash
+	 */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/*
+	 * ESCPI#2
+	 * resTouch SPI ADC
+	 */
+	MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_OE__ECSPI2_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D24__GPIO3_IO24,	ECSPI_PAD_CTRL),
+	/*
+	 * USDHC#4
+	 */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/*
+	 * USB OTG power & ID
+	 */
+	/* USB_OTG_5V_EN */
+	MUXDESC(PAD_EIM_D22__GPIO3_IO22,	GPIO_PAD_CTRL_PD),
+	MUXDESC(PAD_EIM_D31__GPIO3_IO31,	GPIO_PAD_CTRL_PD),
+	/* USB_OTG_JUMPER */
+	MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID,	GPIO_PAD_CTRL_PD),
+	/*
+	 * PWM-Pins
+	 */
+	/* BKLT_CTL */
+	MUXDESC(PAD_SD1_CMD__PWM4_OUT,		GPIO_PAD_CTRL_PD),
+	/* SPEAKER */
+	MUXDESC(PAD_SD1_DAT1__PWM3_OUT,		GPIO_PAD_CTRL_PD),
+	/*
+	 * GPIOs
+	 */
+	/* USB_HUB_nRESET */
+	MUXDESC(PAD_SD1_DAT0__GPIO1_IO16,	GPIO_PAD_CTRL_PD),
+	/* BKLT_EN */
+	MUXDESC(PAD_SD2_DAT0__GPIO1_IO15,	GPIO_PAD_CTRL_PD),
+	/* capTouch_INT */
+	MUXDESC(PAD_KEY_ROW1__GPIO4_IO09,	GPIO_PAD_CTRL_PD),
+	/* capTouch_nRESET */
+	MUXDESC(PAD_KEY_ROW2__GPIO4_IO11,	GPIO_PAD_CTRL_PD),
+	/* SW_nINT */
+	MUXDESC(PAD_EIM_D26__GPIO3_IO26,	GPIO_PAD_CTRL_PU),
+	/* VCC_DISP_EN */
+	MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18,	GPIO_PAD_CTRL_PD),
+	/* eMMC_nRESET */
+	MUXDESC(PAD_NANDF_ALE__GPIO6_IO08,	GPIO_PAD_CTRL_PD),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+	/* PMIC_nIRQ */
+	MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22,	GPIO_PAD_CTRL_PU),
+	/* nTASTER */
+	MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23,	GPIO_PAD_CTRL_PU),
+	/* RGB LCD Display */
+	MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23,	LCDCMOS_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	gpio_direction_output(USBHUB_RSTN, 1);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	ulong b_mode = 4;
+
+	if (gpio_get_value(TASTER) == 0)
+		b_mode = 12;
+
+	env_set_ulong("b_mode", b_mode);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	if (gpio_request(BKLT_EN, "BKLT_EN"))
+		printf("Warning: BKLT_EN setup failed\n");
+	gpio_direction_output(BKLT_EN, 0);
+
+	if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
+		printf("Warning: USBHUB_nRST setup failed\n");
+	gpio_direction_output(USBHUB_RSTN, 0);
+
+	if (gpio_request(TASTER, "TASTER"))
+		printf("Warning: TASTER setup failed\n");
+	gpio_direction_input(TASTER);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	SETUP_IOMUX_PADS(board_pads);
+	SETUP_IOMUX_PADS(eth_pads);
+
+	/* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
+	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+	enable_fec_anatop_clock(0, ENET_25MHZ);
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+#else
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020030,
+	.dram_sdclk_1		= 0x00020030,
+	.dram_cas		= 0x00020030,
+	.dram_ras		= 0x00020030,
+	.dram_reset		= 0x00020030,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00003030,
+	.dram_sdodt1		= 0x00003030,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000030,
+	.dram_sdqs1		= 0x00000030,
+	.dram_sdqs2		= 0x00000030,
+	.dram_sdqs3		= 0x00000030,
+	.dram_sdqs4		= 0x00000030,
+	.dram_sdqs5		= 0x00000030,
+	.dram_sdqs6		= 0x00000030,
+	.dram_sdqs7		= 0x00000030,
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00020030,
+	.dram_dqm1		= 0x00020030,
+	.dram_dqm2		= 0x00020030,
+	.dram_dqm3		= 0x00020030,
+	.dram_dqm4		= 0x00020030,
+	.dram_dqm5		= 0x00020030,
+	.dram_dqm6		= 0x00020030,
+	.dram_dqm7		= 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000030,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000030,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000030,
+	.grp_b1ds		= 0x00000030,
+	.grp_b2ds		= 0x00000030,
+	.grp_b3ds		= 0x00000030,
+	.grp_b4ds		= 0x00000030,
+	.grp_b5ds		= 0x00000030,
+	.grp_b6ds		= 0x00000030,
+	.grp_b7ds		= 0x00000030,
+};
+
+/*
+ * DDR3 desriptions - these are the memory chips we support
+ */
+
+/* NT5CC128M16FP-DII */
+static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
+	.mem_speed      = 1600,
+	.density        = 2,
+	.width          = 16,
+	.banks          = 8,
+	.rowaddr        = 14,
+	.coladdr        = 10,
+	.pagesz         = 2,
+	.trcd           = 1375,
+	.trcmin         = 4875,
+	.trasmin        = 3500,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x003F003E,
+	.p0_mpwldectrl1 = 0x003A003A,
+	.p1_mpwldectrl0 = 0x001B001C,
+	.p1_mpwldectrl1 = 0x00190031,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x02640264,
+	.p0_mpdgctrl1   = 0x02440250,
+	.p1_mpdgctrl0   = 0x02400250,
+	.p1_mpdgctrl1   = 0x0238023C,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x40464644,
+	.p1_mprddlctl   = 0x464A4842,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x38343034,
+	.p1_mpwrdlctl   = 0x36323830,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x00410043,
+	.p0_mpwldectrl1 = 0x003A003C,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x023C0244,
+	.p0_mpdgctrl1   = 0x02240230,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x484C4A48,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3C363434,
+};
+
+static void spl_dram_init(void)
+{
+	struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
+	u32 val, dram_strap = 0;
+	struct mx6_ddr3_cfg *mem = NULL;
+	struct mx6_mmdc_calibration *calib = NULL;
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize		= -1,	/* CPU type specific (overwritten) */
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density	= 32,	/* 32Gb per CS */
+		.ncs		= 1,	/* single chip select */
+		.cs1_mirror	= 0,
+		.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+		.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+		.walat		= 1,	/* Write additional latency */
+		.ralat		= 5,	/* Read additional latency */
+		.mif3_mode	= 3,	/* Command prediction working mode */
+		.bi_on		= 1,	/* Bank interleaving enabled */
+		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type	= 0,	/* DDR3 */
+	};
+
+	/*
+	 * MMDC Calibration requires the following data:
+	 *  mx6_mmdc_calibration - board-specific calibration (routing delays)
+	 *     these calibration values depend on board routing, SoC, and DDR
+	 *  mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+	 *  mx6_ddr_cfg - chip specific timing/layout details
+	 */
+
+	/* setup HWID3-2 to input */
+	val = readl(&gpio->gpio_dir);
+	val &= ~(0x1 << 0 | 0x1 << 1);
+	writel(val, &gpio->gpio_dir);
+
+	/* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
+	dram_strap = readl(&gpio->gpio_psr) & 0x3;
+
+	switch (dram_strap) {
+	/* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
+	case 0:
+		puts("DRAM strap 00\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 2;
+		calib = &cal_nt5cc128m16fp_dii_128x64_s;
+		break;
+	/* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
+	case 1:
+		puts("DRAM strap 01\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 1;
+		calib = &cal_nt5cc128m16fp_dii_128x32_s;
+		break;
+	default:
+		printf("DRAM strap 0x%x (invalid)\n", dram_strap);
+		break;
+	}
+
+	if (!mem) {
+		puts("Error: Invalid Memory Configuration\n");
+		hang();
+	}
+	if (!calib) {
+		puts("Error: Invalid Board Calibration Configuration\n");
+		hang();
+	}
+
+	mx6sdl_dram_iocfg(16 << sysinfo.dsize,
+			  &ddr_iomux_s,
+			  &grp_iomux_s);
+
+	mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+static iomux_v3_cfg_t const board_pads_spl[] = {
+	/* UART#1 PADS */
+	MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA,	UART_PAD_CTRL),
+	/* ESCPI#1 PADS */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/* USDHC#4 PADS */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+};
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	 */
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x00F0FC03, &ccm->CCGR1);
+	writel(0x0FFFF000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0030C3, &ccm->CCGR5);
+	writel(0x000003F0, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	timer_init();
+	gpr_init();
+
+	SETUP_IOMUX_PADS(board_pads_spl);
+	spl_dram_init();
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/BuR/brppt2/config.mk b/board/BuR/brppt2/config.mk
new file mode 100644
index 0000000000..fa973db762
--- /dev/null
+++ b/board/BuR/brppt2/config.mk
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp SPL misc/ &&				\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ifeq ($(hw-platform-y),brppt2)
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += $(hw-platform-y)_prog.bin
+ALL-y += $(hw-platform-y)_prod.zip
+endif
+endif
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig
new file mode 100644
index 0000000000..cf3869ed92
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QM_ROM7720_A1
+
+config SYS_BOARD
+	default "imx8qm_rom7720_a1"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_rom7720"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
new file mode 100644
index 0000000000..b142ee02e6
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QM ROM 7720 a1 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/advantech/imx8qm_rom7720_a1/
+F:	include/configs/imx8qm_rom7720.h
+F:	configs/imx8qm_rom7720_a1_4G_defconfig
diff --git a/board/advantech/imx8qm_rom7720_a1/Makefile b/board/advantech/imx8qm_rom7720_a1/Makefile
new file mode 100644
index 0000000000..51c5de251c
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_rom7720_a1.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README
new file mode 100644
index 0000000000..bff5712589
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/README
@@ -0,0 +1,50 @@
+U-Boot for the NXP i.MX8QM ROM 7720a1 board
+
+Quick Start
+===========
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Build imx-mkimage
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+$ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+==============================
+
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+$ chmod +x imx-sc-firmware-1.1.bin
+$ ./imx-sc-firmware-1.1.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+$ chmod +x firmware-imx-8.0.bin
+$ ./firmware-imx-8.0.bin
+
+Build U-Boot
+============
+
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
+$ make imx8qm_rom7720_a1_4G_defconfig
+$ make u-boot.bin
+$ make flash.bin
+
+Flash the binary into the SD card
+=================================
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+====
+Set Boot switch SW2: 1100.
diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
new file mode 100644
index 0000000000..2f97d5ce96
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	/* This is needed to because Kernel do not Power Up DC_0 */
+	sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifdef CONFIG_FEC_ENABLE_MAX7322
+	u8 value;
+
+	/* This is needed to drive the pads to 1.8V instead of 1.5V */
+	i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
+
+	if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
+		/* Write 0x1 to enable O0 output, this device has no addr */
+		/* hence addr length is 0 */
+		value = 0x1;
+		if (dm_i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
+			printf("MAX7322 write failed\n");
+	} else {
+		printf("MAX7322 Not found\n");
+	}
+	mdelay(1);
+#endif
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: ROM-7720-A1 4GB\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power up base board */
+	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "ROM-7720-A1");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	return 0;
+}
diff --git a/board/advantech/imx8qm_rom7720_a1/imximage.cfg b/board/advantech/imx8qm_rom7720_a1/imximage.cfg
new file mode 100644
index 0000000000..e324c7ca37
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/imximage.cfg
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier:	GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
new file mode 100644
index 0000000000..3f31a8f9c3
--- /dev/null
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
+			puts("Warning: failed to initialize FSPI0\n");
+		}
+	}
+#endif
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
+			puts("Warning: failed to turn off FSPI0\n");
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c
index cbf40d5c4a..ade155c5ad 100644
--- a/board/armadeus/opos6uldev/board.c
+++ b/board/armadeus/opos6uldev/board.c
@@ -3,53 +3,17 @@
  * Copyright (C) 2018 Armadeus Systems
  */
 
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
 #include <common.h>
 
 #ifdef CONFIG_VIDEO_MXS
-#define LCD_PAD_CTRL ( \
-	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
-	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \
-)
-
-static iomux_v3_cfg_t const lcd_pads[] = {
-	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-
-	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
 int setup_lcd(void)
 {
 	struct gpio_desc backlight;
 	int ret;
 
-	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-
 	/* Set Brightness to high */
 	ret = dm_gpio_lookup_name("GPIO4_10", &backlight);
 	if (ret) {
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index 2d0f78da11..8dc4b80872 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -197,7 +197,7 @@ static const struct boot_mode board_boot_modes[] = {
 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 	/* 8 bit bus width */
-	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 	{NULL,	 0},
 };
 #endif
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 1b7acc8df7..f2c3ac3e28 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -476,6 +476,32 @@ static void setup_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart1_pads);
 }
 
+#ifdef CONFIG_FSL_USDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* eMMC/uSDHC4 is always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+	usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	usdhc_cfg[0].max_bus_width = 8;
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
 /* USB */
 static iomux_v3_cfg_t const usb_pads[] = {
 	IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID	| MUX_PAD_CTRL(NO_PAD_CTRL)),
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 043b5f4342..2d08f9a563 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -18,6 +18,9 @@
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
@@ -41,16 +44,7 @@ void spl_dram_init(void)
 
 void spl_board_init(void)
 {
-	struct udevice *dev;
-	int ret;
-
 	puts("Normal Boot\n");
-
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@30380000",
-					&dev);
-	if (ret < 0)
-		printf("Failed to find clock node. Check device tree\n");
 }
 
 #ifdef CONFIG_SPL_LOAD_FIT
@@ -88,8 +82,45 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+#ifndef CONFIG_IMX8M_LPDDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#endif
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+
 void board_init_f(ulong dummy)
 {
+	struct udevice *dev;
 	int ret;
 
 	arch_cpu_init();
@@ -105,14 +136,24 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	ret = spl_init();
+	ret = spl_early_init();
 	if (ret) {
-		debug("spl_init() failed: %d\n", ret);
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
 		hang();
 	}
 
 	enable_tzc380();
 
+	power_init_board();
+
 	/* DDR initialization */
 	spl_dram_init();
 
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
index ead6750ebf..3c9786c6b7 100644
--- a/board/liebherr/mccmon6/Makefile
+++ b/board/liebherr/mccmon6/Makefile
@@ -2,5 +2,8 @@
 #
 # (C) Copyright 2016-2017
 # Lukasz Majewski, DENX Software Engineering, lukma@denx.de
-
-obj-y  := mccmon6.o spl.o
+ifdef CONFIG_SPL_BUILD
+obj-y  := spl.o
+else
+obj-y  := mccmon6.o
+endif
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
index 7d2751ab03..6a5fbbb8e6 100644
--- a/board/liebherr/mccmon6/mccmon6.c
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -9,54 +9,11 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/io.h>
-#include <fsl_esdhc_imx.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <micrel.h>
-#include <phy.h>
-#include <input.h>
-#include <i2c.h>
-#include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
-
-#define USDHC2_CD_GPIO		IMX_GPIO_NR(1, 4)
-#define ETH_PHY_RESET		IMX_GPIO_NR(1, 27)
-#define ECSPI3_CS0		IMX_GPIO_NR(4, 24)
-#define ECSPI3_FLWP		IMX_GPIO_NR(4, 27)
-#define NOR_WP			IMX_GPIO_NR(1, 1)
-#define DISPLAY_EN		IMX_GPIO_NR(1, 2)
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -64,304 +21,11 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const uart1_pads[] = {
-	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* Carrier MicroSD Card Detect */
-	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
-		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
-		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
-		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* KSZ9031 PHY Reset */
-	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
-	SETUP_IOMUX_PADS(uart1_pads);
-}
-
-static void setup_iomux_enet(void)
-{
-	SETUP_IOMUX_PADS(enet_pads);
-
-	/* Reset KSZ9031 PHY */
-	gpio_direction_output(ETH_PHY_RESET, 0);
-	mdelay(10);
-	gpio_set_value(ETH_PHY_RESET, 1);
-	udelay(100);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		/*
-		 * eMMC don't have card detect pin - since it is soldered to the
-		 * PCB board
-		 */
-		ret = 1;
-		break;
-	}
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	u32 index = 0;
-
-	/*
-	 * MMC MAP
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    Soldered on board eMMC device
-	 * mmc1                    MicroSD card
-	 */
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			SETUP_IOMUX_PADS(usdhc3_pads);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			usdhc_cfg[0].max_bus_width = 8;
-			break;
-		case 1:
-			SETUP_IOMUX_PADS(usdhc2_pads);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			usdhc_cfg[1].max_bus_width = 4;
-			gpio_direction_input(USDHC2_CD_GPIO);
-			break;
-		default:
-			printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
-	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eimnor_cs_setup(void)
-{
-	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
-
-	/* NOR configuration */
-	writel(0x00620181, &weim_regs->cs0gcr1);
-	writel(0x00000001, &weim_regs->cs0gcr2);
-	writel(0x0b020000, &weim_regs->cs0rcr1);
-	writel(0x0000b000, &weim_regs->cs0rcr2);
-	writel(0x0804a240, &weim_regs->cs0wcr1);
-	writel(0x00000000, &weim_regs->cs0wcr2);
-
-	writel(0x00000120, &weim_regs->wcr);
-	writel(0x00000010, &weim_regs->wiar);
-	writel(0x00000000, &weim_regs->ear);
-
-	set_chipselect_size(CS0_128);
-}
-
-static void setup_eimnor(void)
-{
-	SETUP_IOMUX_PADS(eimnor_pads);
-	gpio_direction_output(NOR_WP, 1);
-
-	enable_eim_clk(1);
-	eimnor_cs_setup();
-}
-
-/* mccmon6 board has SPI Flash is connected to SPI3 */
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
-}
-
-static iomux_v3_cfg_t const ecspi3_pads[] = {
-	/* SPI3 */
-	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-	IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-	IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-};
-
-void setup_spi(void)
-{
-	SETUP_IOMUX_PADS(ecspi3_pads);
-
-	enable_spi_clk(true, 2);
-
-	/* set cs0 to high */
-	gpio_direction_output(ECSPI3_CS0, 1);
-
-	/* set flwp to high */
-	gpio_direction_output(ECSPI3_FLWP, 1);
-}
-
-struct i2c_pads_info mx6q_i2c1_pad_info = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-struct i2c_pads_info mx6q_i2c2_pad_info = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
-			| MUX_PAD_CTRL(I2C_PAD_CTRL),
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-int board_eth_init(bd_t *bis)
-{
-	setup_iomux_enet();
-
-	return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
-
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	gpio_direction_output(DISPLAY_EN, 1);
-
-	setup_eimnor();
-	setup_spi();
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
-
 	return 0;
 }
 
@@ -378,113 +42,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/*
-	 * Default setting for GMII Clock Pad Skew Register 0x1EF:
-	 * MMD Address 0x2h, Register 0x8h
-	 *
-	 * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
-	 * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
-	 *
-	 * Adjustment -> write 0x3FF:
-	 * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
-	 * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
-	 *
-	 */
-	ksz9031_phy_extended_write(phydev, 0x2,
-				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
-
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
-
-	ksz9031_phy_extended_write(phydev, 0x2,
-				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-				   0x3333);
-
-	ksz9031_phy_extended_write(phydev, 0x2,
-				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-				   0x2052);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void)
-{
-	setup_eimnor();
-
-	gpio_direction_output(DISPLAY_EN, 1);
-}
-#endif /* CONFIG_SPL_BOARD_INIT */
-
-#ifdef CONFIG_SPL_BUILD
-void board_boot_order(u32 *spl_boot_list)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC2:
-	case BOOT_DEVICE_MMC1:
-		spl_boot_list[0] = BOOT_DEVICE_MMC2;
-		spl_boot_list[1] = BOOT_DEVICE_MMC1;
-		break;
-
-	case BOOT_DEVICE_NOR:
-		spl_boot_list[0] = BOOT_DEVICE_NOR;
-		break;
-	}
-}
-#endif /* CONFIG_SPL_BUILD */
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	char s[16];
-	int ret;
-	/*
-	 * We use BOOT_DEVICE_MMC1, but SD card is connected
-	 * to MMC2
-	 *
-	 * Correct "mapping" is delivered in board defined
-	 * board_boot_order() function.
-	 *
-	 * SD card boot is regarded as a "development" one,
-	 * hence we _always_ go through the u-boot.
-	 *
-	 */
-	if (spl_boot_device() == BOOT_DEVICE_MMC1)
-		return 1;
-
-	/* break into full u-boot on 'c' */
-	if (serial_tstc() && serial_getc() == 'c')
-		return 1;
-
-	env_init();
-	ret = env_get_f("boot_os", s, sizeof(s));
-	if ((ret != -1) && (strcmp(s, "no") == 0))
-		return 1;
-
-	/*
-	 * Check if SWUpdate recovery needs to be started
-	 *
-	 * recovery_status = NULL (not set - ret == -1) -> normal operation
-	 *
-	 * recovery_status = progress or
-	 * recovery_status = failed   or
-	 * recovery_status = <any value> -> start SWUpdate
-	 *
-	 */
-	ret = env_get_f("recovery_status", s, sizeof(s));
-	if (ret != -1)
-		return 1;
-
-	return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index f0ed78c847..fc5f5e948c 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -20,7 +20,6 @@
 #include <asm/arch/sys_proto.h>
 #include <spl.h>
 
-#if defined(CONFIG_SPL_BUILD)
 #include <asm/arch/mx6-ddr.h>
 /*
  * Driving strength:
@@ -274,6 +273,25 @@ static void spl_dram_init(void)
 	udelay(100);
 }
 
+static void setup_spi(void)
+{
+	enable_spi_clk(true, 2);
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
 void board_init_f(ulong dummy)
 {
 	ccgr_init();
@@ -284,7 +302,7 @@ void board_init_f(ulong dummy)
 	gpr_init();
 
 	/* iomux */
-	board_early_init_f();
+	setup_iomux_uart();
 
 	/* setup GP timer */
 	timer_init();
@@ -292,7 +310,264 @@ void board_init_f(ulong dummy)
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 
+	/* enable ECSPI clocks */
+	setup_spi();
+
 	/* DDR initialization */
 	spl_dram_init();
 }
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+
+	case BOOT_DEVICE_NOR:
+		spl_boot_list[0] = BOOT_DEVICE_NOR;
+		break;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
 #endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	char s[16];
+	int ret;
+	/*
+	 * We use BOOT_DEVICE_MMC1, but SD card is connected
+	 * to MMC2
+	 *
+	 * Correct "mapping" is delivered in board defined
+	 * board_boot_order() function.
+	 *
+	 * SD card boot is regarded as a "development" one,
+	 * hence we _always_ go through the u-boot.
+	 *
+	 */
+	if (spl_boot_device() == BOOT_DEVICE_MMC1)
+		return 1;
+
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	env_init();
+	ret = env_get_f("boot_os", s, sizeof(s));
+	if ((ret != -1) && (strcmp(s, "no") == 0))
+		return 1;
+
+	/*
+	 * Check if SWUpdate recovery needs to be started
+	 *
+	 * recovery_status = NULL (not set - ret == -1) -> normal operation
+	 *
+	 * recovery_status = progress or
+	 * recovery_status = failed   or
+	 * recovery_status = <any value> -> start SWUpdate
+	 *
+	 */
+	ret = env_get_f("recovery_status", s, sizeof(s));
+	if (ret != -1)
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define NOR_WP			IMX_GPIO_NR(1, 1)
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	/* NOR configuration */
+	writel(0x00620181, &weim_regs->cs0gcr1);
+	writel(0x00000001, &weim_regs->cs0gcr2);
+	writel(0x0b020000, &weim_regs->cs0rcr1);
+	writel(0x0000b000, &weim_regs->cs0rcr2);
+	writel(0x0804a240, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+
+	writel(0x00000120, &weim_regs->wcr);
+	writel(0x00000010, &weim_regs->wiar);
+	writel(0x00000000, &weim_regs->ear);
+
+	set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+	gpio_direction_output(NOR_WP, 1);
+
+	enable_eim_clk(1);
+	eimnor_cs_setup();
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC2_CD_GPIO		IMX_GPIO_NR(1, 4)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		/*
+		 * eMMC don't have card detect pin - since it is soldered to the
+		 * PCB board
+		 */
+		ret = 1;
+		break;
+	}
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * MMC MAP
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    Soldered on board eMMC device
+	 * mmc1                    MicroSD card
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 8;
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+#define DISPLAY_EN		IMX_GPIO_NR(1, 2)
+void spl_board_init(void)
+{
+	setup_eimnor();
+
+	gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
index 626c1f94f9..c8199fa60a 100644
--- a/board/toradex/colibri-imx6ull/MAINTAINERS
+++ b/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -4,6 +4,8 @@ W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
 F:	arch/arm/dts/imx6ull-colibri.dts
+F:	arch/arm/dts/imx6ull-colibri-u-boot.dtsi
+F:	arch/arm/dts/imx6ull-colibri.dtsi
 F:	board/toradex/colibri-imx6ull/
 F:	configs/colibri-imx6ull_defconfig
 F:	include/configs/colibri-imx6ull.h
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 7df708de9b..b1e79b9ded 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -51,6 +51,11 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 						  CONFIG_SYS_OS_BASE,
 						  (void *)header);
 
+#if defined CONFIG_SYS_SPL_ARGS_ADDR && defined CONFIG_CMD_SPL_NOR_OFS
+			memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+			       (void *)CONFIG_CMD_SPL_NOR_OFS,
+			       CONFIG_CMD_SPL_WRITE_SIZE);
+#endif
 			return ret;
 		}
 #endif
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
new file mode 100644
index 0000000000..8f76262c5f
--- /dev/null
+++ b/configs/brppt2_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+# CONFIG_SPL_SYS_THUMB_BUILD is not set
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_TARGET_BRPPT2=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2"
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
+# CONFIG_EXPERT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_BOOTDELAY=0
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+# CONFIG_SPL_BLK is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MMC_BROKEN_CD=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_FIXED=y
+CONFIG_FEC_MXC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index db4753c5c7..072dcb20b5 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 3227249413..91b369532d 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_SAVEENV=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_FORCE_MMC_BOOT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index a934363277..4cbc62fd8f 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
@@ -20,10 +21,10 @@ CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
 CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
 CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_CMD_EXPORTENV is not set
@@ -65,6 +66,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index f352f47ed5..523dbf895b 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -25,7 +25,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
 CONFIG_DM_GPIO=y
diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig
new file mode 100644
index 0000000000..bbecea8e61
--- /dev/null
+++ b/configs/imx8qm_rom7720_a1_4G_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_IMX8QM_ROM7720_A1=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_rom7720_a1/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_MMC=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_ARCH_MISC_INIT
+CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 3d93c20999..2484e91635 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -62,6 +62,8 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index a738ddba7c..e2d3b84616 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -10,25 +10,44 @@ CONFIG_SPL=y
 # CONFIG_CMD_BMODE is not set
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0x8180000
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NOR_OFS=0x09600000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_FSL_USDHC=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_MMC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -37,16 +56,32 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_BUS=0
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
+CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 377c52a41a..45aba4bb06 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -11,25 +11,41 @@ CONFIG_SPL=y
 # CONFIG_CMD_BMODE is not set
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NOR_OFS=0x09600000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_FSL_USDHC=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_MMC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
@@ -38,16 +54,28 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
+CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 5eef6527cd..352d10a0d8 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -73,6 +73,8 @@ CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
@@ -93,6 +95,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
index 2f2fad2c17..1309215d4d 100644
--- a/drivers/misc/imx8/fuse.c
+++ b/drivers/misc/imx8/fuse.c
@@ -74,7 +74,7 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 	}
 
 	return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,
-			    (unsigned long)val, 0);
+			    (unsigned long)val, 0, 0);
 }
 
 int fuse_override(u32 bank, u32 word, u32 val)
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index a41b9620d0..ad7b644886 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -740,6 +740,19 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
 	d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
 	d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
 
+	if (is_mx7() && nand_info->en_randomizer) {
+		d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE |
+				       GPMI_ECCCTRL_RANDOMIZER_TYPE2;
+		/*
+		 * Write NAND page number needed to be randomized
+		 * to GPMI_ECCCOUNT register.
+		 *
+		 * The value is between 0-255. For additional details
+		 * check 9.6.6.4 of i.MX7D Applications Processor reference
+		 */
+		d->cmd.pio_words[3] |= (page % 255) << 16;
+	}
+
 	mxs_dma_desc_append(channel, d);
 
 	/* Flush caches */
@@ -1003,6 +1016,10 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
 	uint32_t tmp;
 	int ret;
 
+	nand_info->en_randomizer = 0;
+	nand_info->oobsize = mtd->oobsize;
+	nand_info->writesize = mtd->writesize;
+
 	ret = mxs_nand_set_geometry(mtd, geo);
 	if (ret)
 		return ret;
@@ -1020,6 +1037,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
 	tmp |= (geo->gf_len == 14 ? 1 : 0) <<
 		BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
 	writel(tmp, &bch_regs->hw_bch_flash0layout0);
+	nand_info->bch_flash0layout0 = tmp;
 
 	tmp = (mtd->writesize + mtd->oobsize)
 		<< BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
@@ -1028,6 +1046,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
 	tmp |= (geo->gf_len == 14 ? 1 : 0) <<
 		BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
 	writel(tmp, &bch_regs->hw_bch_flash0layout1);
+	nand_info->bch_flash0layout1 = tmp;
 
 	/* Set *all* chip selects to use layout 0 */
 	writel(0, &bch_regs->hw_bch_layoutselect);
@@ -1303,3 +1322,100 @@ err:
 	free(nand_info);
 }
 #endif
+
+/*
+ * Read NAND layout for FCB block generation.
+ */
+void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l)
+{
+	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
+	u32 tmp;
+
+	tmp = readl(&bch_regs->hw_bch_flash0layout0);
+	l->nblocks = (tmp & BCH_FLASHLAYOUT0_NBLOCKS_MASK) >>
+			BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
+	l->meta_size = (tmp & BCH_FLASHLAYOUT0_META_SIZE_MASK) >>
+			BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
+
+	tmp = readl(&bch_regs->hw_bch_flash0layout1);
+	l->data0_size = 4 * ((tmp & BCH_FLASHLAYOUT0_DATA0_SIZE_MASK) >>
+			BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET);
+	l->ecc0 = (tmp & BCH_FLASHLAYOUT0_ECC0_MASK) >>
+			BCH_FLASHLAYOUT0_ECC0_OFFSET;
+	l->datan_size = 4 * ((tmp & BCH_FLASHLAYOUT1_DATAN_SIZE_MASK) >>
+			BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET);
+	l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >>
+			BCH_FLASHLAYOUT1_ECCN_OFFSET;
+}
+
+/*
+ * Set BCH to specific layout used by ROM bootloader to read FCB.
+ */
+void mxs_nand_mode_fcb(struct mtd_info *mtd)
+{
+	u32 tmp;
+	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+
+	nand_info->en_randomizer = 1;
+
+	mtd->writesize = 1024;
+	mtd->oobsize = 1862 - 1024;
+
+	/* 8 ecc_chunks_*/
+	tmp = 7	<< BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
+	/* 32 bytes for metadata */
+	tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
+	/* using ECC62 level to be performed */
+	tmp |= 0x1F << BCH_FLASHLAYOUT0_ECC0_OFFSET;
+	/* 0x20 * 4 bytes of the data0 block */
+	tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET;
+	tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
+	writel(tmp, &bch_regs->hw_bch_flash0layout0);
+
+	/* 1024 for data + 838 for OOB */
+	tmp = 1862 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
+	/* using ECC62 level to be performed */
+	tmp |= 0x1F << BCH_FLASHLAYOUT1_ECCN_OFFSET;
+	/* 0x20 * 4 bytes of the data0 block */
+	tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET;
+	tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
+	writel(tmp, &bch_regs->hw_bch_flash0layout1);
+}
+
+/*
+ * Restore BCH to normal settings.
+ */
+void mxs_nand_mode_normal(struct mtd_info *mtd)
+{
+	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+
+	nand_info->en_randomizer = 0;
+
+	mtd->writesize = nand_info->writesize;
+	mtd->oobsize = nand_info->oobsize;
+
+	writel(nand_info->bch_flash0layout0, &bch_regs->hw_bch_flash0layout0);
+	writel(nand_info->bch_flash0layout1, &bch_regs->hw_bch_flash0layout1);
+}
+
+uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
+	struct bch_geometry *geo = &nand_info->bch_geometry;
+
+	return geo->block_mark_byte_offset;
+}
+
+uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
+	struct bch_geometry *geo = &nand_info->bch_geometry;
+
+	return geo->block_mark_bit_offset;
+}
diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c
index 164fb3d31d..40ece9ee3f 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -37,7 +37,8 @@ static int imx8m_power_domain_on(struct power_domain *power_domain)
 	if (pdata->has_pd)
 		power_domain_on(&pdata->pd);
 
-	call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 1);
+	call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		     pdata->resource_id, 1, 0);
 
 	return 0;
 }
@@ -51,7 +52,8 @@ static int imx8m_power_domain_off(struct power_domain *power_domain)
 	if (pdata->resource_id < 0)
 		return -EINVAL;
 
-	call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 0);
+	call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		     pdata->resource_id, 0, 0);
 
 	if (pdata->has_pd)
 		power_domain_off(&pdata->pd);
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 586772fdec..4718dc700c 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -55,6 +55,14 @@ config DM_PMIC_BD71837
 	  This config enables implementation of driver-model pmic uclass features
 	  for PMIC BD71837. The driver implements read/write operations.
 
+config SPL_DM_PMIC_BD71837
+	bool "Enable Driver Model for PMIC BD71837 in SPL stage"
+	depends on DM_PMIC
+	help
+	  This config enables implementation of driver-model pmic uclass
+	  features for PMIC BD71837. The driver implements read/write
+	  operations.
+
 config DM_PMIC_FAN53555
 	bool "Enable support for OnSemi FAN53555"
 	depends on DM_PMIC && DM_REGULATOR && DM_I2C
diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
index e292d42a8c..2e04298273 100644
--- a/drivers/power/pmic/bd71837.c
+++ b/drivers/power/pmic/bd71837.c
@@ -3,8 +3,6 @@
  * Copyright 2018 NXP
  */
 
-#define DEBUG
-
 #include <common.h>
 #include <errno.h>
 #include <dm.h>
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 6922a130c6..c52981053e 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -367,6 +367,7 @@ static int mxs_video_probe(struct udevice *dev)
 	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 					DCACHE_WRITEBACK);
 	video_set_flush_dcache(dev, true);
+	gd->fb_base = plat->base;
 
 	return ret;
 }
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 53a3e9f5c7..c030360c21 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -15,15 +15,23 @@
 #endif
 #include <fsl_wdog.h>
 
-static void imx_watchdog_expire_now(struct watchdog_regs *wdog)
+static void imx_watchdog_expire_now(struct watchdog_regs *wdog, bool ext_reset)
 {
-	clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
+	u16 wcr = WCR_WDE;
+
+	if (ext_reset)
+		wcr |= WCR_SRS; /* do not assert internal reset */
+	else
+		wcr |= WCR_WDA; /* do not assert external reset */
+
+	/* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
+	writew(wcr, &wdog->wcr);
+	writew(wcr, &wdog->wcr);
+	writew(wcr, &wdog->wcr);
 
-	writew(0x5555, &wdog->wsr);
-	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
 	while (1) {
 		/*
-		 * spin for .5 seconds before reset
+		 * spin before reset
 		 */
 	}
 }
@@ -34,7 +42,7 @@ void __attribute__((weak)) reset_cpu(ulong addr)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-	imx_watchdog_expire_now(wdog);
+	imx_watchdog_expire_now(wdog, true);
 }
 #endif
 
@@ -47,9 +55,10 @@ static void imx_watchdog_reset(struct watchdog_regs *wdog)
 #endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
 }
 
-static void imx_watchdog_init(struct watchdog_regs *wdog)
+static void imx_watchdog_init(struct watchdog_regs *wdog, bool ext_reset)
 {
 	u16 timeout;
+	u16 wcr;
 
 	/*
 	 * The timer watchdog can be set between
@@ -61,11 +70,14 @@ static void imx_watchdog_init(struct watchdog_regs *wdog)
 #endif
 	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
 #ifdef CONFIG_FSL_LSCH2
-	writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
+	wcr = (WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout;
 #else
-	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
-		WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
+	wcr = WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_SRS |
+		WCR_WDA | SET_WCR_WT(timeout);
+	if (ext_reset)
+		wcr |= WCR_WDT;
 #endif /* CONFIG_FSL_LSCH2*/
+	writew(wcr, &wdog->wcr);
 	imx_watchdog_reset(wdog);
 }
 
@@ -81,11 +93,12 @@ void hw_watchdog_init(void)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-	imx_watchdog_init(wdog);
+	imx_watchdog_init(wdog, true);
 }
 #else
 struct imx_wdt_priv {
 	void __iomem *base;
+	bool ext_reset;
 };
 
 static int imx_wdt_reset(struct udevice *dev)
@@ -101,7 +114,7 @@ static int imx_wdt_expire_now(struct udevice *dev, ulong flags)
 {
 	struct imx_wdt_priv *priv = dev_get_priv(dev);
 
-	imx_watchdog_expire_now(priv->base);
+	imx_watchdog_expire_now(priv->base, priv->ext_reset);
 	hang();
 
 	return 0;
@@ -111,7 +124,7 @@ static int imx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 {
 	struct imx_wdt_priv *priv = dev_get_priv(dev);
 
-	imx_watchdog_init(priv->base);
+	imx_watchdog_init(priv->base, priv->ext_reset);
 
 	return 0;
 }
@@ -124,6 +137,8 @@ static int imx_wdt_probe(struct udevice *dev)
 	if (!priv->base)
 		return -ENOENT;
 
+	priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
+
 	return 0;
 }
 
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
new file mode 100644
index 0000000000..d369315090
--- /dev/null
+++ b/include/configs/brppt2.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Config file for BuR BRPP2_IMX6 board
+ *
+ * Copyright (C) 2018
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ */
+#ifndef __CONFIG_BRPP2_IMX6_H
+#define __CONFIG_BRPP2_IMX6_H
+
+#include <configs/bur_cfg_common.h>
+#include <asm/arch/imx-regs.h>
+
+/* -- i.mx6 specifica -- */
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		L2_PL310_BASE
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_MXC_GPT_HCLK
+
+#define CONFIG_LOADADDR			0x10700000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* MMC */
+#define CONFIG_FSL_USDHC
+
+/* Boot */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MACH_TYPE		0xFFFFFFFF
+
+/* misc */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_OFFSET		0x20000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+BUR_COMMON_ENV \
+"autoload=0\0" \
+"cfgaddr=0x106F0000\0" \
+"scraddr=0x10700000\0" \
+"loadaddr=0x10800000\0" \
+"dtbaddr=0x12000000\0" \
+"ramaddr=0x12100000\0" \
+"cfgscr=mw ${loadaddr} 0 128\0" \
+"cfgscrl=fdt addr ${dtbaddr} &&"\
+" sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \
+"console=ttymxc0,115200n8 consoleblank=0 quiet\0" \
+"t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \
+	" root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \
+"b_t50lgcy#0=" \
+	"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
+	"load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \
+	"run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \
+"t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \
+	" rootwait panic=2\0" \
+"b_t50lgcy#1=" \
+	"load ${loaddev}:1 ${loadaddr} zImage && " \
+	"load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \
+	"load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \
+	"run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\
+"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
+"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
+"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
+"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
+"b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \
+"b_tgts_rcy=t50lgcy#1 usb0 net\0" \
+"b_tgts_pme=net usb0 mmc0 mmc1\0" \
+"b_mode=4\0" \
+"b_break=0\0" \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do echo \"### booting ${target} ###\"; run b_${target};" \
+" if test ${b_break} = 1; then; exit; fi; done\0" \
+"loaddev=mmc 0\0" \
+"altbootcmd=setenv b_mode 0; run b_default;\0" \
+"bootlimit=1\0" \
+"net2nor=sf probe && dhcp &&" \
+" tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \
+" sf write ${loadaddr} 400 ${filesize} &&" \
+" tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \
+" sf write ${loadaddr} 0x100000 ${filesize}\0"
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Ethernet */
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_FIXED_SPEED		_1000BASET
+#define CONFIG_ARP_TIMEOUT		1500UL
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+
+/* SPL */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#endif	/* CONFIG_SPL */
+#endif	/* __CONFIG_BRPP2_IMX6_H */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index d4d8d20850..84fae34777 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -107,7 +107,7 @@
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \
-	"fdt_file=fsl-imx8mq-evk.dtb\0" \
+	"fdt_file=imx8mq-evk.dtb\0" \
 	"initrd_addr=0x43800000\0"		\
 	"initrd_high=0xffffffffffffffff\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 2b8f85ded1..37ef595e4e 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -54,8 +54,15 @@
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	AHAB_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
@@ -76,16 +83,27 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
 			"else " \
-				"echo WARN: Cannot load the DT; " \
+				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
-			"echo wait for boot; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console} " \
 		"root=/dev/nfs " \
@@ -97,15 +115,24 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
 			"else " \
-				"echo WARN: Cannot load the DT; " \
+				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
-			"booti; " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"booti ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -113,10 +140,17 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loadimage; then " \
-				   "run mmcboot; " \
-			   "else run netboot; " \
-			   "fi; " \
+			   "if test ${sec_boot} = yes; then " \
+				   "if run loadcntr; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			    "else " \
+				   "if run loadimage; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			 "fi; " \
 		   "fi; " \
 	   "else booti ${loadaddr} - ${fdt_addr}; fi"
 
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
new file mode 100644
index 0000000000..fb31dc4627
--- /dev/null
+++ b/include/configs/imx8qm_rom7720.h
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __IMX8QM_ROM7720_H
+#define __IMX8QM_ROM7720_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE	0x1000  /* 4 KB */
+
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* FUSE command */
+#define CONFIG_CMD_FUSE
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"m4_1_image=m4_1.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+	"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=imx8qm-rom7720-a1.dtb\0" \
+	"initrd_addr=0x83800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE			0x2000
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_OFFSET	(4 * 1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE	CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#else
+#define CONFIG_ENV_OFFSET	(64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board,
+ * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
+ * USDHC2 is for SD, USDHC3 is for SD on base board
+ */
+#define CONFIG_SYS_MMC_ENV_DEV		2   /* USDHC3 */
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */
+#define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
+
+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QM_ROM7720_H */
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 872805cae6..59f88bd203 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -53,8 +53,15 @@
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	AHAB_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
@@ -75,16 +82,27 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
 			"else " \
-				"echo WARN: Cannot load the DT; " \
+				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
-			"echo wait for boot; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console} " \
 		"root=/dev/nfs " \
@@ -96,15 +114,24 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
 			"else " \
-				"echo WARN: Cannot load the DT; " \
+				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
-			"booti; " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -112,10 +139,17 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loadimage; then " \
-				   "run mmcboot; " \
-			   "else run netboot; " \
-			   "fi; " \
+			   "if test ${sec_boot} = yes; then " \
+				   "if run loadcntr; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			    "else " \
+				   "if run loadimage; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			 "fi; " \
 		   "fi; " \
 	   "else booti ${loadaddr} - ${fdt_addr}; fi"
 
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 667dac7340..c685de6551 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -14,10 +14,6 @@
 
 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
-#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
 
 /*
@@ -28,28 +24,17 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage"
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
 
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED		100000
-
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
@@ -66,22 +51,18 @@
 #define CONFIG_SYS_FLASH_BANKS_SIZES	{ (32 * SZ_1M) }
 
 /* Ethernet Configuration */
-#define CONFIG_FEC_MXC
 #define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		1
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=ttymxc0,115200 quiet\0" \
-	"fdtfile=imx6q-mccmon6.dtb\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"boot_os=yes\0" \
+	"kernelsize=0x300000\0" \
 	"disable_giga=yes\0" \
 	"download_kernel=" \
-		"tftpboot ${kernel_addr} ${kernel_file};" \
-		"tftpboot ${fdt_addr} ${fdtfile};\0" \
+		"tftpboot ${loadaddr} ${kernel_file};\0" \
 	"get_boot_medium=" \
 		"setenv boot_medium nor;" \
 		"setexpr.l _src_sbmr1 *0x020d8004;" \
@@ -89,10 +70,7 @@
 		"if test ${_b_medium} = 40; then " \
 			"setenv boot_medium sdcard;" \
 		"fi\0" \
-	"kernel_file=uImage\0" \
-	"load_kernel=" \
-		"load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
-		"load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
+	"kernel_file=fitImage\0" \
 	"boot_sd=" \
 		"echo '#######################';" \
 		"echo '# Factory SDcard Boot #';" \
@@ -103,12 +81,11 @@
 		"run factory_flash_img;\0" \
 	"boot_nor=" \
 		"setenv kernelnor 0x08180000;" \
-		"setenv dtbnor 0x09980000;" \
 		"setenv bootargs console=${console} " \
 		CONFIG_MTDPARTS_DEFAULT " " \
 		"root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
-		"cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
-		"bootm ${kernelnor} - ${dtbloadaddr};\0" \
+		"cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \
+		"bootm ${loadaddr};reset;\0" \
 	"boot_recovery=" \
 		"echo '#######################';" \
 		"echo '# RECOVERY SWU Boot   #';" \
@@ -116,14 +93,13 @@
 		"setenv rootfsloadaddr 0x13000000;" \
 		"setenv swukernelnor 0x08980000;" \
 		"setenv swurootfsnor 0x09180000;" \
-		"setenv swudtbnor 0x099A0000;" \
 		"setenv bootargs console=${console} " \
 		CONFIG_MTDPARTS_DEFAULT " " \
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
 		    ":${hostname}::off root=/dev/ram rw;" \
 		"cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
-		"cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
-		"bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
+		"cp.l ${swukernelnor} ${loadaddr} ${kernelsize};" \
+		"bootm ${loadaddr} ${rootfsloadaddr};reset;\0" \
 	"boot_tftp=" \
 		"echo '#######################';" \
 		"echo '# TFTP Boot           #';" \
@@ -131,7 +107,7 @@
 		"if run download_kernel; then " \
 		     "setenv bootargs console=${console} " \
 		     "root=/dev/mmcblk0p2 rootwait;" \
-		     "bootm ${kernel_addr} - ${fdt_addr};" \
+		     "bootm $loadaddr};reset;" \
 		"fi\0" \
 	"bootcmd=" \
 		"if test -n ${recovery_status}; then " \
@@ -151,13 +127,10 @@
 		     "fi;" \
 		"fi\0" \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-	"fdt_addr=0x18000000\0" \
 	"bootdev=1\0" \
 	"bootpart=1\0" \
-	"kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
 	"netdev=eth0\0" \
 	"load_addr=0x11000000\0" \
-	"dtbloadaddr=0x12000000\0" \
 	"uboot_file=u-boot.img\0" \
 	"SPL_file=SPL\0" \
 	"load_uboot=tftp ${load_addr} ${uboot_file}\0" \
@@ -184,6 +157,7 @@
 		    "device ${mmcdev};" \
 		    "run factory_nor_img;" \
 		    "run factory_eMMC_img;" \
+		    "run factory_SPL_falcon_setup;" \
 		"fi\0" \
 	"factory_eMMC_img="\
 		"echo 'Update mccmon6 eMMC image'; " \
@@ -205,6 +179,16 @@
 		    "erase ${nor_bank_start} +${nor_img_size};" \
 		    "setexpr nor_img_size ${nor_img_size} / 4; " \
 		    "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
+	"factory_SPL_falcon_setup="\
+		"echo 'Write Falcon boot data'; " \
+		"setenv kernelnor 0x08180000;" \
+		"cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \
+		"spl export fdt ${loadaddr};" \
+		"setenv nor_img_addr ${fdtargsaddr};" \
+		"setenv nor_img_size 0x20000;" \
+		"setenv nor_bank_start " \
+				__stringify(CONFIG_CMD_SPL_NOR_OFS)";" \
+		"run nor_update\0" \
 	"tftp_nor_uboot="\
 		"echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
 		"setenv nor_img_file u-boot.img; " \
@@ -213,22 +197,14 @@
 		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
 		    "run nor_update;" \
 		"fi\0" \
-	"tftp_nor_uImg="\
-		"echo 'Update mccmon6 NOR uImage via TFTP'; " \
-		"setenv nor_img_file uImage; " \
+	"tftp_nor_fitImg="\
+		"echo 'Update mccmon6 NOR fitImage via TFTP'; " \
+		"setenv nor_img_file fitImage; " \
 		"setenv nor_img_size 0x500000; " \
 		"setenv nor_bank_start 0x08180000; " \
 		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
 		    "run nor_update;" \
 		"fi\0" \
-	"tftp_nor_dtb="\
-		"echo 'Update mccmon6 NOR DTB via TFTP'; " \
-		"setenv nor_img_file imx6q-mccmon6.dtb; " \
-		"setenv nor_img_size 0x20000; " \
-		"setenv nor_bank_start 0x09980000; " \
-		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
-		    "run nor_update;" \
-		"fi\0" \
 	"tftp_nor_img="\
 		"echo 'Update mccmon6 NOR image via TFTP'; " \
 		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index 309b4717c4..f80e34729a 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -41,17 +41,9 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 
-/* Ethernet */
-#ifdef CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x1
-#define CONFIG_FEC_XCV_TYPE             RMII
-#define CONFIG_ETHPRIME			"FEC"
-#endif
-
 /* LCD */
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
@@ -59,6 +51,8 @@
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
 #define CONFIG_VIDEO_MXS
 #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
 #endif
@@ -95,6 +89,8 @@
 	"mmcroot=/dev/mmcblk0p2 ro\0"                                                           \
 	"mmcrootfstype=ext4 rootwait\0"                                                         \
 	"kernelimg="           __stringify(CONFIG_BOARD_NAME)          "-linux.bin\0"           \
+	"splashpos=0,0\0"									\
+	"splashimage="		__stringify(CONFIG_LOADADDR) 		"\0"			\
 	"videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \
 	"check_env=if test -n ${flash_env_version}; "                                           \
 		"then env default env_version; "                                                \
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 11dcafcfde..65463673d2 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -1,10 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
@@ -148,465 +145,263 @@
 
 /* BUS TYPE */
 /* MAIN AXI */
-#define IMX8MQ_CLK_MAIN_AXI_SRC		103
-#define IMX8MQ_CLK_MAIN_AXI_CG		104
-#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV	105
-#define IMX8MQ_CLK_MAIN_AXI_DIV		106
+#define IMX8MQ_CLK_MAIN_AXI		103
 /* ENET AXI */
-#define IMX8MQ_CLK_ENET_AXI_SRC		107
-#define IMX8MQ_CLK_ENET_AXI_CG		108
-#define IMX8MQ_CLK_ENET_AXI_PRE_DIV	109
-#define IMX8MQ_CLK_ENET_AXI_DIV		110
+#define IMX8MQ_CLK_ENET_AXI		104
 /* NAND_USDHC_BUS */
-#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC		111
-#define IMX8MQ_CLK_NAND_USDHC_BUS_CG		112
-#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV	113
-#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV		114
+#define IMX8MQ_CLK_NAND_USDHC_BUS	105
 /* VPU BUS */
-#define IMX8MQ_CLK_VPU_BUS_SRC			115
-#define IMX8MQ_CLK_VPU_BUS_CG			116
-#define IMX8MQ_CLK_VPU_BUS_PRE_DIV		117
-#define IMX8MQ_CLK_VPU_BUS_DIV			118
+#define IMX8MQ_CLK_VPU_BUS		106
 /* DISP_AXI */
-#define IMX8MQ_CLK_DISP_AXI_SRC			119
-#define IMX8MQ_CLK_DISP_AXI_CG			120
-#define IMX8MQ_CLK_DISP_AXI_PRE_DIV		121
-#define IMX8MQ_CLK_DISP_AXI_DIV			122
+#define IMX8MQ_CLK_DISP_AXI		107
 /* DISP APB */
-#define IMX8MQ_CLK_DISP_APB_SRC			123
-#define IMX8MQ_CLK_DISP_APB_CG			124
-#define IMX8MQ_CLK_DISP_APB_PRE_DIV		125
-#define IMX8MQ_CLK_DISP_APB_DIV			126
+#define IMX8MQ_CLK_DISP_APB		108
 /* DISP RTRM */
-#define IMX8MQ_CLK_DISP_RTRM_SRC		127
-#define IMX8MQ_CLK_DISP_RTRM_CG			128
-#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV		129
-#define IMX8MQ_CLK_DISP_RTRM_DIV		130
+#define IMX8MQ_CLK_DISP_RTRM		109
 /* USB_BUS */
-#define IMX8MQ_CLK_USB_BUS_SRC			131
-#define IMX8MQ_CLK_USB_BUS_CG			132
-#define IMX8MQ_CLK_USB_BUS_PRE_DIV		133
-#define IMX8MQ_CLK_USB_BUS_DIV			134
+#define IMX8MQ_CLK_USB_BUS		110
 /* GPU_AXI */
-#define IMX8MQ_CLK_GPU_AXI_SRC			135
-#define IMX8MQ_CLK_GPU_AXI_CG			136
-#define IMX8MQ_CLK_GPU_AXI_PRE_DIV		137
-#define IMX8MQ_CLK_GPU_AXI_DIV			138
+#define IMX8MQ_CLK_GPU_AXI		111
 /* GPU_AHB */
-#define IMX8MQ_CLK_GPU_AHB_SRC			139
-#define IMX8MQ_CLK_GPU_AHB_CG			140
-#define IMX8MQ_CLK_GPU_AHB_PRE_DIV		141
-#define IMX8MQ_CLK_GPU_AHB_DIV			142
+#define IMX8MQ_CLK_GPU_AHB		112
 /* NOC */
-#define IMX8MQ_CLK_NOC_SRC			143
-#define IMX8MQ_CLK_NOC_CG			144
-#define IMX8MQ_CLK_NOC_PRE_DIV			145
-#define IMX8MQ_CLK_NOC_DIV			146
+#define IMX8MQ_CLK_NOC			113
 /* NOC_APB */
-#define IMX8MQ_CLK_NOC_APB_SRC			147
-#define IMX8MQ_CLK_NOC_APB_CG			148
-#define IMX8MQ_CLK_NOC_APB_PRE_DIV		149
-#define IMX8MQ_CLK_NOC_APB_DIV			150
+#define IMX8MQ_CLK_NOC_APB		115
 
 /* AHB */
-#define IMX8MQ_CLK_AHB_SRC			151
-#define IMX8MQ_CLK_AHB_CG			152
-#define IMX8MQ_CLK_AHB_PRE_DIV			153
-#define IMX8MQ_CLK_AHB_DIV			154
+#define IMX8MQ_CLK_AHB			116
 /* AUDIO AHB */
-#define IMX8MQ_CLK_AUDIO_AHB_SRC		155
-#define IMX8MQ_CLK_AUDIO_AHB_CG			156
-#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV		157
-#define IMX8MQ_CLK_AUDIO_AHB_DIV		158
+#define IMX8MQ_CLK_AUDIO_AHB		117
 
 /* DRAM_ALT */
-#define IMX8MQ_CLK_DRAM_ALT_SRC			159
-#define IMX8MQ_CLK_DRAM_ALT_CG			160
-#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV		161
-#define IMX8MQ_CLK_DRAM_ALT_DIV			162
+#define IMX8MQ_CLK_DRAM_ALT		118
 /* DRAM APB */
-#define IMX8MQ_CLK_DRAM_APB_SRC			163
-#define IMX8MQ_CLK_DRAM_APB_CG			164
-#define IMX8MQ_CLK_DRAM_APB_PRE_DIV		165
-#define IMX8MQ_CLK_DRAM_APB_DIV			166
+#define IMX8MQ_CLK_DRAM_APB		119
 /* VPU_G1 */
-#define IMX8MQ_CLK_VPU_G1_SRC			167
-#define IMX8MQ_CLK_VPU_G1_CG			168
-#define IMX8MQ_CLK_VPU_G1_PRE_DIV		169
-#define IMX8MQ_CLK_VPU_G1_DIV			170
+#define IMX8MQ_CLK_VPU_G1		120
 /* VPU_G2 */
-#define IMX8MQ_CLK_VPU_G2_SRC			171
-#define IMX8MQ_CLK_VPU_G2_CG			172
-#define IMX8MQ_CLK_VPU_G2_PRE_DIV		173
-#define IMX8MQ_CLK_VPU_G2_DIV			174
+#define IMX8MQ_CLK_VPU_G2		121
 /* DISP_DTRC */
-#define IMX8MQ_CLK_DISP_DTRC_SRC		175
-#define IMX8MQ_CLK_DISP_DTRC_CG			176
-#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV		177
-#define IMX8MQ_CLK_DISP_DTRC_DIV		178
+#define IMX8MQ_CLK_DISP_DTRC		122
 /* DISP_DC8000 */
-#define IMX8MQ_CLK_DISP_DC8000_SRC		179
-#define IMX8MQ_CLK_DISP_DC8000_CG		180
-#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV		181
-#define IMX8MQ_CLK_DISP_DC8000_DIV		182
+#define IMX8MQ_CLK_DISP_DC8000		123
 /* PCIE_CTRL */
-#define IMX8MQ_CLK_PCIE1_CTRL_SRC		183
-#define IMX8MQ_CLK_PCIE1_CTRL_CG		184
-#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV		185
-#define IMX8MQ_CLK_PCIE1_CTRL_DIV		186
+#define IMX8MQ_CLK_PCIE1_CTRL		124
 /* PCIE_PHY */
-#define IMX8MQ_CLK_PCIE1_PHY_SRC		187
-#define IMX8MQ_CLK_PCIE1_PHY_CG			188
-#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV		189
-#define IMX8MQ_CLK_PCIE1_PHY_DIV		190
+#define IMX8MQ_CLK_PCIE1_PHY		125
 /* PCIE_AUX */
-#define IMX8MQ_CLK_PCIE1_AUX_SRC		191
-#define IMX8MQ_CLK_PCIE1_AUX_CG			192
-#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV		193
-#define IMX8MQ_CLK_PCIE1_AUX_DIV		194
+#define IMX8MQ_CLK_PCIE1_AUX		126
 /* DC_PIXEL */
-#define IMX8MQ_CLK_DC_PIXEL_SRC			195
-#define IMX8MQ_CLK_DC_PIXEL_CG			196
-#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV		197
-#define IMX8MQ_CLK_DC_PIXEL_DIV			198
+#define IMX8MQ_CLK_DC_PIXEL		127
 /* LCDIF_PIXEL */
-#define IMX8MQ_CLK_LCDIF_PIXEL_SRC		199
-#define IMX8MQ_CLK_LCDIF_PIXEL_CG		200
-#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV		201
-#define IMX8MQ_CLK_LCDIF_PIXEL_DIV		202
+#define IMX8MQ_CLK_LCDIF_PIXEL		128
 /* SAI1~6 */
-#define IMX8MQ_CLK_SAI1_SRC			203
-#define IMX8MQ_CLK_SAI1_CG			204
-#define IMX8MQ_CLK_SAI1_PRE_DIV			205
-#define IMX8MQ_CLK_SAI1_DIV			206
-
-#define IMX8MQ_CLK_SAI2_SRC			207
-#define IMX8MQ_CLK_SAI2_CG			208
-#define IMX8MQ_CLK_SAI2_PRE_DIV			209
-#define IMX8MQ_CLK_SAI2_DIV			210
-
-#define IMX8MQ_CLK_SAI3_SRC			211
-#define IMX8MQ_CLK_SAI3_CG			212
-#define IMX8MQ_CLK_SAI3_PRE_DIV			213
-#define IMX8MQ_CLK_SAI3_DIV			214
-
-#define IMX8MQ_CLK_SAI4_SRC			215
-#define IMX8MQ_CLK_SAI4_CG			216
-#define IMX8MQ_CLK_SAI4_PRE_DIV			217
-#define IMX8MQ_CLK_SAI4_DIV			218
-
-#define IMX8MQ_CLK_SAI5_SRC			219
-#define IMX8MQ_CLK_SAI5_CG			220
-#define IMX8MQ_CLK_SAI5_PRE_DIV			221
-#define IMX8MQ_CLK_SAI5_DIV			222
-
-#define IMX8MQ_CLK_SAI6_SRC			223
-#define IMX8MQ_CLK_SAI6_CG			224
-#define IMX8MQ_CLK_SAI6_PRE_DIV			225
-#define IMX8MQ_CLK_SAI6_DIV			226
+#define IMX8MQ_CLK_SAI1			129
+
+#define IMX8MQ_CLK_SAI2			130
+
+#define IMX8MQ_CLK_SAI3			131
+
+#define IMX8MQ_CLK_SAI4			132
+
+#define IMX8MQ_CLK_SAI5			133
+
+#define IMX8MQ_CLK_SAI6			134
 /* SPDIF1 */
-#define IMX8MQ_CLK_SPDIF1_SRC			227
-#define IMX8MQ_CLK_SPDIF1_CG			228
-#define IMX8MQ_CLK_SPDIF1_PRE_DIV		229
-#define IMX8MQ_CLK_SPDIF1_DIV			230
+#define IMX8MQ_CLK_SPDIF1		135
 /* SPDIF2 */
-#define IMX8MQ_CLK_SPDIF2_SRC			231
-#define IMX8MQ_CLK_SPDIF2_CG			232
-#define IMX8MQ_CLK_SPDIF2_PRE_DIV		233
-#define IMX8MQ_CLK_SPDIF2_DIV			234
+#define IMX8MQ_CLK_SPDIF2		136
 /* ENET_REF */
-#define IMX8MQ_CLK_ENET_REF_SRC			235
-#define IMX8MQ_CLK_ENET_REF_CG			236
-#define IMX8MQ_CLK_ENET_REF_PRE_DIV		237
-#define IMX8MQ_CLK_ENET_REF_DIV			238
+#define IMX8MQ_CLK_ENET_REF		137
 /* ENET_TIMER */
-#define IMX8MQ_CLK_ENET_TIMER_SRC		239
-#define IMX8MQ_CLK_ENET_TIMER_CG		240
-#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV		241
-#define IMX8MQ_CLK_ENET_TIMER_DIV		242
+#define IMX8MQ_CLK_ENET_TIMER		138
 /* ENET_PHY */
-#define IMX8MQ_CLK_ENET_PHY_REF_SRC		243
-#define IMX8MQ_CLK_ENET_PHY_REF_CG		244
-#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV		245
-#define IMX8MQ_CLK_ENET_PHY_REF_DIV		246
+#define IMX8MQ_CLK_ENET_PHY_REF		139
 /* NAND */
-#define IMX8MQ_CLK_NAND_SRC			247
-#define IMX8MQ_CLK_NAND_CG			248
-#define IMX8MQ_CLK_NAND_PRE_DIV			249
-#define IMX8MQ_CLK_NAND_DIV			250
+#define IMX8MQ_CLK_NAND			140
 /* QSPI */
-#define IMX8MQ_CLK_QSPI_SRC			251
-#define IMX8MQ_CLK_QSPI_CG			252
-#define IMX8MQ_CLK_QSPI_PRE_DIV			253
-#define IMX8MQ_CLK_QSPI_DIV			254
+#define IMX8MQ_CLK_QSPI			141
 /* USDHC1 */
-#define IMX8MQ_CLK_USDHC1_SRC			255
-#define IMX8MQ_CLK_USDHC1_CG			256
-#define IMX8MQ_CLK_USDHC1_PRE_DIV		257
-#define IMX8MQ_CLK_USDHC1_DIV			258
+#define IMX8MQ_CLK_USDHC1		142
 /* USDHC2 */
-#define IMX8MQ_CLK_USDHC2_SRC			259
-#define IMX8MQ_CLK_USDHC2_CG			260
-#define IMX8MQ_CLK_USDHC2_PRE_DIV		261
-#define IMX8MQ_CLK_USDHC2_DIV			262
+#define IMX8MQ_CLK_USDHC2		143
 /* I2C1 */
-#define IMX8MQ_CLK_I2C1_SRC			263
-#define IMX8MQ_CLK_I2C1_CG			264
-#define IMX8MQ_CLK_I2C1_PRE_DIV			265
-#define IMX8MQ_CLK_I2C1_DIV			266
+#define IMX8MQ_CLK_I2C1			144
 /* I2C2 */
-#define IMX8MQ_CLK_I2C2_SRC			267
-#define IMX8MQ_CLK_I2C2_CG			268
-#define IMX8MQ_CLK_I2C2_PRE_DIV			269
-#define IMX8MQ_CLK_I2C2_DIV			270
+#define IMX8MQ_CLK_I2C2			145
 /* I2C3 */
-#define IMX8MQ_CLK_I2C3_SRC			271
-#define IMX8MQ_CLK_I2C3_CG			272
-#define IMX8MQ_CLK_I2C3_PRE_DIV			273
-#define IMX8MQ_CLK_I2C3_DIV			274
+#define IMX8MQ_CLK_I2C3			146
 /* I2C4 */
-#define IMX8MQ_CLK_I2C4_SRC			275
-#define IMX8MQ_CLK_I2C4_CG			276
-#define IMX8MQ_CLK_I2C4_PRE_DIV			277
-#define IMX8MQ_CLK_I2C4_DIV			278
+#define IMX8MQ_CLK_I2C4			147
 /* UART1 */
-#define IMX8MQ_CLK_UART1_SRC			279
-#define IMX8MQ_CLK_UART1_CG			280
-#define IMX8MQ_CLK_UART1_PRE_DIV		281
-#define IMX8MQ_CLK_UART1_DIV			282
+#define IMX8MQ_CLK_UART1		148
 /* UART2 */
-#define IMX8MQ_CLK_UART2_SRC			283
-#define IMX8MQ_CLK_UART2_CG			284
-#define IMX8MQ_CLK_UART2_PRE_DIV		285
-#define IMX8MQ_CLK_UART2_DIV			286
+#define IMX8MQ_CLK_UART2		149
 /* UART3 */
-#define IMX8MQ_CLK_UART3_SRC			287
-#define IMX8MQ_CLK_UART3_CG			288
-#define IMX8MQ_CLK_UART3_PRE_DIV		289
-#define IMX8MQ_CLK_UART3_DIV			290
+#define IMX8MQ_CLK_UART3		150
 /* UART4 */
-#define IMX8MQ_CLK_UART4_SRC			291
-#define IMX8MQ_CLK_UART4_CG			292
-#define IMX8MQ_CLK_UART4_PRE_DIV		293
-#define IMX8MQ_CLK_UART4_DIV			294
+#define IMX8MQ_CLK_UART4		151
 /* USB_CORE_REF */
-#define IMX8MQ_CLK_USB_CORE_REF_SRC		295
-#define IMX8MQ_CLK_USB_CORE_REF_CG		296
-#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV		297
-#define IMX8MQ_CLK_USB_CORE_REF_DIV		298
+#define IMX8MQ_CLK_USB_CORE_REF		152
 /* USB_PHY_REF */
-#define IMX8MQ_CLK_USB_PHY_REF_SRC		299
-#define IMX8MQ_CLK_USB_PHY_REF_CG		300
-#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV		301
-#define IMX8MQ_CLK_USB_PHY_REF_DIV		302
+#define IMX8MQ_CLK_USB_PHY_REF		153
 /* ECSPI1 */
-#define IMX8MQ_CLK_ECSPI1_SRC			303
-#define IMX8MQ_CLK_ECSPI1_CG			304
-#define IMX8MQ_CLK_ECSPI1_PRE_DIV		305
-#define IMX8MQ_CLK_ECSPI1_DIV			306
+#define IMX8MQ_CLK_ECSPI1		154
 /* ECSPI2 */
-#define IMX8MQ_CLK_ECSPI2_SRC			307
-#define IMX8MQ_CLK_ECSPI2_CG			308
-#define IMX8MQ_CLK_ECSPI2_PRE_DIV		309
-#define IMX8MQ_CLK_ECSPI2_DIV			310
+#define IMX8MQ_CLK_ECSPI2		155
 /* PWM1 */
-#define IMX8MQ_CLK_PWM1_SRC			311
-#define IMX8MQ_CLK_PWM1_CG			312
-#define IMX8MQ_CLK_PWM1_PRE_DIV			313
-#define IMX8MQ_CLK_PWM1_DIV			314
+#define IMX8MQ_CLK_PWM1			156
 /* PWM2 */
-#define IMX8MQ_CLK_PWM2_SRC			315
-#define IMX8MQ_CLK_PWM2_CG			316
-#define IMX8MQ_CLK_PWM2_PRE_DIV			317
-#define IMX8MQ_CLK_PWM2_DIV			318
+#define IMX8MQ_CLK_PWM2			157
 /* PWM3 */
-#define IMX8MQ_CLK_PWM3_SRC			319
-#define IMX8MQ_CLK_PWM3_CG			320
-#define IMX8MQ_CLK_PWM3_PRE_DIV			321
-#define IMX8MQ_CLK_PWM3_DIV			322
+#define IMX8MQ_CLK_PWM3			158
 /* PWM4 */
-#define IMX8MQ_CLK_PWM4_SRC			323
-#define IMX8MQ_CLK_PWM4_CG			324
-#define IMX8MQ_CLK_PWM4_PRE_DIV			325
-#define IMX8MQ_CLK_PWM4_DIV			326
+#define IMX8MQ_CLK_PWM4			159
 /* GPT1 */
-#define IMX8MQ_CLK_GPT1_SRC			327
-#define IMX8MQ_CLK_GPT1_CG			328
-#define IMX8MQ_CLK_GPT1_PRE_DIV			329
-#define IMX8MQ_CLK_GPT1_DIV			330
+#define IMX8MQ_CLK_GPT1			160
 /* WDOG */
-#define IMX8MQ_CLK_WDOG_SRC			331
-#define IMX8MQ_CLK_WDOG_CG			332
-#define IMX8MQ_CLK_WDOG_PRE_DIV			333
-#define IMX8MQ_CLK_WDOG_DIV			334
+#define IMX8MQ_CLK_WDOG			161
 /* WRCLK */
-#define IMX8MQ_CLK_WRCLK_SRC			335
-#define IMX8MQ_CLK_WRCLK_CG			336
-#define IMX8MQ_CLK_WRCLK_PRE_DIV		337
-#define IMX8MQ_CLK_WRCLK_DIV			338
+#define IMX8MQ_CLK_WRCLK		162
 /* DSI_CORE */
-#define IMX8MQ_CLK_DSI_CORE_SRC			339
-#define IMX8MQ_CLK_DSI_CORE_CG			340
-#define IMX8MQ_CLK_DSI_CORE_PRE_DIV		341
-#define IMX8MQ_CLK_DSI_CORE_DIV			342
+#define IMX8MQ_CLK_DSI_CORE		163
 /* DSI_PHY */
-#define IMX8MQ_CLK_DSI_PHY_REF_SRC		343
-#define IMX8MQ_CLK_DSI_PHY_REF_CG		344
-#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV		345
-#define IMX8MQ_CLK_DSI_PHY_REF_DIV		346
+#define IMX8MQ_CLK_DSI_PHY_REF		164
 /* DSI_DBI */
-#define IMX8MQ_CLK_DSI_DBI_SRC			347
-#define IMX8MQ_CLK_DSI_DBI_CG			348
-#define IMX8MQ_CLK_DSI_DBI_PRE_DIV		349
-#define IMX8MQ_CLK_DSI_DBI_DIV			350
+#define IMX8MQ_CLK_DSI_DBI		165
 /*DSI_ESC */
-#define IMX8MQ_CLK_DSI_ESC_SRC			351
-#define IMX8MQ_CLK_DSI_ESC_CG			352
-#define IMX8MQ_CLK_DSI_ESC_PRE_DIV		353
-#define IMX8MQ_CLK_DSI_ESC_DIV			354
+#define IMX8MQ_CLK_DSI_ESC		166
 /* CSI1_CORE */
-#define IMX8MQ_CLK_CSI1_CORE_SRC		355
-#define IMX8MQ_CLK_CSI1_CORE_CG			356
-#define  IMX8MQ_CLK_CSI1_CORE_PRE_DIV		357
-#define IMX8MQ_CLK_CSI1_CORE_DIV		358
+#define IMX8MQ_CLK_CSI1_CORE		167
 /* CSI1_PHY */
-#define IMX8MQ_CLK_CSI1_PHY_REF_SRC		359
-#define IMX8MQ_CLK_CSI1_PHY_REF_CG		360
-#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV		361
-#define IMX8MQ_CLK_CSI1_PHY_REF_DIV		362
+#define IMX8MQ_CLK_CSI1_PHY_REF		168
 /* CSI_ESC */
-#define IMX8MQ_CLK_CSI1_ESC_SRC			363
-#define IMX8MQ_CLK_CSI1_ESC_CG			364
-#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV		365
-#define IMX8MQ_CLK_CSI1_ESC_DIV			366
+#define IMX8MQ_CLK_CSI1_ESC		169
 /* CSI2_CORE */
-#define IMX8MQ_CLK_CSI2_CORE_SRC		367
-#define IMX8MQ_CLK_CSI2_CORE_CG			368
-#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV		369
-#define IMX8MQ_CLK_CSI2_CORE_DIV		370
+#define IMX8MQ_CLK_CSI2_CORE		170
 /* CSI2_PHY */
-#define IMX8MQ_CLK_CSI2_PHY_REF_SRC		371
-#define IMX8MQ_CLK_CSI2_PHY_REF_CG		372
-#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV		373
-#define IMX8MQ_CLK_CSI2_PHY_REF_DIV		374
+#define IMX8MQ_CLK_CSI2_PHY_REF		171
 /* CSI2_ESC */
-#define IMX8MQ_CLK_CSI2_ESC_SRC			375
-#define IMX8MQ_CLK_CSI2_ESC_CG			376
-#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV		377
-#define IMX8MQ_CLK_CSI2_ESC_DIV			378
+#define IMX8MQ_CLK_CSI2_ESC		172
 /* PCIE2_CTRL */
-#define IMX8MQ_CLK_PCIE2_CTRL_SRC		379
-#define IMX8MQ_CLK_PCIE2_CTRL_CG		380
-#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV		381
-#define IMX8MQ_CLK_PCIE2_CTRL_DIV		382
+#define IMX8MQ_CLK_PCIE2_CTRL		173
 /* PCIE2_PHY */
-#define IMX8MQ_CLK_PCIE2_PHY_SRC		383
-#define IMX8MQ_CLK_PCIE2_PHY_CG			384
-#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV		385
-#define IMX8MQ_CLK_PCIE2_PHY_DIV		386
+#define IMX8MQ_CLK_PCIE2_PHY		174
 /* PCIE2_AUX */
-#define IMX8MQ_CLK_PCIE2_AUX_SRC		387
-#define IMX8MQ_CLK_PCIE2_AUX_CG			388
-#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV		389
-#define IMX8MQ_CLK_PCIE2_AUX_DIV		390
+#define IMX8MQ_CLK_PCIE2_AUX		175
 /* ECSPI3 */
-#define IMX8MQ_CLK_ECSPI3_SRC			391
-#define IMX8MQ_CLK_ECSPI3_CG			392
-#define IMX8MQ_CLK_ECSPI3_PRE_DIV		393
-#define IMX8MQ_CLK_ECSPI3_DIV			394
+#define IMX8MQ_CLK_ECSPI3		176
 
 /* CCGR clocks */
-#define IMX8MQ_CLK_A53_ROOT			395
-#define IMX8MQ_CLK_DRAM_ROOT			396
-#define IMX8MQ_CLK_ECSPI1_ROOT			397
-#define IMX8MQ_CLK_ECSPI2_ROOT			398
-#define IMX8MQ_CLK_ECSPI3_ROOT			399
-#define IMX8MQ_CLK_ENET1_ROOT			400
-#define IMX8MQ_CLK_GPT1_ROOT			401
-#define IMX8MQ_CLK_I2C1_ROOT			402
-#define IMX8MQ_CLK_I2C2_ROOT			403
-#define IMX8MQ_CLK_I2C3_ROOT			404
-#define IMX8MQ_CLK_I2C4_ROOT			405
-#define IMX8MQ_CLK_M4_ROOT			406
-#define IMX8MQ_CLK_PCIE1_ROOT			407
-#define IMX8MQ_CLK_PCIE2_ROOT			408
-#define IMX8MQ_CLK_PWM1_ROOT			409
-#define IMX8MQ_CLK_PWM2_ROOT			410
-#define IMX8MQ_CLK_PWM3_ROOT			411
-#define IMX8MQ_CLK_PWM4_ROOT			412
-#define IMX8MQ_CLK_QSPI_ROOT			413
-#define IMX8MQ_CLK_SAI1_ROOT			414
-#define IMX8MQ_CLK_SAI2_ROOT			415
-#define IMX8MQ_CLK_SAI3_ROOT			416
-#define IMX8MQ_CLK_SAI4_ROOT			417
-#define IMX8MQ_CLK_SAI5_ROOT			418
-#define IMX8MQ_CLK_SAI6_ROOT			419
-#define IMX8MQ_CLK_UART1_ROOT			420
-#define IMX8MQ_CLK_UART2_ROOT			421
-#define IMX8MQ_CLK_UART3_ROOT			422
-#define IMX8MQ_CLK_UART4_ROOT			423
-#define IMX8MQ_CLK_USB1_CTRL_ROOT		424
-#define IMX8MQ_CLK_USB2_CTRL_ROOT		425
-#define IMX8MQ_CLK_USB1_PHY_ROOT		426
-#define IMX8MQ_CLK_USB2_PHY_ROOT		427
-#define IMX8MQ_CLK_USDHC1_ROOT			428
-#define IMX8MQ_CLK_USDHC2_ROOT			429
-#define IMX8MQ_CLK_WDOG1_ROOT			430
-#define IMX8MQ_CLK_WDOG2_ROOT			431
-#define IMX8MQ_CLK_WDOG3_ROOT			432
-#define IMX8MQ_CLK_GPU_ROOT			433
-#define IMX8MQ_CLK_HEVC_ROOT			434
-#define IMX8MQ_CLK_AVC_ROOT			435
-#define IMX8MQ_CLK_VP9_ROOT			436
-#define IMX8MQ_CLK_HEVC_INTER_ROOT		437
-#define IMX8MQ_CLK_DISP_ROOT			438
-#define IMX8MQ_CLK_HDMI_ROOT			439
-#define IMX8MQ_CLK_HDMI_PHY_ROOT		440
-#define IMX8MQ_CLK_VPU_DEC_ROOT			441
-#define IMX8MQ_CLK_CSI1_ROOT			442
-#define IMX8MQ_CLK_CSI2_ROOT			443
-#define IMX8MQ_CLK_RAWNAND_ROOT			444
-#define IMX8MQ_CLK_SDMA1_ROOT			445
-#define IMX8MQ_CLK_SDMA2_ROOT			446
-#define IMX8MQ_CLK_VPU_G1_ROOT			447
-#define IMX8MQ_CLK_VPU_G2_ROOT			448
+#define IMX8MQ_CLK_A53_ROOT			177
+#define IMX8MQ_CLK_DRAM_ROOT			178
+#define IMX8MQ_CLK_ECSPI1_ROOT			179
+#define IMX8MQ_CLK_ECSPI2_ROOT			180
+#define IMX8MQ_CLK_ECSPI3_ROOT			181
+#define IMX8MQ_CLK_ENET1_ROOT			182
+#define IMX8MQ_CLK_GPT1_ROOT			183
+#define IMX8MQ_CLK_I2C1_ROOT			184
+#define IMX8MQ_CLK_I2C2_ROOT			185
+#define IMX8MQ_CLK_I2C3_ROOT			186
+#define IMX8MQ_CLK_I2C4_ROOT			187
+#define IMX8MQ_CLK_M4_ROOT			188
+#define IMX8MQ_CLK_PCIE1_ROOT			189
+#define IMX8MQ_CLK_PCIE2_ROOT			190
+#define IMX8MQ_CLK_PWM1_ROOT			191
+#define IMX8MQ_CLK_PWM2_ROOT			192
+#define IMX8MQ_CLK_PWM3_ROOT			193
+#define IMX8MQ_CLK_PWM4_ROOT			194
+#define IMX8MQ_CLK_QSPI_ROOT			195
+#define IMX8MQ_CLK_SAI1_ROOT			196
+#define IMX8MQ_CLK_SAI2_ROOT			197
+#define IMX8MQ_CLK_SAI3_ROOT			198
+#define IMX8MQ_CLK_SAI4_ROOT			199
+#define IMX8MQ_CLK_SAI5_ROOT			200
+#define IMX8MQ_CLK_SAI6_ROOT			201
+#define IMX8MQ_CLK_UART1_ROOT			202
+#define IMX8MQ_CLK_UART2_ROOT			203
+#define IMX8MQ_CLK_UART3_ROOT			204
+#define IMX8MQ_CLK_UART4_ROOT			205
+#define IMX8MQ_CLK_USB1_CTRL_ROOT		206
+#define IMX8MQ_CLK_USB2_CTRL_ROOT		207
+#define IMX8MQ_CLK_USB1_PHY_ROOT		208
+#define IMX8MQ_CLK_USB2_PHY_ROOT		209
+#define IMX8MQ_CLK_USDHC1_ROOT			210
+#define IMX8MQ_CLK_USDHC2_ROOT			211
+#define IMX8MQ_CLK_WDOG1_ROOT			212
+#define IMX8MQ_CLK_WDOG2_ROOT			213
+#define IMX8MQ_CLK_WDOG3_ROOT			214
+#define IMX8MQ_CLK_GPU_ROOT			215
+#define IMX8MQ_CLK_HEVC_ROOT			216
+#define IMX8MQ_CLK_AVC_ROOT			217
+#define IMX8MQ_CLK_VP9_ROOT			218
+#define IMX8MQ_CLK_HEVC_INTER_ROOT		219
+#define IMX8MQ_CLK_DISP_ROOT			220
+#define IMX8MQ_CLK_HDMI_ROOT			221
+#define IMX8MQ_CLK_HDMI_PHY_ROOT		222
+#define IMX8MQ_CLK_VPU_DEC_ROOT			223
+#define IMX8MQ_CLK_CSI1_ROOT			224
+#define IMX8MQ_CLK_CSI2_ROOT			225
+#define IMX8MQ_CLK_RAWNAND_ROOT			226
+#define IMX8MQ_CLK_SDMA1_ROOT			227
+#define IMX8MQ_CLK_SDMA2_ROOT			228
+#define IMX8MQ_CLK_VPU_G1_ROOT			229
+#define IMX8MQ_CLK_VPU_G2_ROOT			230
 
 /* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT			449
-#define IMX8MQ_SYS2_PLL_OUT			450
-#define IMX8MQ_SYS3_PLL_OUT			451
-#define IMX8MQ_DRAM_PLL_OUT			452
-
-#define IMX8MQ_GPT_3M_CLK			453
-
-#define IMX8MQ_CLK_IPG_ROOT			454
-#define IMX8MQ_CLK_IPG_AUDIO_ROOT		455
-#define IMX8MQ_CLK_SAI1_IPG			456
-#define IMX8MQ_CLK_SAI2_IPG			457
-#define IMX8MQ_CLK_SAI3_IPG			458
-#define IMX8MQ_CLK_SAI4_IPG			459
-#define IMX8MQ_CLK_SAI5_IPG			460
-#define IMX8MQ_CLK_SAI6_IPG			461
+#define IMX8MQ_SYS1_PLL_OUT			231
+#define IMX8MQ_SYS2_PLL_OUT			232
+#define IMX8MQ_SYS3_PLL_OUT			233
+#define IMX8MQ_DRAM_PLL_OUT			234
+
+#define IMX8MQ_GPT_3M_CLK			235
+
+#define IMX8MQ_CLK_IPG_ROOT			236
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
+#define IMX8MQ_CLK_SAI1_IPG			238
+#define IMX8MQ_CLK_SAI2_IPG			239
+#define IMX8MQ_CLK_SAI3_IPG			240
+#define IMX8MQ_CLK_SAI4_IPG			241
+#define IMX8MQ_CLK_SAI5_IPG			242
+#define IMX8MQ_CLK_SAI6_IPG			243
 
 /* DSI AHB/IPG clocks */
 /* rxesc clock */
-#define IMX8MQ_CLK_DSI_AHB_SRC                  462
-#define IMX8MQ_CLK_DSI_AHB_CG                   463
-#define IMX8MQ_CLK_DSI_AHB_PRE_DIV              464
-#define IMX8MQ_CLK_DSI_AHB_DIV                  465
+#define IMX8MQ_CLK_DSI_AHB			244
 /* txesc clock */
-#define IMX8MQ_CLK_DSI_IPG_DIV                  466
-
-/* VIDEO2 PLL */
-#define IMX8MQ_VIDEO2_PLL1_REF_SEL		467
-#define IMX8MQ_VIDEO2_PLL1_REF_DIV		468
-#define IMX8MQ_VIDEO2_PLL1			469
-#define IMX8MQ_VIDEO2_PLL1_OUT			470
-#define IMX8MQ_VIDEO2_PLL1_OUT_DIV		471
-#define IMX8MQ_VIDEO2_PLL2			472
-#define IMX8MQ_VIDEO2_PLL2_DIV			473
-#define IMX8MQ_VIDEO2_PLL2_OUT			474
-#define IMX8MQ_CLK_TMU_ROOT			475
-
-#define IMX8MQ_CLK_END				476
+#define IMX8MQ_CLK_DSI_IPG_DIV                  245
+
+#define IMX8MQ_CLK_TMU_ROOT			246
+
+/* Display root clocks */
+#define IMX8MQ_CLK_DISP_AXI_ROOT		247
+#define IMX8MQ_CLK_DISP_APB_ROOT		248
+#define IMX8MQ_CLK_DISP_RTRM_ROOT		249
+
+#define IMX8MQ_CLK_OCOTP_ROOT			250
+
+#define IMX8MQ_CLK_DRAM_ALT_ROOT		251
+#define IMX8MQ_CLK_DRAM_CORE			252
+
+#define IMX8MQ_CLK_MU_ROOT			253
+#define IMX8MQ_VIDEO2_PLL_OUT			254
+
+#define IMX8MQ_CLK_CLKO2			255
+
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
+
+#define IMX8MQ_CLK_CLKO1			257
+#define IMX8MQ_CLK_ARM				258
+
+#define IMX8MQ_CLK_GPIO1_ROOT			259
+#define IMX8MQ_CLK_GPIO2_ROOT			260
+#define IMX8MQ_CLK_GPIO3_ROOT			261
+#define IMX8MQ_CLK_GPIO4_ROOT			262
+#define IMX8MQ_CLK_GPIO5_ROOT			263
+
+#define IMX8MQ_CLK_SNVS_ROOT			264
+#define IMX8MQ_CLK_GIC				265
+
+#define IMX8MQ_CLK_END				266
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h
new file mode 100644
index 0000000000..985f2bbd4d
--- /dev/null
+++ b/include/dt-bindings/usb/pd.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_POWER_DELIVERY_H
+#define __DT_POWER_DELIVERY_H
+
+/* Power delivery Power Data Object definitions */
+#define PDO_TYPE_FIXED		0
+#define PDO_TYPE_BATT		1
+#define PDO_TYPE_VAR		2
+#define PDO_TYPE_APDO		3
+
+#define PDO_TYPE_SHIFT		30
+#define PDO_TYPE_MASK		0x3
+
+#define PDO_TYPE(t)	((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK		0x3ff
+#define PDO_CURR_MASK		0x3ff
+#define PDO_PWR_MASK		0x3ff
+
+#define PDO_FIXED_DUAL_ROLE	(1 << 29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND	(1 << 28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP	(1 << 28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER	(1 << 27) /* Externally powered */
+#define PDO_FIXED_USB_COMM	(1 << 26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP	(1 << 25) /* Data role swap supported */
+#define PDO_FIXED_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_FIXED_CURR_SHIFT	0	/* 10mA units */
+
+#define PDO_FIXED_VOLT(mv)	((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma)	((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags)			\
+	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |		\
+	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT	0	/* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw)			\
+	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |	\
+	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT	0	/* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma)				\
+	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |	\
+	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+#define APDO_TYPE_PPS		0
+
+#define PDO_APDO_TYPE_SHIFT	28	/* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK	0x3
+
+#define PDO_APDO_TYPE(t)	((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT	17	/* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT	8	/* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT	0	/* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK	0xff
+#define PDO_PPS_APDO_CURR_MASK	0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma)	\
+	((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma)					\
+	(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) |		\
+	 PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) |	\
+	 PDO_PPS_APDO_MAX_CURR(max_ma))
+
+ #endif /* __DT_POWER_DELIVERY_H */
diff --git a/include/mxs_nand.h b/include/mxs_nand.h
index 4bd65cded9..ada20483d0 100644
--- a/include/mxs_nand.h
+++ b/include/mxs_nand.h
@@ -66,8 +66,30 @@ struct mxs_nand_info {
 	/* DMA descriptors */
 	struct mxs_dma_desc	**desc;
 	uint32_t		desc_index;
+
+	/* Hardware BCH interface and randomizer */
+	u32 en_randomizer;
+	u32 writesize;
+	u32 oobsize;
+	u32 bch_flash0layout0;
+	u32 bch_flash0layout1;
+};
+
+struct mxs_nand_layout {
+	u32 nblocks;
+	u32 meta_size;
+	u32 data0_size;
+	u32 ecc0;
+	u32 datan_size;
+	u32 eccn;
 };
 
 int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
 int mxs_nand_init_spl(struct nand_chip *nand);
 int mxs_nand_setup_ecc(struct mtd_info *mtd);
+
+void mxs_nand_mode_fcb(struct mtd_info *mtd);
+void mxs_nand_mode_normal(struct mtd_info *mtd);
+u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd);
+u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd);
+void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l);