Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/04May2020

- Support 64-bit U-Boot as the payload for coreboot x86

16 files changed, 183 insertions, 42 deletions

diff --git a/Makefile b/Makefile
index 6bb9cf55f2..cc99873062 100644
--- a/Makefile
+++ b/Makefile
@@ -926,6 +926,9 @@ ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
 ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
 endif
+ifeq ($(CONFIG_SYS_COREBOOT)$(CONFIG_SPL),yy)
+ALL-$(CONFIG_BINMAN) += u-boot-x86-with-spl.bin
+endif
 
 # Build a combined spl + u-boot image for sunxi
 ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
@@ -1626,6 +1629,9 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
 endif
 endif
 
+u-boot-x86-with-spl.bin: spl/u-boot-spl.bin u-boot.bin FORCE
+	$(call if_changed,binman)
+
 ifneq ($(CONFIG_TEGRA),)
 ifneq ($(CONFIG_BINMAN),)
 # Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 307267a8fb..ee0499f5d7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
 obj-$(CONFIG_INTEL_TANGIER) += tangier/
 obj-$(CONFIG_APIC) += lapic.o ioapic.o
-obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
 obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
 obj-$(CONFIG_QFW) += qfw_cpu.o
+ifndef CONFIG_SYS_COREBOOT
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
+endif
 ifndef CONFIG_$(SPL_)X86_64
 obj-$(CONFIG_SMP) += mp_init.o
 endif
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index c8e6a889d0..497d6284ac 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -25,5 +25,6 @@ config SYS_COREBOOT
 	imply FS_CBFS
 	imply CBMEM_CONSOLE
 	imply X86_TSC_READ_BASE
+	select BINMAN if X86_64
 
 endif
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 35b15bb1da..605f90304e 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -11,8 +11,14 @@
 # (C) Copyright 2002
 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
 
+ifndef CONFIG_SPL
 obj-y += car.o
+endif
+ifdef CONFIG_SPL_BUILD
+obj-y += coreboot_spl.o
+else
+obj-y += sdram.o
+endif
 obj-y += coreboot.o
 obj-y += tables.o
-obj-y += sdram.o
 obj-y += timestamp.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 0c4c6348d1..624caf67a6 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -27,7 +27,8 @@ int arch_cpu_init(void)
 
 	timestamp_init();
 
-	return x86_cpu_init_f();
+	return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+		 x86_cpu_init_f();
 }
 
 int checkcpu(void)
diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c
new file mode 100644
index 0000000000..36661871e9
--- /dev/null
+++ b/arch/x86/cpu/coreboot/coreboot_spl.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#include <common.h>
+#include <init.h>
+
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8526e856d7..2e5d0ddd9f 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -290,3 +290,28 @@ int reserve_arch(void)
 	return 0;
 }
 #endif
+
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+	u32 *ptr, *end;
+
+	size /= 4;
+	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+		if (*ptr == 0x4f49424c) /* "LBIO" */
+			return (long)ptr;
+	}
+
+	return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+	long addr;
+
+	/* We look for LBIO in the first 4K of RAM and again at 960KB */
+	addr = detect_coreboot_table_at(0x0, 0x1000);
+	if (addr < 0)
+		addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+	return addr;
+}
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 0312a26bbb..435e50edad 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -24,6 +24,7 @@
 #include <malloc.h>
 #include <spl.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
@@ -447,31 +448,6 @@ int x86_cpu_init_f(void)
 	return 0;
 }
 
-long detect_coreboot_table_at(ulong start, ulong size)
-{
-	u32 *ptr, *end;
-
-	size /= 4;
-	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
-		if (*ptr == 0x4f49424c) /* "LBIO" */
-			return (long)ptr;
-	}
-
-	return -ENOENT;
-}
-
-long locate_coreboot_table(void)
-{
-	long addr;
-
-	/* We look for LBIO in the first 4K of RAM and again at 960KB */
-	addr = detect_coreboot_table_at(0x0, 0x1000);
-	if (addr < 0)
-		addr = detect_coreboot_table_at(0xf0000, 0x1000);
-
-	return addr;
-}
-
 int x86_cpu_reinit_f(void)
 {
 	setup_identity();
@@ -638,16 +614,6 @@ int cpu_jump_to_64bit_uboot(ulong target)
 
 	func = (func_t)ptr;
 
-	/*
-	 * Copy U-Boot from ROM
-	 * TODO(sjg@chromium.org): Figure out a way to get the text base
-	 * correctly here, and in the device-tree binman definition.
-	 *
-	 * Also consider using FIT so we get the correct image length and
-	 * parameters.
-	 */
-	memcpy((char *)target, (char *)0xfff00000, 0x100000);
-
 	/* Jump to U-Boot */
 	func((ulong)pgtable, 0, (ulong)target);
 
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 1736bd2b53..374803b876 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o
 
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SYS_COREBOOT
 obj-y += cpu_from_spl.o
 endif
 endif
+endif
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 90925e46ea..4b64339f25 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -53,6 +53,7 @@ int misc_init_r(void)
 	return 0;
 }
 
+#ifndef CONFIG_SYS_COREBOOT
 int checkcpu(void)
 {
 	return 0;
@@ -62,6 +63,7 @@ int print_cpuinfo(void)
 {
 	return 0;
 }
+#endif
 
 int x86_cpu_reinit_f(void)
 {
diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi
new file mode 100644
index 0000000000..38efc48d83
--- /dev/null
+++ b/arch/x86/dts/coreboot-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <config.h>
+
+/ {
+	binman {
+		filename = "u-boot-x86-with-spl.bin";
+		u-boot-spl {
+		};
+		u-boot {
+			offset = <0x10000>;
+		};
+	};
+};
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 90baec2a17..212b4d596d 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -63,7 +63,7 @@ static int x86_spl_init(void)
 	 * is not needed. We could make this a CONFIG option or perhaps
 	 * place it immediately below CONFIG_SYS_TEXT_BASE.
 	 */
-	char *ptr = (char *)0x110000;
+	__maybe_unused char *ptr = (char *)0x110000;
 #else
 	struct udevice *punit;
 #endif
@@ -111,7 +111,8 @@ static int x86_spl_init(void)
 			      __func__, ret);
 	}
 
-#ifndef CONFIG_TPL
+#ifndef CONFIG_SYS_COREBOOT
+# ifndef CONFIG_TPL
 	memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
 
 	/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
@@ -140,7 +141,7 @@ static int x86_spl_init(void)
 		return ret;
 	}
 	mtrr_commit(true);
-#else
+# else
 	ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
 	if (ret)
 		debug("Could not find PUNIT (err=%d)\n", ret);
@@ -148,6 +149,7 @@ static int x86_spl_init(void)
 	ret = set_max_freq();
 	if (ret)
 		debug("Failed to set CPU frequency (err=%d)\n", ret);
+# endif
 #endif
 
 	return 0;
@@ -162,7 +164,7 @@ void board_init_f(ulong flags)
 		debug("Error %d\n", ret);
 		panic("x86_spl_init fail");
 	}
-#ifdef CONFIG_TPL
+#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
 	gd->bd = malloc(sizeof(*gd->bd));
 	if (!gd->bd) {
 		printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
@@ -207,6 +209,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
 	spl_image->os = IH_OS_U_BOOT;
 	spl_image->name = "U-Boot";
 
+	if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
+		/*
+		 * Copy U-Boot from ROM
+		 * TODO(sjg@chromium.org): Figure out a way to get the text base
+		 * correctly here, and in the device-tree binman definition.
+		 *
+		 * Also consider using FIT so we get the correct image length
+		 * and parameters.
+		 */
+		memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
+		       0x100000);
+	}
+
 	debug("Loading to %lx\n", spl_image->load_addr);
 
 	return 0;
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index 188906b080..a05673bb0b 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/coreboot/coreboot/
 F:	include/configs/chromebook_link.h
 F:	configs/coreboot_defconfig
+
+COREBOOT64 BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/coreboot/coreboot/
+F:	include/configs/chromebook_link.h
+F:	configs/coreboot64_defconfig
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175b37..9edcf8d74e 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -15,6 +15,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+__maybe_unused void print_cpu_word_size(void)
+{
+	printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
+}
+
 __maybe_unused
 static void print_num(const char *name, ulong value)
 {
@@ -208,6 +213,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_baudrate();
 	print_num("relocaddr", gd->relocaddr);
 	board_detail();
+	print_cpu_word_size();
+
 	return 0;
 }
 
@@ -227,6 +234,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -252,6 +260,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("fdt_blob", (ulong)gd->fdt_blob);
 	print_num("new_fdt", (ulong)gd->new_fdt);
 	print_num("fdt_size", (ulong)gd->fdt_size);
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -283,6 +292,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -294,6 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_std_bdinfo(gd->bd);
 	print_num("relocaddr", gd->relocaddr);
 	print_num("reloc off", gd->reloc_off);
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -354,6 +365,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 #endif
 	if (gd->fdt_blob)
 		print_num("fdt_blob", (ulong)gd->fdt_blob);
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -368,6 +380,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_bi_flash(bd);
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
+
 	return 0;
 }
 
@@ -388,6 +402,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_mhz("ethspeed",	    bd->bi_ethspeed);
 #endif
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -405,6 +420,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
 	print_num("FB base  ", gd->fb_base);
 #endif
+	print_cpu_word_size();
+
 	return 0;
 }
 
@@ -419,6 +436,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_bi_dram(bd);
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -435,6 +453,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("reloc off", gd->reloc_off);
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
@@ -448,6 +467,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_bi_mem(bd);
 	print_eth_ip_addr();
 	print_baudrate();
+	print_cpu_word_size();
 
 	return 0;
 }
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
new file mode 100644
index 0000000000..80353b8eb3
--- /dev/null
+++ b/configs/coreboot64_defconfig
@@ -0,0 +1,48 @@
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0x1120000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_X86_RUN_64BIT=y
+CONFIG_VENDOR_COREBOOT=y
+CONFIG_TARGET_COREBOOT=y
+CONFIG_SPL_TEXT_BASE=0x1110000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_PCI_PNP is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index fd974229eb..9c44c025a4 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot:
 At present it seems that for Minnowboard Max, coreboot does not pass through
 the video information correctly (it always says the resolution is 0x0). This
 works correctly for link though.
+
+64-bit U-Boot
+-------------
+
+In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
+produces an image which can be booted from coreboot (32-bit). Internally it
+works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
+can be useful for running UEFI applications, for example.
+
+This has only been lightly tested.