| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | HSD #15012971876: ddr: altera: n5x: Fix compilation warningrel_socfpga_v2022.10_23.03.03_pr | Lokanathan, Raaj | 2023-03-14 | 1 | -26/+26 |
| * | HSD #14016045851: misc: socfpga_secreg: Fix compilation warningrel_socfpga_v2022.10_23.03.02_pr | Lokanathan, Raaj | 2023-03-01 | 1 | -1/+1 |
| * | HSD #14016045851: misc: socfpga_secreg: Enable masking supportrel_socfpga_v2022.10_23.03.01_pr | Lokanathan, Raaj | 2023-02-27 | 1 | -9/+39 |
| * | HSD #15011830300: ddr: altera: agilex: Update data rate based on HMC rate and... | Sin Hui Kho | 2022-12-16 | 2 | -2/+23 |
| * | usb: gadget: dfu: Fix the unchecked length field | Venkatesh Yadav Abbarapu | 2022-12-14 | 1 | -21/+37 |
| * | HSD #15011972255: drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash | Teik Heng Chong | 2022-12-09 | 1 | -0/+5 |
| * | drivers: nand: Move the following nand drivers to nand framework objects | Lokanathan, Raaj | 2022-10-12 | 1 | -4/+4 |
| * | drivers: fpga: Follow mainline to pass compatible flags to fpga_load | Lokanathan, Raaj | 2022-10-12 | 1 | -1/+2 |
| * | HSD #15011817806: fs-loader: Perform code cleanups on fs-loader driver | Lokanathan, Raaj | 2022-10-11 | 1 | -8/+5 |
| * | HSD #18022972407: drivers: clk: Update comment to describe pll bypass | Jit Loon Lim | 2022-10-11 | 2 | -4/+10 |
| * | spi: Remove speed and mode from spi_flash_probe_bus_cs | Lokanathan, Raaj | 2022-10-06 | 1 | -2/+0 |
| * | spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode | Patrice Chotard | 2022-10-06 | 1 | -2/+16 |
| * | spi: spi-uclass: Add new spi_get_bus_and_cs() implementation | Patrice Chotard | 2022-10-06 | 1 | -16/+2 |
| * | configs: socfpga: Define the correct ref clock for the QSPI driver | Lokanathan, Raaj | 2022-10-06 | 1 | -3/+0 |
| * | Added correction for is_ddr_init and reset_type_print | Lokanathan, Raaj | 2022-10-06 | 1 | -73/+27 |
| * | ddr: altera: n5x: Include DDR4 for the same hardcoding settings | Tien Fong Chee | 2022-10-06 | 1 | -16/+12 |
| * | ddr: altera: n5x: Fixing debug log typo | Tien Fong Chee | 2022-10-06 | 1 | -4/+4 |
| * | ddr: altera: n5x: Ensure 'cal->header.data_len' is validated | Tien Fong Chee | 2022-10-06 | 1 | -8/+35 |
| * | ddr: altera: n5x: Ensure correct size of result for correct type casting | Tien Fong Chee | 2022-10-06 | 1 | -4/+4 |
| * | ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set | Tien Fong Chee | 2022-10-06 | 1 | -4/+7 |
| * | ddr: altera: n5x: Return error if invalid DDR type is detected in argument | Tien Fong Chee | 2022-10-06 | 1 | -0/+3 |
| * | ddr: altera: n5x: Checking DDR init hang before reset due to watchdog | Tien Fong Chee | 2022-10-06 | 1 | -8/+21 |
| * | ddr: altera: n5x: Checking DDR DBE | Tien Fong Chee | 2022-10-06 | 1 | -9/+23 |
| * | arm: socfpga: n5x: Update DDR init progress bit | Tien Fong Chee | 2022-10-06 | 1 | -0/+16 |
| * | ddr: altera: n5x: Add self-refresh support in DDR4 | Tien Fong Chee | 2022-10-06 | 1 | -42/+725 |
| * | ddr: altera: Add SDRAM driver for Intel N5X device from mainline | Lokanathan, Raaj | 2022-10-06 | 1 | -824/+97 |
| * | HSD #18020445323-10: arm: dts: soc64: Move OCRAM CCU config to DTS | Tien Fong Chee | 2022-10-06 | 1 | -18/+0 |
| * | HSD #18020445323-7: ddr: altera: agilex: Remove code redundancy | Tien Fong Chee | 2022-10-06 | 1 | -4/+1 |
| * | HSD #18020445323-3: arm: dts: s10: Move CCU config of DDR to DTS | Tien Fong Chee | 2022-10-06 | 1 | -44/+0 |
| * | mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl | Lokanathan, Raaj | 2022-10-06 | 1 | -2/+4 |
| * | Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver | Lokanathan, Raaj | 2022-10-06 | 1 | -0/+1 |
| * | HSD #15010294106: spl: fit: nand: fix fit loading on bad blocks | Tien Fong Chee | 2022-10-06 | 1 | -7/+35 |
| * | HSD #1509758009-2: i2c: designware_i2c: Remove clk disabled codes | Tien Fong Chee | 2022-10-06 | 1 | -5/+0 |
| * | HSD# 14014664649: spi: designware: add support for bits-per-word DT binding | Matthew Gerlach | 2022-10-06 | 1 | -2/+14 |
| * | HSD #22011135953-5: arm: socfpga: Enhance checking on potential overwrite | Tien Fong Chee | 2022-10-06 | 1 | -3/+4 |
| * | ddr: altera: n5x: Include DDR4 for the same hardcoding settings | Tien Fong Chee | 2022-10-06 | 1 | -69/+10 |
| * | ddr: altera: n5x: Fixing debug log typo | Tien Fong Chee | 2022-10-06 | 1 | -6/+6 |
| * | HSD #22011135953-2: misc: socfpga_secreg: Enable register settings in DTS | Tien Fong Chee | 2022-10-06 | 3 | -0/+97 |
| * | drivers: fpga: Add FPGA configuration during bootm for Intel SOCFPGA | Yau Wai Gan | 2022-10-06 | 1 | -0/+40 |
| * | ddr: altera: n5x: Ensure 'cal->header.data_len' is validated | Tien Fong Chee | 2022-10-06 | 1 | -8/+36 |
| * | ddr: altera: n5x: Ensure correct size of result for correct type casting | Tien Fong Chee | 2022-10-06 | 1 | -4/+4 |
| * | ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set | Tien Fong Chee | 2022-10-06 | 1 | -4/+7 |
| * | ddr: altera: n5x: Return error if invalid DDR type is detected in argument | Tien Fong Chee | 2022-10-06 | 1 | -0/+3 |
| * | ddr: altera: n5x: Checking DDR init hang before reset due to watchdog | Tien Fong Chee | 2022-10-06 | 1 | -8/+21 |
| * | ddr: altera: n5x: Checking DDR DBE | Tien Fong Chee | 2022-10-06 | 1 | -9/+24 |
| * | arm: socfpga: n5x: Update DDR init progress bit | Tien Fong Chee | 2022-10-06 | 1 | -0/+16 |
| * | drivers: fpga: intel_pr: enable illegal request detection | Chew, Chiau Ee | 2022-10-06 | 1 | -9/+45 |
| * | HSD #1508949110: set/clear reset_req bit before/after PR | Chew, Chiau Ee | 2022-10-06 | 1 | -2/+15 |
| * | ddr: altera: n5x: Add self-refresh support in DDR4 | Tien Fong Chee | 2022-10-06 | 1 | -24/+732 |
| * | HSD #1509063521: net: phy: micrel: Get phy node from phy-handle | Ley Foon Tan | 2022-10-06 | 1 | -2/+9 |
