| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode | Patrice Chotard | 2022-10-06 | 1 | -2/+16 |
| * | spi: spi-uclass: Add new spi_get_bus_and_cs() implementation | Patrice Chotard | 2022-10-06 | 2 | -20/+10 |
| * | configs: socfpga: Define the correct ref clock for the QSPI driver | Lokanathan, Raaj | 2022-10-06 | 3 | -3/+13 |
| * | HSD 15011662064: Remove "x1" register to follow mainline changes | Lokanathan, Raaj | 2022-10-06 | 1 | -1/+1 |
| * | Added correction for is_ddr_init and reset_type_print | Lokanathan, Raaj | 2022-10-06 | 1 | -73/+27 |
| * | ddr: altera: n5x: Include DDR4 for the same hardcoding settings | Tien Fong Chee | 2022-10-06 | 1 | -16/+12 |
| * | ddr: altera: n5x: Fixing debug log typo | Tien Fong Chee | 2022-10-06 | 1 | -4/+4 |
| * | ddr: altera: n5x: Ensure 'cal->header.data_len' is validated | Tien Fong Chee | 2022-10-06 | 1 | -8/+35 |
| * | ddr: altera: n5x: Ensure correct size of result for correct type casting | Tien Fong Chee | 2022-10-06 | 1 | -4/+4 |
| * | ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set | Tien Fong Chee | 2022-10-06 | 1 | -4/+7 |
| * | ddr: altera: n5x: Return error if invalid DDR type is detected in argument | Tien Fong Chee | 2022-10-06 | 1 | -0/+3 |
| * | ddr: altera: n5x: Checking DDR init hang before reset due to watchdog | Tien Fong Chee | 2022-10-06 | 1 | -8/+21 |
| * | ddr: altera: n5x: Checking DDR DBE | Tien Fong Chee | 2022-10-06 | 1 | -9/+23 |
| * | arm: socfpga: n5x: Update DDR init progress bit | Tien Fong Chee | 2022-10-06 | 1 | -0/+16 |
| * | ddr: altera: n5x: Add self-refresh support in DDR4 | Tien Fong Chee | 2022-10-06 | 2 | -42/+726 |
| * | ddr: altera: Add SDRAM driver for Intel N5X device from mainline | Lokanathan, Raaj | 2022-10-06 | 2 | -828/+97 |
| * | HSD #18020445323-10: arm: dts: soc64: Move OCRAM CCU config to DTS | Tien Fong Chee | 2022-10-06 | 3 | -18/+22 |
| * | HSD #18020445323-9: arm: dts: agilex: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-10-06 | 1 | -0/+18 |
| * | HSD #18020445323-8: arm: dts: agilex: Add fpga2sdram FW settings | Tien Fong Chee | 2022-10-06 | 1 | -0/+32 |
| * | HSD #18020445323-7: ddr: altera: agilex: Remove code redundancy | Tien Fong Chee | 2022-10-06 | 1 | -4/+1 |
| * | HSD #18020445323-6: arm: dts: s10: Move CCU config of OCRAM to DTS | Tien Fong Chee | 2022-10-06 | 2 | -6/+4 |
| * | HSD #18020445323-5: arm: dts: s10: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-10-06 | 1 | -0/+18 |
| * | HSD #18020445323-4: arm: dts: s10: Add fpga2sdram FW settings | Tien Fong Chee | 2022-10-06 | 1 | -0/+84 |
| * | HSD #18020445323-3: arm: dts: s10: Move CCU config of DDR to DTS | Tien Fong Chee | 2022-10-06 | 2 | -44/+27 |
| * | HSD #18020445323-2: arm: dts: Add comments for all accesses config in DTS | Tien Fong Chee | 2022-10-06 | 4 | -4/+17 |
| * | HSD #18020445323-1: doc: dtbinding: Improve doc description | Tien Fong Chee | 2022-10-06 | 1 | -12/+382 |
| * | HSD #18016393902: doc: README.socfpga: Add Git branch releases convention | Sin Hui Kho | 2022-10-06 | 1 | -11/+41 |
| * | HSD #14016754550: arch: arm: dts: Align kernel.itb load and entry address | Dinesh Maniyam | 2022-10-06 | 1 | -3/+3 |
| * | HSD #18021819983: configs: socfpga: Change load address to 0x02000000 | Dinesh Maniyam | 2022-10-06 | 7 | -0/+7 |
| * | Remove the duplicated SYS_LOAD_ADDR config from Kconfig | Lokanathan, Raaj | 2022-10-06 | 1 | -14/+0 |
| * | HSD #15011081322: arm: socfpga: Add new QSPI clock path of Linux DTB | Sin Hui Kho | 2022-10-06 | 1 | -6/+10 |
| * | mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl | Lokanathan, Raaj | 2022-10-06 | 1 | -2/+4 |
| * | HSD #18021819983: arm64: dts: Increase reserved memory size to 32MB | Dinesh Maniyam | 2022-10-06 | 2 | -3/+3 |
| * | CVE-2022-30767: unbounded memcpy with a failed length check This patch tries ... | Lokanathan, Raaj | 2022-10-06 | 1 | -2/+0 |
| * | HSD #14015806978: arm: dts: a10: Remove hardcoded handoff info for A10 NAND &... | Lokanathan, Raaj | 2022-10-06 | 8 | -1142/+134 |
| * | HSD #18019787883: arm: socfpga: Expand the help text for the bridge command. | Lokanathan, Raaj | 2022-10-06 | 1 | -2/+3 |
| * | HSD#15010839051: configs: increase CONFIG_SYS_BOOTM_LEN to support kernel > 32MB | Kah Jing Lee | 2022-10-06 | 1 | -0/+1 |
| * | HSD#15010839051: configs: add env. variable to support compressed kernel in q... | Kah Jing Lee | 2022-10-06 | 1 | -0/+2 |
| * | HSD #15010938416: arm: dts: soc64: changing DDR aliasing addresses | Tien Fong Chee | 2022-10-06 | 3 | -7/+70 |
| * | doc: README.socfpga: Add official boot flow support info | Yau Wai Gan | 2022-10-06 | 1 | -0/+28 |
| * | doc: README.socfpga: Update for U-boot 2022.04 | Lokanathan, Raaj | 2022-10-06 | 1 | -26/+6 |
| * | Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver | Lokanathan, Raaj | 2022-10-06 | 1 | -0/+1 |
| * | Enable fs_loader compilation at SPL Level for socfpga defconfigs | Lokanathan, Raaj | 2022-10-06 | 5 | -0/+5 |
| * | configs: socfpga: Follow mainline to rename SPL_CRC32_SUPPORT to SPL_CRC32 | Lokanathan, Raaj | 2022-10-06 | 3 | -3/+3 |
| * | Follow mainline to convert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig | Lokanathan, Raaj | 2022-10-06 | 2 | -0/+3 |
| * | Follow mainline to convert CONFIG_SYS_LOAD_ADDR to Kconfig | Lokanathan, Raaj | 2022-10-06 | 5 | -8/+16 |
| * | HSD #16015333053: configs: socfpga: Disable QSPI config in SPL of CV defconfig | Lokanathan, Raaj | 2022-10-06 | 1 | -0/+1 |
| * | HSD #15010294106: spl: fit: nand: fix fit loading on bad blocks | Tien Fong Chee | 2022-10-06 | 1 | -7/+35 |
| * | HSD #1509758009-3: Enable I2C as default for Arria 10 defconfig | Tien Fong Chee | 2022-10-06 | 1 | -0/+3 |
| * | HSD #15010208928: arm: socfpga: a10: Enable double peripheral RBF config | Tien Fong Chee | 2022-10-06 | 3 | -1/+4 |
