| Commit message (Expand) | Author | Age | Files | Lines |
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| * | HSD #15011972255: drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flashrel_socfpga_v2022.04_23.02.02_prrel_socfpga_v2022.04_23.02.01_prrel_socfpga_v2022.04_23.01.02_prrel_socfpga_v2022.04_23.01.01_prrel_socfpga_v2022.04_22.12.02_prrel_socfpga_v2022.04_22.12.01_prrel_socfpga_v2022.04_22.11.02_prsocfpga_v2022.04 | Teik Heng Chong | 2022-11-10 | 1 | -0/+5 |
| * | fs/squashfs: sqfs_read: Prevent arbitrary code executionQPDS22.1STD_REL_GSRD_PR | Miquel Raynal | 2022-11-02 | 2 | -4/+8 |
| * | net: nfs: Fix CVE-2022-30767 (old CVE-2019-14196) | Andrea zi0Black Cappa | 2022-11-02 | 1 | -3/+1 |
| * | arm: socfpga: Add bsp-generator scripts with qts-filterrel_socfpga_v2022.04_22.11.01_pr | Kah Jing Lee | 2022-10-18 | 10 | -60/+1986 |
| * | HSD #18018343739: Add TSE PCS supportrel_socfpga_v2022.04_22.10.02_pr | Lokanathan, Raaj | 2022-10-04 | 6 | -9/+374 |
| * | HSD #18023245840: doc: Add the link for the documentation of the .its | Lokanathan, Raaj | 2022-10-04 | 1 | -0/+3 |
| * | jenkins: Enable PR CI/CD | Boon Khai Ng | 2022-10-03 | 1 | -0/+242 |
| * | HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses"rel_socfpga_v2022.04_22.10.01_prrel_socfpga_v2022.04_22.09.03_prQPDS22.3_REL_GSRD_PR | Lokanathan, Raaj | 2022-09-20 | 3 | -66/+6 |
| * | configs: socfpga: Remove SPL SPI related configs from Cyclone V | Lokanathan, Raaj | 2022-09-08 | 1 | -0/+4 |
| * | HSD #14016599689: arm: arria10: Add correct mask bits for RTRIM and PU_DRV_STRG | Lokanathan, Raaj | 2022-09-08 | 1 | -2/+2 |
| * | HSD #16018042241: arm: dts: arria10: Increase boot partition size for NAND | Teoh Ji Sheng | 2022-09-08 | 1 | -2/+2 |
| * | HSD #18019005734: arch: arm: mach-socfpga: SDM Doorbell Issue Fixrel_socfpga_v2022.04_22.09.02_pr | Yuslaimi, Alif Zakuan | 2022-08-30 | 1 | -10/+5 |
| * | HSD #18023002776: drivers: spi: Add MT25U01G part number for SPI NOR Flash | Jit Loon Lim | 2022-08-30 | 1 | -0/+1 |
| * | drivers: mtd: spi: Add support for IS25WP01G SPI NOR flash | Teik Heng Chong | 2022-08-16 | 1 | -0/+2 |
| * | HSD #14016953396: rsu: ignore fw cpb errors after fixing cpbsrel_socfpga_v2022.04_RC_22.08.02_pr | Radu Bacrau | 2022-07-27 | 1 | -2/+6 |
| * | HSD #14016896875: rsu: fix cpb header | Radu Bacrau | 2022-07-27 | 1 | -1/+1 |
| * | HSD #18022972407: drivers: clk: Update comment to describe pll bypass | Jit Loon Lim | 2022-07-25 | 2 | -4/+10 |
| * | drivers: mtd: spi: Add support for MX66U1G45G SPI NOR flash | Teik Heng Chong | 2022-07-25 | 1 | -0/+2 |
| * | Merge branch 'socfpga_v2022.04_RC' of https://github.com/intel-innersource/ap... | Lokanathan, Raaj | 2022-07-22 | 27 | -146/+692 |
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| | * | HSD #18020445323-10: arm: dts: soc64: Move OCRAM CCU config to DTS | Tien Fong Chee | 2022-07-22 | 3 | -18/+22 |
| | * | HSD #18020445323-9: arm: dts: agilex: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-07-22 | 1 | -0/+18 |
| | * | HSD #18020445323-8: arm: dts: agilex: Add fpga2sdram FW settings | Tien Fong Chee | 2022-07-22 | 1 | -0/+32 |
| | * | HSD #18020445323-7: ddr: altera: agilex: Remove code redundancy | Tien Fong Chee | 2022-07-22 | 1 | -4/+1 |
| | * | HSD #18020445323-6: arm: dts: s10: Move CCU config of OCRAM to DTS | Tien Fong Chee | 2022-07-22 | 2 | -6/+4 |
| | * | HSD #18020445323-5: arm: dts: s10: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-07-22 | 1 | -0/+18 |
| | * | HSD #18020445323-4: arm: dts: s10: Add fpga2sdram FW settings | Tien Fong Chee | 2022-07-22 | 1 | -0/+84 |
| | * | HSD #18020445323-3: arm: dts: s10: Move CCU config of DDR to DTS | Tien Fong Chee | 2022-07-22 | 2 | -45/+28 |
| | * | HSD #18020445323-2: arm: dts: Add comments for all accesses config in DTS | Tien Fong Chee | 2022-07-22 | 4 | -4/+17 |
| | * | HSD #18020445323-1: doc: dtbinding: Improve doc description | Tien Fong Chee | 2022-07-22 | 1 | -12/+382 |
| | * | HSD #18016393902: doc: README.socfpga: Add Git branch releases convention | Sin Hui Kho | 2022-07-22 | 1 | -11/+41 |
| | * | HSD #14016754550: arch: arm: dts: Align kernel.itb load and entry addressrel_socfpga_v2022.04_RC_22.08.01_pr | Dinesh Maniyam | 2022-07-15 | 1 | -3/+3 |
| | * | i2c: fix stack buffer overflow vulnerability in i2c md command | Nicolas Iooss | 2022-07-14 | 1 | -12/+12 |
| | * | HSD #18021819983: configs: socfpga: Change load address to 0x02000000rel_socfpga_v2022.04_RC_22.07.02_pr | Dinesh Maniyam | 2022-07-06 | 7 | -0/+7 |
| | * | HSD #18021819983: arm64: dts: Increase reserved memory size to 32MB | Dinesh Maniyam | 2022-07-06 | 2 | -4/+4 |
| | * | drivers: clk: Update license for Intel N5X device | Teik Heng Chong | 2022-07-04 | 4 | -8/+8 |
| | * | Remove the duplicated SYS_LOAD_ADDR config from Kconfig | Lokanathan, Raaj | 2022-06-27 | 1 | -14/+0 |
| | * | HSD #15011081322: arm: socfpga: Add new QSPI clock path of Linux DTB | Sin Hui Kho | 2022-06-27 | 1 | -6/+10 |
| | * | intel: n5x: ddr: update licenserel_socfpga_v2022.04_RC_22.07.01_pr | Lokanathan, Raaj | 2022-06-23 | 1 | -2/+2 |
| | * | mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl | Lokanathan, Raaj | 2022-06-23 | 1 | -2/+4 |
| * | | HSD #14016173729: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to BIT[0] | Dinesh Maniyam | 2022-07-22 | 1 | -2/+2 |
| * | | Added correction for is_ddr_init and reset_type_print | Lokanathan, Raaj | 2022-07-22 | 1 | -73/+27 |
| * | | ddr: altera: n5x: Include DDR4 for the same hardcoding settings | Tien Fong Chee | 2022-07-22 | 1 | -16/+12 |
| * | | ddr: altera: n5x: Fixing debug log typo | Tien Fong Chee | 2022-07-22 | 1 | -4/+4 |
| * | | ddr: altera: n5x: Ensure 'cal->header.data_len' is validated | Tien Fong Chee | 2022-07-22 | 1 | -8/+35 |
| * | | ddr: altera: n5x: Ensure correct size of result for correct type casting | Tien Fong Chee | 2022-07-22 | 1 | -4/+4 |
| * | | ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set | Tien Fong Chee | 2022-07-22 | 1 | -4/+7 |
| * | | ddr: altera: n5x: Return error if invalid DDR type is detected in argument | Tien Fong Chee | 2022-07-22 | 1 | -0/+3 |
| * | | ddr: altera: n5x: Checking DDR init hang before reset due to watchdog | Tien Fong Chee | 2022-07-22 | 1 | -8/+21 |
| * | | ddr: altera: n5x: Checking DDR DBE | Tien Fong Chee | 2022-07-22 | 1 | -9/+23 |
| * | | arm: socfpga: n5x: Update DDR init progress bit | Tien Fong Chee | 2022-07-22 | 1 | -0/+16 |
